First International Workshop on
FPGAs for Software Programmers (FSP 2014)
September 1, 2014, Munich, Germany
co-located with
International Conference on Field Programmable Logic and Applications (FPL)

Overview and Scope

The aim of this workshop is to make FPGA and reconfigurable technology accessible to software programmers. Despite their frequently proven power and performance benefits, designing for FPGAs is mostly an engineering discipline carried out by highly trained specialists. With recent progress in high-level synthesis, a first important step towards bringing FPGA technology to potentially millions of software developers was taken. However, to make this happen, there are still important issues to be solved that are in the focus of this workshop.

The FSP Workshop aims at bringing researchers and experts from both academia and industry together to discuss and exchange the latest research advances and future trends. This includes high-level compilation and languages, design automation tools that raise the abstraction level when designing for (heterogeneous) FPGAs and reconfigurable systems and standardized target platforms. This will in particular put focus on the requirements of software developers and application engineers. In addition, a distinctive feature of the workshop will be its cross section through all design levels, ranging from programming down to custom hardware. Thus, the workshop is targeting all those who are interested in understanding the big picture and the potential of domain-specific computing and software-driven FPGA development. In addition, the FSP Workshop shall facilitate collaboration of the different domains.

Topics of the FSP Workshop include, but are not limited to:

  • High-level synthesis and domain-specific languages (DSLs) for FPGAs and heterogeneous systems
  • Mapping approaches and tools for heterogeneous FPGAs
  • Support of hard IP blocks such as embedded processors and memory interfaces
  • Development environments for software engineers (automated tool flows, design frameworks and tools,
       tool interaction)
  • FPGA virtualization (design for portability, resource sharing, hardware abstraction)
  • Design automation technologies for multi-FPGA and heterogeneous systems
  • Methods for leveraging (partial) dynamic reconfiguration to increase performance, flexibility,
       reliability, or programmability
  • Operating system services for FPGA resource management, reliability, security
  • Target hardware design platforms (infrastructure, drivers, portable systems)
  • Overlays (CGRAs, vector processors, ASIP- and GPU-like intermediate fabrics)
  • Applications (embedded computing, signal processing, big data, bio informatics, database acceleration)
  • Directions for collaborations (research proposals, networking, Horizon 2020)


Access ePrint Proceedings here:

Registration Information

Please visit the FPL 2014 homepage ( for registration.

Call for Papers

Download as PDF document.

Paper submission

Perspective authors are invited to submit original contributions (up to six pages) or extended abstracts describing work-in-progress or position papers (extended abstracts should not exceed two pages). All papers should be submitted in PDF file format following the standard IEEE conference template ( Papers may or may not hide author names and affiliation for optional blind reviewing.
All submissions have to be sent via the conference management system EasyChair. Please set up your own personal account if you do not already own an EasyChair account.


Accepted papers will be included in an ePrint proceedings volume with Open Access. Every accepted paper must have at least one author registered to the workshop by the time the camera-ready paper is due. In addition, selected authors will be invited to contribute a chapter for a book project.

Presentation formats

We are seeking contributions for presentation as oral papers (talk) and posters. Note that the presentation format is independent of the paper length (i.e., regular or short paper). While you will be asked to indicate your preferred presentation format when submitting a paper, the program committee may request an alternative format be considered. The program committee will allocate the format of presentations, taking into account the preference of authors and the balance of the program.

Important dates

Submission deadline:June 30, 2014 extended to July 10, 2014 (strict)
Notification of acceptance:July 31, 2014
Camera-ready final version:August 14, 2014

Registration Information

Please visit the FPL 2014 homepage ( for registration.


Monday September 1, 2014
8:45 – 9:00
Welcome and Introduction
9:00 – 9:45
Session 1: Open Source High-Level Synthesis
9:45 – 10:05
Fast-Forward Presentation of Posters
P1: High-Level Design of Portable and Scalable FPGA Accelerators
Markus Weinhardt, Rainer Höckmann, and Thomas Kinder
P3: Stream Processor Generator for HPC to Embedded Applications on FPGA-based System Platform
Kentaro Sano, Hayato Suzuki, Ryo Ito, Tomohiro Ueno, and Satoru Yamamoto
P4: High Level Programming for Heterogeneous Architectures
Oren Segal, Martin Margala, Sai Rahul Chalamalasetti, and Mitch Wright
P6: OpenHEC: A Framework for Application Programmers to Design FPGA-based Systems
Zhilei Chai, Zhibin Wang, Wenmin Yang, Shuai Ding, and Yuanpu Zhang
10:05 – 10:50
Coffee Break and Posters
10:50 – 12:15
Session 2: FPGA Programming for Everyone
11:35 – 11:55
Tools and Techniques for Efficient High-Level System Design on FPGAs
Adrian J. Chung, Kathryn Cobden, Mark Jervis, Martin Langhammer, Bogdan Pasca
12:15 – 13:30
13:30 – 15:00
Session 3: Domain-Specific Methods and Tools
13:30 – 13:50
Enabling FPGAs for the Masses
Janarbek Matai, Dustin Richmond, Dajung Lee, and Ryan Kastner
13:50 – 14:10
Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs
Moritz Schmid, Oliver Reiche, Christian Schmitt, Frank Hannig, and Jürgen Teich
14:10 – 14:30
High Level Hardware/Software Embedded System Design with Redsharc
Sam Skalicky, Andrew G. Schmidt, and Matthew French
15:00 – 15:30
Coffee Break
15:30 – 16:55
Session 4: OpenSPL (organized by Georgi Gaydadjiev, Chalmers University of Technology and Maxeler Technologies)
16:15 – 16:25
Wayne Luk, Imperial College, UK
16:25 – 16:35
Apostolos Dollas, Technical University of Crete, Greece
16:35 – 16:45
Peter Zinterhof, University of Salzburg, Austria
16:45 – 16:55
Carsten Trinitis, TU Munich, Germany
16:55 – 17:00

Invited speakers:

Jason H. Anderson, University of Toronto
"LegUp High-Level Synthesis of Processor/Accelerator FPGA Systems"

Jason Anderson We describe a high-level synthesis (HLS) tool, called LegUp, under active development at the University of Toronto. LegUp accepts a C program as input and automatically compiles the program to a hybrid architecture comprising a processor (a soft-core MIPS or a hardened ARM) and custom hardware accelerators. Results show that the tool produces hardware solutions of comparable quality to a commercial high-level synthesis tool. LegUp is open source and freely downloadable (, providing a powerful platform that can be leveraged for new research on a wide range of HLS and hardware/software co-design topics. The tool has been downloaded by over 1000 groups from around the world since its initial release in March 2011. The talk will overview LegUp's current capabilities, as well as current research underway.

Speaker's bio:
Jason Anderson ( received the B.Sc. degree in computer engineering from the University of Manitoba, and the M.A.Sc. and Ph.D. degrees in electrical and computer engineering (ECE) from the University of Toronto (U of T). He is an Associate Professor with the Department of ECE, U of T. From 1997-2008, he was with the FPGA implementation tools group at Xilinx, Inc., in San Jose, CA, and Toronto, ON. From 2005 to 2008, he managed groups at Xilinx focused on placement, routing, and strategic projects. He became a Principal Engineer at Xilinx in 2007. He joined the ECE Department at Toronto in 2008. Prof. Anderson has received six awards for excellence in undergraduate teaching, three best papers awards, holds 25 U.S. patents, and has authored over 60 papers in refereed journals and symposia. His research interests include all aspects of computer-aided design (CAD), architecture and circuits for FPGAs.

Peter Yiannacouras, Altera
"Beyond C-to-Gates: Enabling Full System Design Using OpenCL"

Peter Yiannacouras Despite the large speed ups and low power achievable through FPGA acceleration, FPGAs remain largely inaccessible to software developers. Recent advancements in high level synthesis allow custom datapaths to be generated from explicitly parallel languages such as OpenCL or from the parallelism extracted automatically from sequential code. These C to gates tools provide only productivity gains for hardware designers, as their output is RTL which still needs to be integrated into a hardware system, timing closed, validated, etc. Additional front end tools, CAD automation, and even physical board specifications are necessary to make FPGAs accessible to software developers. This talk will discuss these and other key challenges in enabling software developers to execute, profile, and iterate on their end application by providing them a development ecosystem which abstracts away the FPGA hardware along with its cumbersome CAD flow.

Speaker's bio:
Peter Yiannacouras received the Ph.D. degree from the Electrical and Computer Engineering Department, University of Toronto, in 2009 researching vector overlay architectures for FPGAs. He is presently a design engineer in the Altera OpenCL Platforms team since 2011 where he fully automates the execution of compiler-generated RTL on arbitrary FPGA acceleration cards. Previous to that he worked at the Nokia Research Center in 2010, and at Intel Microarchitecture Research Labs in 2006.

Oskar Mencer, Maxeler Technologies
"Programming Dataflow Engines and OpenSPL"

Oskar Mencer Dataflow Engines (DFEs) form an hardware abstraction which makes flexible hardware easy to program via a spatial computing infrastructure. OpenSPL ( is a consortium to drive the development of open infrastructure for spatial computing. Advantages of static computing in space are: (1) predictability and reliability of performance (QoS), (2) just-in-time computing, minimizing power consumption via low clock frequency, and (3) the ability to scale computations to ultra large problem sizes more efficiently than commodity memory systems.
In this talk, I will present the current state of programming tools and available hardware infrastructure for computing in space, including real-world application examples, as well as debugging and runtime monitoring infrastructure.

Speaker's bio:
Oskar Mencer is CEO and Founder of Maxeler Technologies and Senior Lecturer at Imperial College London. Prior to Maxeler, Oskar was Member of Technical Staff at the Computing Sciences Center at Bell Labs in Murray Hill. He joined Bell Labs after receiving a PhD from Stanford University. Besides driving Maximum Performance Computing (MPC) at Maxeler, Oskar was also Consulting Professor in Geophysics at Stanford University and has received two Best Paper Awards, an Imperial College Research Excellence Award in 2007 and a Special Award from Com.sult in 2012 for "revolutionising the world of computers".



General Co-Chairs

Frank Hannig, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Dirk Koch, University of Manchester, UK
Daniel Ziener, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany

Program Committee

Hideharu Amano, Keio University, Japan
Jason H. Anderson, University of Toronto, Canada
Gordon Brebner, Xilinx Inc., USA
João M. P. Cardoso, University of Porto, Portugal
Jason Cong, University of California, Los Angeles, USA
Andreas Koch, Technical University of Darmstadt, Germany
Miriam Leeser, Northeastern University, USA
Wayne Luk, Imperial College London, UK
Christian Plessl, University of Paderborn, Germany
Dan Poznanovic, Cray Inc., USA
Rodric Rabbah, IBM Research, USA
Deshanand Singh, Altera Corp., Canada
Satnam Singh, Google Inc., USA
Dirk Stroobandt, Ghent University, Belgium
Kazutoshi Wakabayashi, NEC Corp., Japan
Markus Weinhardt, Osnabrück University of Applied Sciences, Germany