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Codesign
Lehrstuhl für Informatik 12
SystemCoDesigner
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Department Informatik  >  Informatik 12  >  Forschung  >  SystemCoDesigner
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select your optimal design

Almost 80% of all design decisions are taken in the first 20% of the design time. Thus, an early and substantiated knowledge about possible solutions is mandatory to design high quality systems. Aiding in this critical design phase is the mission of SystemCoDesigner. It is a software tool for automatic design space exploration at the electronic system level. Additionally, SystemCoDesigner generates platform-based prototyps of (mixed) hardware/software systems. By exploring the design space, a designer becomes more confident in decisions to be done. To sum up, SystemCoDesigner is a novel EDA tool which covers all aspects from (i) specification over (ii) automatic exploration to (iii) automatic prototype implementation.

The input to SystemCoDesigner is a functional model written in SystemC. Each SystemC module in these models can be refined to different hardware or software implementations. Hardware synthesis can be done using high-level synthesis tools, while software is directly generated from the high-level SystemC model. In the exploration phase, the goal is to optimally allocate resources and bind the SystemC modules onto these allocated resources. During exploration, evaluatin of candidate designs is performed through SystemC simulation. These automatically generated system level performance models permit a fast estimation of latency and throughput numbers by a combined behavioral and timing simulation considering allocation and binding effects. The result of the exploration is a set of Pareto-optimized designs corresponding to different hardware/software implementations. After decision making, i.e., selecting a suitable design out of the optimized set, a prototype implementation of the resulting hardware/software system can be generated. As a proof of concept, the mapping onto Xilinx FPGAs using Xilinx Micro-Blaze softcore processors and automatically synthesized hardware components has been successfully performed for several case-studies.

Features in a Nutshell

+ SystemC front end
+ powerful exploration through multi-objective optimization algorithms
+ fast SystemC performance evaluation
+ graphical result representation
+ automatic Xilinx FPGA back end

SystemCoDesigner flyer

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  Impressum Stand: 14 January 2009.   Ch.H.