Dezember 2009: Veröffentlichung des Abschlussberichts als Buch
Dynamically Reconfigurable Systems - Das Buch zum Schwerpunktprogramm finden Sie hier.
08.09.2008 - 10.09.2008 Internationales Review auf der FPL 2008 ein toller Erfolg für das Schwerpunktprogramm 1148 Rekonfigurierbare Rechensysteme der Deutschen Forschungsgemeinschaft
Das SPP1148 stellte sich einer Herausforderung der ganz besonderen Art auf der FPL 2008 (International Conference on Field Programmable Logic and Applications), die von 8. bis 10. September 2008 in Heidelberg stattfand, siehe
Zu einer Begutachtung außer der Reihe wurden von der Deutschen Forschungsgemeinschaft, vertreten durch Herrn Dr. Michael Lentze, neben einem deutschen Gutachterteam auch internationale Experten aus Forschung und Industrie eingeladen, um am 9. September die Ergebnisse des Schwerpunktprogramms nach 5 Jahren Arbeit seit Beginn im Jahr 2003 zu begutachten.
Dazu haben ca. 20 Mitarbeiter des Schwerpunktprogramms gemeinsame Posterstände mit Demonstratoren aufgebaut, die während der ganzen Konferenz präsent waren, um die Früchte der Kooperationen und gemeinsam erreichten Ergebnisse darzustellen.
Groß gelobt wurde die exzellente Zusammenarbeit zwischen den geförderten Projekten sowie die weite internationale Sichtbarkeit der erzielten Ergebnisse.
10.03.2008 Erfolgreiche CeBIT 2008 Teilnahme: Demo und Vorstellung der Erlangen Slot Machine ESM
Gemeinsames CeBIT 2008 Foto mit der Gruppe von Herrn Dr. Walter Stechele von der TU München. Von links nach rechts:
Herr Walter Stechele, Rafael Pohlig, Christopher Claus, Matthias Kovatsch und Mateusz Majer.
Due to constantly decreasing lifetime of technical products, systems able to be reconfigured at different levels of hardware granularity are becoming more and more important. Only those systems are able to provide optimal solutions for applications with constraints and requirements not clearly defined at design time and for which high redesign time should be avoided.
It is possible with reconfigurable solutions to optimize the production cost of digital products, particularly those produced in low volume.
The expected research results will be used as foundation for the development of self-reconfigurable or self-repairing systems in the feature.
This aim of this project is to overcome the deficiency of design automation of reconfigurable devices, in particular FPGA-based architectures. This goal is likely to be reached by supplying models and optimization methodologies for dynamic hardware reconfiguration. Those models and methods are part of a kind of operating system for hardware reconfiguration in charge of the resource management at run-time.
Concretely, our investigations target mathematical optimization of strategies and methods for the optimal management and use of novel and future generation of reconfigurable hardware. Those reconfigurable chips are currently in used in different technical systems. Due to the practical barrier like the high reconfiguration overhead as well as the lack of theoretical models and methods, the potential of reconfigurable hardware could be only narrowly exploited.
Our goal is to show that existing technologies can be used to overcome many difficulties mentioned above. We are therefore expecting new impulses for the development of new generation of chips.
Modeling of Reconfigurable Systems
Resource requirement as well as reconfigurable resources and reconfigurable chips most be adequately modeled. While the influencing variables in traditional operating systems are well understood, many properties of reconfigurable systems like the number and the kind of reconfigurable resource, the run-time or the reconfiguration overhead are still dubious. However, analogue to the notion of task in the software world, we consequently use the notion of Hardware tasks and Hardware processes to denote requirements. Nevertheless, we have to differentiate between Tasks and Module:
A module represents a hardware reconfiguration which can execute some tasks. With relatively high reconfiguration overhead of modules and short execution time of tasks, it is suitable to maintain module running after the execution of a given tasks for the possible execution of incoming tasks. This example shows that the hardware resource could be adequately modelled. Characteristics like non interruption of hardware tasks, reconfiguration overhead, communication model will be adequately formulated.
Based on the mathematical model, the optimization goal is an efficient resource management. In traditional operating systems the central problems are resource allocation, as well as the temporal resource assignment known as scheduling. Basically, the concepts in software operating system are the same as in reconfigurable hardware. It is only the matter of which optimization algorithms and optimization goals are followed in hardware reconfiguration.
Three different scenarios should be investigated here:
The first one is the optimal resource allocation and scheduling of a given static set of hardware tasks at design time. The two other scenarios assume unknown temporal requirements. While one of the two scenarios consider case with fast changing request, the second scenario target maximum resource utilization by constant load.
Our model of dynamic reconfiguration is made upon a scheduler, an on-line placer and the reconfigurable device. The scheduler manages the tasks and decides when and on which device a task should be executed. Then the task is given to the placer which will try to place it on the device, i.e allocating a set of processing elements (PE) for that task. If the placer is not able to find a site for the new task, then it will be sent back to the scheduler which can decide to send it later or to send another task to the placer.
On-line placement Methods
Run-time space allocation, also known as temporal placement or on-line placement is a central part in reconfigurable computing. For the on-line placement problems, two sub problems have to be solved in order to place a ready to execute task:
Most of the work on on-line placement uses a free space manager to solve sub problem 1. The free space on the device is represented as a set of empty rectangles. For an incoming component, one of the empty rectangles is chosen according to the placement strategy (best-fit, first-fit, etc...) , the task is placed inside the chosen rectangle and the new set of empty rectangles is computed. The main drawback of this method (free space segmentation) is that the set of empty rectangles increases very fast each time a new task is placed, thus making the search for a suitable site (sub problem 2) difficult. Moreover, incoming tasks are handled as independent entities. Therefore the communication aspect is neglected.
- Identifying the set of potential sites to place the new task.
- Selecting the best site to place the component according to a set of given criteria.
Our new approach for on-line placement of components on reconfigurable devices exploits the fact that the set of empty rectangles grows much faster than the set of placed rectangles (tasks) and therefore it is more suitable to manage the occupied space rather than the free space on the device. In real application each task communicates somehow with its environment. This communication is done in form of inputs to and outputs from the tasks. Therefore communication among tasks plays an important role in our placement strategy. The optimization of the communication is an important criterion in finding the solution of sub problem 2.
The methods described below are being investigated in real hardware context. For this purpose, we have implemented an FPGA based reconfigurable platform called Erlangen Slot Machine (ESM).
The ESM is used to implement our different on-line and off-line placement and routing algorithms. More detailed information is available at
We demonstrated the ESM platform at the ARCS2007 conference in Zürich and gave an introductory tutorial to the interested reconfigurable community. The tutorial covered a partial video example as well as the control of the whole reconfiguration through an embedded PowerPC.
Main application for the ESM are video processing applications. Using partial run-time reconfiguration the video processing kernels can be exchanged without disturbance of the whole video processing system.
As application, we also considerer the used of reconfigurable nodes in distributed control system: the so called ReCoNets. We are investigating the ReCoNets requirements when a new task is generated in the network. This is a realistic example which occurs for example in automobile electronic and for which we did some preliminary work.
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