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Department Informatik  >  Informatik 12  >  Forschung  >  ReCoNets
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ReCoNets - Publications

2010
49 J. Teich.
The DFG Priority Program 1148 Reconfigurable Computing - Achievements and Lessons Learned.
DATE Friday Workshop The European Landscape of Reconfigurable Computing: Lessons Learned, new Perspectives and Innovations, Dresden, Germany, March 2010. Invited Talk. ©1
48 C. Haubelt, D. Koch, F. Reimann, T. Streichert and J. Teich.
ReCoNets – Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections.
In Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications, p. 223-244, Springer, Heidelberg, February 2010. 10.1007/978-90-481-3485-4_11. ©1
47 M. Platzner, J. Teich and N. Wehn.
Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications.
Springer, Heidelberg, February 2010. ©1
46 J. Angermeier, C. Bobda, M. Majer and J. Teich.
Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform.
In Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications, p. 51-71, Springer, Heidelberg, February 2010. ©1
45 S. Fekete, T. Kamphans, N. Schweer, C. Tessars, J. van der Veen, A. Ahmadinia, J. Angermeier, D. Koch, M. Majer and J. Teich.
ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices.
In Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications, p. 199-222, Springer, Heidelberg, February 2010. ©1
2009
44 D. Koch, C. Beckhoff and J. Teich.
A Communication Architecture for Complex Runtime Reconfigurable Systems and its Implementation on Spartan-3 FPGAs.
Proceedings of the 17th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2009), pp. 233-236, Monterey, California, USA
Extended paper version:. ©2
43 D. Koch, C. Beckhoff and J. Teich.
Minimizing Internal Fragmentation by Fine-grained Two-dimensional Module Placement for Runtime Reconfigurable Systems.
Proceedings 17th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2009), pp. 251-254, Napa, California, April, 2009. ©1
42 D. Koch, C. Beckhoff and J. Teich.
Hardware Decompression Techniques for FPGA-based Embedded Systems.
ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol.2, no. 9, June 2009. ©1
2008
41 F. Reimann, M. Glaß, M. Lukasiewycz, J. Keinert, C. Haubelt and J. Teich.
Symbolic Voter Placement for Dependability-Aware System Synthesis.
In Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 237-242, Atlanta, GA USA, October 19-24 2008. ©1
40 M. Glaß, M. Lukasiewycz, F. Reimann, C. Haubelt and J. Teich.
Symbolic Reliability Analysis of Self-healing Networked Embedded Systems.
In Proceedings of the 27th International Conference on Computer Safety, Reliability and Security (SAFECOMP 2008), pp. 139-152, Newcastle upon Tyne, UK, September 22-25, 2008. ©1
39 S. Fekete, J. van der Veen, J. Angermeier, D. Koch and J. Teich.
No-Break Dynamic Defragmentation of Reconfigurable Devices.
Proceedings of International Conference on Field-Programmable Logic and Applications (FPL 08), pp. 113-118, Heidelberg, Germany. ©1
38 D. Koch, T. Streichert, C. Haubelt and J. Teich.
Logic Chip, Logic System and Method for Designing a Logic Chip.
Patent PCT/EP2008/007342, filed 8.9.2008. ©1
37 D. Koch, C. Beckhoff and J. Teich.
ReCoBus-Builder – a Novel Tool and Technique to Build Statically and Dynamically Reconfigurable Systems for FPGAs.
Proceedings of International Conference on Field-Programmable Logic and Applications (FPL 08), pp. 119-124, Heidelberg, Germany. ©1
36 D. Koch, T. Streichert, C. Haubelt and J. Teich.
Logic Chip, Method and Computer Program for Providing a Configuration Information for a Configurable Logic Chip.
Patent PCT/EP2008/007343, filed 8.9.2008. ©1
35 D. Koch, C. Haubelt and J. Teich.
Efficient Reconfigurable On-Chip Buses for FPGAs.
Proceedings 16th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2008), pp. 287-290, Palo Alto, California, April 14-15, 2008. ©1
34 M. Glaß, M. Lukasiewycz, F. Reimann, C. Haubelt and J. Teich.
Symbolic Reliability Analysis and Optimization of ECU Networks.
Proceedings of Design, Automation and Test in Europe (DATE 2008), IEEE Computer Society, pp. 158-163, Munich, Germany, March 10-14, 2008. ©1
33 T. Streichert, C. Haubelt, D. Koch and J. Teich.
Concepts for Self-Adaptive and Self-Healing Networked Embedded Systems.
Organic Computing, Rolf Würtz (Ed.), Springer Series Understanding Complex Systems, pp. 241-260, Springer, 2008. ©1
32 R. Brendle, T. Streichert, D. Koch, C. Haubelt and J. Teich.
Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks.
Proceedings of the International Conference on Architecture of Computing Systems (ARCS 2008), pp. 117-129, Dresden, Germany, February 25-28, 2008. ©1
31 T. Streichert, M. Glaß, R. Wanka, C. Haubelt and J. Teich.
Topology-Aware Replica Placement in Fault-Tolerant Embedded Networks.
Proceedings of the International Conference on Architecture of Computing Systems (ARCS 2008), pp. 23-37, Dresden, Germany, February 25-28, 2008. ©1
2007
30 D. Koch, C. Beckhoff and J. Teich.
Bitstream Decompression for High Speed FPGA Configuration from Slow Memories.
In Proceedings of the IEEE International Conference on Field-Programmable Technology 2007 (ICFPT'07), pp. 161-168. ©1
29 T. Streichert, M. Glaß, C. Haubelt and J. Teich.
Design space exploration of reliable networked embedded systems.
In Journal on Systems Architecture (JSA). Volume 53(10): 751-763, 2007. ©1
28 D. Koch, T. Streichert, C. Haubelt and J. Teich.
Efficient Reconfigurable On-Chip Buses.
Europäisches Patent EP07017975, Anmeldetag 13.09.2007. ©1
27 D. Koch, C. Haubelt, T. Streichert and J. Teich.
Modeling and Synthesis of Hardware-Software Morphing.
In Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), pp. 2746-2749, New Orleans, LA, U.S.A., May 2007. ©1
26 F. Dittmann, F. Rammig, M. Streubühr, C. Haubelt, A. Schallenberg and W. Nebel.
Exploration, Partitioning and Simulation of Reconfigurable Systems.
it - Information Technology, http://it-information-technology.de , Oldenbourg Wissenschaftsverlag, vol. 49(3):149-156, 2007. ©1
25 T. Streichert, C. Strengert, D. Koch, C. Haubelt and J. Teich.
Communication Aware Optimization of the Task Binding in Hardware/Software Reconfigurable Networks.
Journal on Integrated Circuits and Systems, Volume 2, Number 1, pp. 29-36, March 2007. ©1
24 D. Koch, C. Haubelt and J. Teich.
Efficient Hardware Checkpointing -- Concepts, Overhead Analysis, and Implementation.
In Proceedings of the 15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2007), Monterey, CA, pp. 188-196, February 18-20, 2007.
Download demo video. ©1
23 N. Bergmann, M. Platzner and J. Teich.
Dynamically Reconfigurable Architectures.
EURASIP Journal of Embedded Systems, Volume 2007 (2007), Article ID 28405, 2 pages, February 2007. ©1
22 M. Busse and T. Streichert.
Time Synchronization.
In Algorithms for Sensor and Ad Hoc Networks; Springer Lecture Notes 4621, pp. 359-380, Springer, 2007. ©1
2006
21 T. Streichert, D. Koch, C. Haubelt and J. Teich.
Modeling and Design of Fault-Tolerant and Self-Adaptive Reconfigurable Networked Embedded Systems.
EURASIP Journal on Embedded Systems, Volume 2006 (2006), Article ID 42168, 15 pages, Hindawi Publishing Corporation. ©1
20 T. Streichert.
Placing Functionality in Fault-Tolerant Hardware/Software Reconfigurable Networks.
In Proceedings of 16th International Conference on Field Programmable Logic and Applications, pp. 927--928, Madrid, Spain, August 28-30, 2006. ©1
19 T. Streichert, C. Strengert, C. Haubelt and J. Teich.
Dynamic Task Binding for Hardware/Software Reconfigurable Networks .
In Proceedings of SBCCI 2006, pages 38-43, Ouro Preto, Brasil, August 28th - September 1st, 2006. ©1
18 T. Streichert, C. Haubelt and J. Teich.
Multi-Objective Topology Optimization for Networked Embedded Systems.
In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2006), pp. 93--98, Samos (Greece), July 17-20, 2006.. ©1
17 D. Koch, M. Körber and J. Teich.
Searching RC5-Keys with Distributed Reconfigurable Computing.
In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA 2006), Las Vegas, USA, June 26-29, 2006. ©1
16 J. Becker, J. Teich, P. Athanas and G. Brebner.
Dynamically Reconfigurable Architectures.
Proceedings of the Dagstuhl Seminar Nº 06141, ISSN 1862 - 4405, Dagstuhl, Germany, April 02-07, 2006. ©1
15 D. Koch, T. Streichert, S. Dittrich, C. Strengert, C. Haubelt and J. Teich.
An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks.
In Proceedings of the 19th International Conference on Architecture of Computing Systems (ARCS 2006), Frankfurt/Main, Germany, pp. 202-216, March 13-16, 2006. ©1
14 J. Teich, C. Haubelt, D. Koch and T. Streichert.
Concepts for Self-Adaptive Automotive Control Architectures.
DATE'06 Friday Workshop Future Trends in Automotive Electronics and Tool Integration, Conference Design Automation and Test in Europe, March 10, 2006, Munich, Germany. ©1
2005
13 A. Ahmadinia, C. Bobda, M. Majer and J. Teich.
Packet Routing in Dynamically Changing Networks on Chip.
In Proceedings of the 12th Reconfigurable Architectures Workshop (RAW 2005), Denver, USA, p. 154b, IEEE Computer Society, April 4-5, 2005. ©1
12 C. Haubelt.
Automated Model-Based Design Space Exploration of Embedded Systems.
PhD Forum at the Design, Automation and Test in Europe (DATE'05), March 7-11, Munich, Germany, 2005. ©1
11 T. Streichert, C. Haubelt and J. Teich.
Distributed HW/SW-Partitioning for Embedded Reconfigurable Systems.
In Proceedings of DATE 2005, Munich, Germany, pp. 894-895, March 7-11, 2005. ©1
10 T. Streichert, C. Haubelt and J. Teich.
Verteilte HW/SW-Partitionierung für fehlertolerante rekonfigurierbare Netzwerke.
In Proceedings of 17. ITG/GI/GMM Workshop für Testmethoden und Zuverlässigkeit und Fehlertoleranz von Schaltungen und Systemen. Innsbruck, Austria, pp. 50-54, February 27 - March 1, 2005. ©1
9 C. Haubelt, S. Otto, C. Grabbe and J. Teich.
A System-Level Approach to Hardware Reconfigurable Systems.
In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC'05). Shanghai, China, pp. 298-301, January 18-21, 2005. ©1
8 T. Streichert, C. Haubelt and J. Teich.
Online Hardware/Software Partitioning in Networked Embedded Systems.
In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC'05). Shanghai, China, pp. 982-985, January 18-21, 2005. ©1
2004
7 A. Ahmadinia, C. Bobda, D. Koch, M. Majer and J. Teich.
A Dynamic NoC Approach for Communication in Reconfigurable Devices.
In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL), Antwerp, Belgium, LNCS 3203, pp. 1032-1036, Springer, August 30 - September 1, 2004. ©1
6 C. Haubelt.
Design Space Exploration for Distributed Hardware Reconfigurable Systems.
In Field-Programmable Logic and Applications by Jürgen Becker, Marco Platzner, and Serge Vernalde (Eds.). In Lecture Notes in Computer Science, Vol. 3203, p. 1171, Springer, Berlin, Heidelberg, 2004. ©1
5 C. Haubelt and J. Teich.
Modeling and Analysis of Distributed Reconfigurable Hardware.
In Dresdener Arbeitstagung Schaltungs- und Systementwurf (DASS 2004), pp. 106-111, Dresden, Germany, April 19-20, 2004. ©1
4 D. Koch and J. Teich.
Platform-Independent Methodology for Partial Reconfiguration.
Proceedings of the 2004 ACM conference Computing Frontiers (CF 04), pp. 398-403, April 14-16, 2004, Ischia, Italy. ©1
2003
3 C. Haubelt, D. Koch and J. Teich.
ReCoNets: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware.
In Proceedings of the 16th Symposium on Integrated Circuits and Systems Design (SBCCI2003), pp. 343-348, São Paulo, Brazil, September 8-11, 2003. ©1
2 R. Feldmann, C. Haubelt, B. Monien and J. Teich.
Fault Tolerance Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques.
In Proceedings of 13th International Conference on Field Programmable Logic and Applications, pp. 478-487, Lisbon, Portugal, September 1-3, 2003. ©1
1 C. Haubelt, D. Koch and J. Teich.
Basic OS Support for Distributed Reconfigurable Hardware.
In Proceedings of the Third International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'03), pp. 18-22, Samos, Greece, July 21-23, 2003, ISBN 90-807957-1-2. ©1

Semester and Diploma Thesis

2006
6 C. Strengert.
Untersuchung von Algorithmen zur Replikaplatzierung in rekonfigurierbaren Netzwerken.
Hardware/Software Co-Design, Dept of Computer Science-12, University of Erlangen-Nuremberg. ©1
2005
5 S. Dittrich.
Konzeption und Implementierung einer Infrastruktur für Betriebssystemdienste wie auch deren Analyse und Umsetzung.
Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, September 2005. ©1
4 G. Bunin.
Implementierung von Bildverarbeitungsalgorithmen für ein Hardware/Software-rekonfigurierbares Netzwerk.
Studienarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Juli 2005. ©1
3 C. Strengert.
Entwurf und Implementierung eines Netzwerkmanagementsystems zur Analyse von Hardware/Software-rekonfigurierbaren Netzwerken.
Studienarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Juli 2005. ©1
2004
2 C. Cao.
Design and Implementation of Packet Routing and Task Migration Strategies in a Reconfigurable Network.
Master Thesis, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, August 2004 . ©1
1 S. Dittrich.
FPGA-basierte Hardware-Software Plattform für eingebettete Systemlösungen.
Studienarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Juni 2004. ©1
  Impressum Stand: 07 January 2009.   D.K.