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Department Informatik  >  Informatik 12  >  Forschung  >  ReCoBus

The Simple Formula for Building Bus-based Reconfigurable Systems


Click here for registering for the FPL ReCoBus-Builder tutorial

ReCoBus Technology in a Nutshell

In order to keep the design complexity in these days FPGA-based systems manageble, higher abstraction levels are becomming obligatory. In future, FPGA designers will have to think more in modules and not so much in look-up tables.

To assist this process, we developed the ReCoBus technology that provides a flexible backplane bus that is highly optimized for regular structured FPGAs. This allows for plugging pre-synthesized modules together in a manner that is comparable to the sytem integration known from PCB-based backplane buses (for example VME, PCI, etc.). The integration of such modules is carried out without any time consuming synthesis runs or place and route iterations. Furthermore, by the use of partial reconfiguration, single modules can be hot-swapped in a few miliseconds at runtime.
Make the best of your FPGA designs and use the ReCoBus technology to improve your systems.
  • Save FPGA area and power
  • Simplify system integration and enhance reusabilty by module encapsulation
  • Utilize partial runtime reconfiguration - whenever possible
  • Speed up your design processes with parallel working teams
  • Avoid long synthesis and P&R runs by using modulear design techniques

Click here for registering for the FPL ReCoBus-Builder tutorial

This project is supported in part by the German Research Foundation (DFG).
  Impressum Stand: 22 June 2009.   D.K.