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Lehrstuhl für Informatik 12
Multi-Core Architectures and Programming
Department Informatik  >  Informatik 12  >  Forschung  >  Multicore Architectures and Programming

Multi-core Architectures and Programming

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Abstract

Multi-core processors offer a high theoretical computation performance and therefore open up new fascinating possibilities in scientific and other domains, like multimedia, medicine and finance. In order to fully exploit the performance, an efficient mapping of algorithms to the architecture of the respective multi-core processor has to be determined. Compared to traditional single-core processors, a radical rethinking of programming methodologies needs to be undertaken. Our aims are to gain new insights into modern multi-core architectures and the corresponding programming paradigms in order to exploit the platform and to make it easier to map algorithms to the platform. As platforms, we focus in particular on graphics cards from NVIDIA (e.g. Tesla based systems), on systems based on the Cell Processor (e.g. Sony's PLAYSTATION 3). However, we look also for new architectures like Tilera's TILEPro64 and Intel's Many Integrated Core (MIC).

Contact

Frank Hannig
Richard Membarth

Publications

2013
17 R. Membarth.
Code Generation for GPU Accelerators from a Domain-Specific Language for Medical Imaging.
Dissertation, University of Erlangen-Nuremberg, ISBN 978-3-8439-1074-3, Verlag Dr. Hut, Munich, Germany, May 2, 2013. ©1
2012
16 R. Membarth, F. Hannig, J. Teich and H. Köstler.
Towards Domain-specific Computing for Stencil Codes in HPC.
In Proceedings of the 2nd International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC), pp. 1133-1138, Salt Lake City, UT, USA, November 16, 2012. ©3
[doi>10.1109/SC.Companion.2012.136]
15 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Mastering Software Variant Explosion for GPU Accelerators.
In Proceedings of the 10th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar), pp. 123-132, Rhodes Island, Greece, August 27, 2012. ©1
[doi>10.1007/978-3-642-36949-0_15]
14 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators based on a Domain-Specific Language for Medical Imaging.
In Proceedings of the 11th International Symposium on Parallel and Distributed Computing (ISPDC), pp. 211-218, Munich, Germany, June 25-29, 2012. ©3
[doi>10.1109/ISPDC.2012.36]
13 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Generating Device-specific GPU Code for Local Operators in Medical Imaging.
In Proceedings of the 26th IEEE International Parallel & Distributed Processing Symposium (IPDPS), pp. 569-581, Shanghai, China, May 21-25, 2012. ©3
[doi>10.1109/IPDPS.2012.59]
12 R. Membarth, J. Lupp, F. Hannig, J. Teich, M. Körner and W. Eckert.
Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging.
In Proceedings of the 25th International Conference on Architecture of Computing Systems (ARCS), pp. 147-159, Munich, Germany, February 28 - March 02, 2012. ©1
[doi>10.1007/978-3-642-28293-5_13]
2011
11 P. Marwedel, J. Teich, G. Kouveli, I. Bacivarov, L. Thiele, S. Ha, C. Lee, Q. Xu and L. Huang.
Mapping of Applications to MPSoCs.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 109-118, Taipei, Taiwan. Oct. 9-14, 2011. ©1
10 R. Membarth, A. Lokhmotov and J. Teich.
Generating GPU Code from a High-level Representation for Image Processing Kernels.
In Proceedings of the 5th Workshop on Highly Parallel Processing on a Chip (HPPC), pp. 270-280, Bordeaux, France, August 30, 2011. ©1
[doi>10.1007/978-3-642-29737-3_31]
9 G. Kouveli, F. Hannig, J. Lupp and J. Teich.
Towards Resource-Aware Programming on Intel's Single-Chip Cloud Computer Processor.
In 3rd Many-core Applications Research Community (MARC) Symposium, Ettlingen, Germany, Jul. 5-6, 2011, volume 7598 of KIT Scientific Reports, pp. 111-114, KIT Scientific Publishing, 2011. ©1
8 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Frameworks for GPU Accelerators: A Comprehensive Evaluation using 2D/3D Image Registration.
In Proceedings of the 9th IEEE Symposium on Application Specific Processors (SASP), pp. 78-81, San Diego, CA, USA, June 5-6, 2011. ©3
[doi>10.1109/SASP.2011.5941083]
7 R. Membarth, H. Dutta, F. Hannig and J. Teich.
Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards.
In Transactions on High-Performance Embedded Architectures and Compilers (Transactions on HiPEAC), 5(3), 2011. ©3
6 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Frameworks for Multi-core Architectures: A Comprehensive Evaluation using 2D/3D Image Registration.
In Proceedings of the 24th International Conference on Architecture of Computing Systems (ARCS), pp. 62-73, Lake Como, Italy, February 22-25, 2011. ©1
[doi>10.1007/978-3-642-19137-4_6]
5 R. Membarth, F. Hannig, J. Teich, G. Litz and H. Hornegger.
Detector Defect Correction of Medical Images on Graphics Processors.
In Proceedings of the SPIE: Medical Imaging 2011: Image Processing, pp. 79624M 1-12, Lake Buena Vista, Orlando, FL, USA, February 12-17, 2011. ©1
[doi>10.1117/12.877656]
2010
4 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Comparison of Parallelization Frameworks for Shared Memory Multi-Core Architectures.
In Proceedings of the Embedded World Conference, Nuremberg, Germany, March 03-05, 2010. ©1
2009
3 R. Membarth, F. Hannig, H. Dutta and J. Teich.
Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors.
In Proceedings of the 9th International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS Workshop), pp. 277-288, July 20-23, 2009. ©1
[doi>10.1007/978-3-642-03138-0_31]
2 R. Membarth, F. Hannig, H. Dutta and J. Teich.
Optimization Flow for Algorithm Mapping on Graphics Cards.
In Proceedings of ACACES 2009 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems, pp. 229-232, Barcelona, Spain, July 12-18, 2009. ©1
1 R. Membarth, P. Kutzer, H. Dutta, F. Hannig and J. Teich.
Acceleration of Multiresolution Imaging Algorithms: A Comparative Study.
In Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 211-214, Boston, MA, USA, July 7-9, 2009. ©2
[doi>10.1109/ASAP.2009.8]

Misc.

2012
5 R. Membarth.
Code Generation for GPU Accelerators in Medical Imaging.
Invited Talk at the Symposium on Personal High-Performance Computing (PHPC), Brussels, Belgium, December 13, 2012. ©1
4 R. Membarth.
Automatic Code Generation for Image Processing Algorithms on Accelerators in Heterogeneous Architectures.
Talk, Intel GmbH, Braunschweig, Germany, September 20, 2012. ©1
3 M. Körner, W. Eckert, R. Membarth, F. Hannig and J. Teich.
Entwicklungsframeworks für Mehrkernarchitekturen und Grafikprozessoren: Evaluierung anhand eines Algorithmus zur Registrierung von 3D- mit 2D-Bilddaten.
Talk at the Conference for Parallel Programming, Concurrency, and Multi-core Systems (parallel), Karlsruhe, Germany, May 23-25, 2012. ©1
2011
2 W. Eckert and R. Membarth.
Frameworks for Multicore Architectures and GPU Accelerators: A Comprehensive Evaluation using 2D/3D Image Registration.
Talk at the Conference Multicore@Siemens, Erlangen, Germany, November 15-16, 2011. ©1
1 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Domain-specific Computing and Code Generation for Medical Imaging.
Poster Presentation at the 2nd Programming and Tuning Massively Parallel Systems Summer School (PUMPS), Barcelona, Spain, July 18-22, 2011. ©1

Studienarbeiten and Diploma Theses

2011
6 M. Geyer.
WCET-Analyse für Graphikkarten.
Pre-Master's thesis (Studienarbeit), Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, June 2011 . ©1
5 S. Roloff.
Simulation of Resource-Aware Applications on Heterogeneous Architectures.
Master's thesis (Diplomarbeit), Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany, June 2011. ©1
4 J. Lupp.
Task-Scheduling auf Grafikkarten mit Echtzeitanforderungen.
Bachelor Thesis, Department of Computer Science, UFriedrich-Alexander-Universität Erlangen-Nürnberg, Germany, May 2011. ©1
2010
3 S. Roloff.
Evaluierung der Programmiersprache X10 anhand von JPEG 2000.
Pre-Master's thesis (Projektarbeit), Department of Computer Science, University of Erlangen-Nuremberg, Germany, October 2010. ©1
2008
2 P. Kutzer.
Effiziente Abbildungsmethoden für Multibandzerlegungsfilter auf dem Cell-Prozessor .
Studienarbeit, Hardware/Software Co-Design, Dept of Computer Science-12, University of Erlangen-Nuremberg. ©1
1 R. Membarth.
Efficient Mapping Methodology for Medical Image Processing on GPUs.
Diploma thesis (Diplomarbeit), Department of Computer Science, University of Erlangen-Nuremberg, Germany, September 2008 . ©1

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  Impressum Stand: 09 May 2012.   R.M.