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Codesign
Department of Computer Science 12
Research and Projects
2D/3D Surveillance
AEOS
Automobilsensorik
AIS
BUILDABONG
CogniPower
CoMap
CRAU
DCCD
DIANA
ExaStencils
GEFA
HIPAcc
HLESI
HBS
InvasIC
INI.FAU
JReliability
KODAK
MMSys
Opt4J
Organic Bus
PARO
ReCoNodes
ReCoNets
ReKoSys
SEIS
SystemCoDesigner
PowerEval

CRC/Transregio 89
Invasive Computing

Dept. of Computer Science  >  CS 12  >  Research and Projects

Forschungsschwerpunkt des Lehrstuhls Hardware-Software-Co-Design ist der systematische Entwurf (CAD) eingebetteter Hardware/Software-Systeme. Im ersten Arbeitsgebiet SDA (System-Level Design Automation) wird der Co-Entwurf und die Optimierung der (teil-)automatisierten Abbildung von Spezifikationen in den Sprachen SystemC und Simulink auf heterogene eingebettete Zielplattformen erforscht. Der zweite Schwerpunkt ACD (Architecture and Compiler Design) untersucht den Co-Entwurf von Architektur und Compiler für massiv parallele MPSoC-Architekturen. Dazu gehören neben VLSI-Rechenfeldern auch Systeme mit eingebetteten Graphikkarten (GPUs). Im dritten Schwerpunkt RC (Reconfigurable Computing) werden die Potentiale von FPGAs untersucht zur Realisierung dynamisch rekonfigurierbarer (adaptiver) Systeme sowie die Aspekte der Zuverlässigkeit, Sicherheit (Security) und Verfügbarkeit zukünftiger nanoelektronischer Schaltungen. Einen weiteren Schwerpunkt bilden diskrete Optimierungsmethoden, insbesondere lokale und globale Suchverfahren, lineare Programmierung, Mehrzieloptimierungsverfahren und deren Anwendung im Kontext der optimalen Auslegung technischer Systeme.


System-level Design Automation

Ongoing Projects

Automobilsensorik@ESI
Due to its interdisciplinary collaboration, the ESI application center (dt. ESI-Anwendungszentrum) and its lab on automotive sensors (dt. Automobilsensorik@ESI) provides excellent competences to expedit future automotive embedded systems. Hardware/Software Co-Design investigates the aspects of designing reliable and safe vide-based driver assistance systems at system level.
Funding body: Bavarian Ministry of Economic Affairs and Media, Energy and Technology as part of the ESI-Anwendungszentrum
CogniPower: Cognitive Power Control for Mobile Devices
The ultimate goal of this project is to investigate how to apply cognitive approaches to manage power consumption for mobile devices for various loads induced by user behavior as well as a dynamically changing radio environment. In general, service quality experienced by the user and power efficiency of the mobile device are conflicting targets. Here, the project aims to employ cognitive techniques to find the best trade-off between these objectives.
Funding body: Intel Deutschland GmbH, Neubiberg
CRAU: Compositional System Level Reliability Analysis in the Presence of Uncertainties
The ultimate goal of this project is the investigation and development of a methodology for system-level reliability analysis and design of reliable systems through means of self-adaptation and error-resiliency. This project focuses on the development of suitable cross-level reliability analysis techniques that combine various reliability analysis techniques across different levels of abstraction and enrich them by the ability to consider and explicitly model uncertainties.
Funding body: German Research Foundation (DFG) under Grant Number GL 819/1-2 and TE 163/16-2
GEFA: Holistic Design of Automotive Advanced Driver Assistance Systems
The main target of this project is the development of novel design methods, tailored to distributed video-based driver assistance and cyper-physical systems in general. We put focus on how to combine modelling, analysis, and design space exploration to cover algorithms, applications, interconnection, and ECU architectures in a holistic and cross-level fashion.
Funding body: Bavarian Ministry of Economic Affairs, Infrastructure, Transport and Technology, in the context of the R&D program 'Information and Communications Technology' and the European Regional Development Fund (ERDF) as part of ESI Application Center
INI.FAU: Design and Evaluation of high-availability Ethernet-based E/E-Architectures for latency and safety-critical Applications
With the institute INI.FAU, the Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) strikes a new path in research and teaching. Together with the AUDI AG, a regional competence center is developed in the site of Ingolstadt that provides unique working conditions for scientific staff to transfer theoretic knowledge into practical applications. One major goal is to advance future automotive electronics via novel methods in simulation, design, data analysis, and safety engineering.
Funding body: AUDI AG, Ingolstadt
InvasIC: Transregional Collaborative Research Centre 89 — Invasive Computing
In the proposed CRC/Transregio, we intend to investigate a completely novel paradigm for designing and programming future parallel computing systems called invasive computing. The main idea and novelty of invasive computing is to introduce resource-aware programming support in the sense that a given program gets the ability to explore and dynamically spread its computations to neighbour processors similar to a phase of invasion, then to execute portions of code of high parallelism degree in parallel based on the available (invasible) region on a given multi-processor architecture. Afterwards, once the program terminates or if the degree of parallelism should be lower again, the program may enter a retreat phase, deallocate resources and resume execution again, for example, sequentially on a single processor. In order to support this idea of self-adaptive and resource-aware programming, not only new programming concepts, languages, compilers and operating systems are necessary but also revolutionary architectural changes in the design of MPSoCs (Multi-Processor Systems-on-a-Chip) must be provided so to efficiently support invasion, infection and retreat operations involving concepts for dynamic processor, interconnect and memory reconfiguration.
Subproject A4, Design-Time Characterisation and Analysis of Invasive Algorithmic Patterns
Funding body: German Research Foundation (DFG) under Grant Number TRR 89/1-2010
KoDaK: Coexistence of different Traffic Classes in Vehicles and Airplanes
The overall goal of this project is the analysis and realization of different Ethernet variants for the application domains avionics and aerospace, rail transport, and automotive. The fokus of Hardware/Software Co-Design is the development of virtual prototypes for (a) the simulative evaluation of complete systems from the applications domains as well as (b) the automized test and validation of network components.
Funding body: Bavarian Ministry of Economic Affairs and Media, Energy and Technology under Grant Number IUK-1406-0010 / IUK453/002
SystemCoDesigner: System level design space exploration for embedded systems
Almost 80% of all design decisions are taken in the first 20% of the design time. Thus, an early and substantiated knowledge about possible solutions is mandatory to design high quality systems. Aiding in this critical design phase is the mission of SystemCoDesigner. It is a software tool for automatic design space exploration at the electronic system level. Additionally, SystemCoDesigner generates platform-based prototyps of (mixed) hardware/software systems. By exploring the design space, a designer becomes more confident in decisions to be done. To sum up, SystemCoDesigner is a novel EDA tool which covers all aspects from (i) specification over (ii) automatic exploration to (iii) automatic prototype implementation.

Open Source Projects

JReliability: The Java-Based Reliability Library
JReliability allows to derive several reliability-related measures like Mean-Time-To-Failure (MTTF) or Mission-Time (MT) of complex systems that are modeled using Boolean functions, efficiently encoded in Binary Decision Diagrams (BDDs). The library is platform-independent and licensed under LGPL (open source).
Opt4J: The Free Optimization Framework for Java
Opt4J is a lightweight but powerful framework for applying optimization algorithms like Evolutionary Algorithms, Particle Swarms, or Simulated Annealing to synthetic benchmarks as well as real-world optimization problems. The complete framework is written in Java and available as open source licensed under LGPL.
SysteMoC: Representing Models of Computation in SystemC
The automatic identification of models of computation is the key for analysis as well as efficient synthesis for hardware/software systems. Programming language like Java, C++, etc. are Turing-complete and mostly restrict the analysis and synthesis. Here, the project SysteMoC is located. Based on the system design language SystemC, coding styles are defined which permit the identification of the underlying model of computation and, hence, allow for analysis and efficient synthesis of hardware/software systems.

Completed Projects

AEOS: Actor-Oriented Synthesis and Optimization of Digital Hardware/Software Systems at the Electronic System Level
This project is focused on new approaches to optimally synthesize behavioral models targeting heterogeneous Multi-Processor-Systems-on-a-Chip implementations. This also includes novel hardware synthesis and software synthesis methodologies as well as synthesis approaches across hardware/software boundaries.
Funding body: German Research Foundation (DFG) under Grant Number TE 163/18-2
DIANA: Extended Diagnostic Capabilities to Improve the Analyzability of Electrical Deficiencies in Automotive Systems.
In the DIANA project research is done to improve the analyzability and the diagnostic capabilities of electronic control units in automotive systems. The goal is to make the detection and the repair of electric malfunctions in automobiles faster and more efficient. To acchieve this goal, there is a tight collaboration between corporations along the whole production chain of the automotive industry, including producers of semiconductors, system suppliers, and car manufacturers.
Funding body: Federal Ministry of Education and Research (BMBF) under subcontract of the AUDI AG
Hardware/Software Co-Design of Camera-based Driver Assistance Systems
The goal of this project is the model-based design of future camera-based driver assistance systems. This includes an actor-oriented modeling of the driver functional parts of the systems. Based on this model, different implementation alternatives in both hardware and software shall be investigated and evaluated with respect to their applicability in an automotive environment.
In cooperation with Daimler AG, Ulm
HLESI: High-Level Modeling of Bus Controllers and Systems from the Industrial Automation Domain
This project investigates the applicability of high-level modelling, analysis, and sythesis techniques from the MPSoC domain in the area of industrial automation communication systems. As a real-world case-study, the project develops a high-level model of a PROFINET Ethernet controller.
Funding body: Bavarian Ministry of Economic Affairs, Infrastructure, Transport and Technology, in the context of the R&D program 'Information and Communications Technology' and the European Regional Development Fund (ERDF) as part of ESI Application Center
INI.FAU: Integral Safety Architecture — Modeling, Analysis, Optimization, and Variant Management
With the institute INI.FAU, the Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) strikes a new path in research and teaching. Together with the AUDI AG, a regional competence center is developed in the site of Ingolstadt that provides unique working conditions for scientific staff to transfer theoretic knowledge into practical applications. One major goal is to advance future automotive electronics via novel methods in simulation, design, data analysis, and safety engineering.
Funding body: AUDI AG, Ingolstadt
PowerEval: Performance and Power Consumption Evaluation and Optimization of Future Mobile Platforms
Modern mobile platform consist of both hardware components like processors, buses, memory, and HF components as well as software components like the operating system, drivers, communication stacks, and interfaces to the application software. This project developes a novel methodology to investigate various architectural trade-offs with respect to energy efficiency already at the system level when designing future mobile platforms.
Funding body: Bavarian Ministry of Economic Affairs, Infrastructure, Transport and Technology, in the context of the R&D program 'Information and Communications Technology' and the European Regional Development Fund (ERDF)
SEIS: Security in embedded IP-based systems
The SEIS project focuses on supporting the secure usage of the internet protocol in embedded systems to create a basis for further innovations and improvements in efficiency. Our vision is a continuous and secure utilization of IP based communications in all application areas.
SFB694 Research Project B5: Production-Aware Design Methodology for Software Embedded in Components of Mobile Systems
Nowadays, electronics and software comprise the highest potential for innovation but also for breakdown factors in automotive applications. Hence, in this project, production-aware and model-based software design methodologies will be investigated in order to compensate tolerances in manufacturing, aging, and faults in embedded systems. With the goal to analyze, sustainable improve, and solve the problem of richness of variants, novel design methodologies will be explored.
SpecVer: Specification for Verification of complex systems
SpecVer investigates novel design methodologies for complex systems from the telecommunication domain. In Contrast to existing approaches, SpecVer raises the level of abstraction by allowing for late changes in the design as well as a tight combination of specification and verification. That way, the productivity as well as the reliability of each design step will be sustainable increased ("first-time-right"). The results are exspected to be transferable to othe domains, as automotive, etc.

Architecture and Compiler Design

Ongoing Projects

ExaStencils — Advanced Stencil-Code Engineering
ExaStencils has the goal to develop a software technology which enables the largely automatic derivation of highly optimized, exascale-ready stencil codes. The main distinguishing quality of the project is that domain knowledge of the specific application and the execution platform used is going to be leveraged at several levels of abstraction in tuning the implementation. The major steps are (1) tuning the mathematical formulation of the problem, (2) converting it to a domain-specific programming language, (3) employing software product-line technology for an effective management of the commonalities and variabilities of stencil codes and for domain-specific optimization and generation, (4) applying polyhedral techniques of loop optimization, and (5) adapting to the specific features of the execution platform used. The first two case studies will be in particle simulation and quantum chemistry.
Funding body: German Research Foundation (DFG) under Grant Number TE 163/17-1
HBS: Research Training Group "Heterogeneous Image Systems", Project B3
In project B3 consistent methods for the mapping of algorithms to heterogeneous architectures will be examined. In particular, we will explore novel parallelization strategies, partitioning methods, and code generation techniques, with a focus on image systems.
Funding body: German Research Foundation (DFG)
INI.FAU: Parallelization and Resource Estimation of Algorithms for Heterogeneous DAS Architectures
With the institute INI.FAU, the Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) strikes a new path in research and teaching. Together with the AUDI AG, a regional competence center is developed in the site of Ingolstadt that provides unique working conditions for scientific staff to transfer theoretic knowledge into practical applications. One major goal is to advance future automotive electronics via novel methods in simulation, design, data analysis, and safety engineering.
Funding body: AUDI AG, Ingolstadt
InvasIC: Transregional Collaborative Research Centre 89 — Invasive Computing
In the proposed CRC/Transregio, we intend to investigate a completely novel paradigm for designing and programming future parallel computing systems called invasive computing. The main idea and novelty of invasive computing is to introduce resource-aware programming support in the sense that a given program gets the ability to explore and dynamically spread its computations to neighbour processors similar to a phase of invasion, then to execute portions of code of high parallelism degree in parallel based on the available (invasible) region on a given multi-processor architecture. Afterwards, once the program terminates or if the degree of parallelism should be lower again, the program may enter a retreat phase, deallocate resources and resume execution again, for example, sequentially on a single processor. In order to support this idea of self-adaptive and resource-aware programming, not only new programming concepts, languages, compilers and operating systems are necessary but also revolutionary architectural changes in the design of MPSoCs (Multi-Processor Systems-on-a-Chip) must be provided so to efficiently support invasion, infection and retreat operations involving concepts for dynamic processor, interconnect and memory reconfiguration.
Project B2, Invasive Tightly-Coupled Processor Arrays
Project C2, Simulative Design Space Exploration
Project C3, Compilation and Code Generation for Invasive Programs
Project Z2, Validation and Demonstrator
Funding body: German Research Foundation (DFG) under Grant Number TRR 89/1-2010
Dedicated massive parallelism
In this project called PARO, problems of designing fine-grain massively parallel VLSI processor array architectures are treated. Formerly known as systolic arrays, these architectures turn out to play a dominant role, not as standalone computers, but as building blocks of larger customized systems. Their integration into larger systems makes the implementation and application of special design methodologies from algorithm to processor array necessary.
MAP: Multi-core Architectures and Programming
This project considers current multi-core and many-core systems found in commodity systems. Such systems by be graphics cards which have nowadays up to 240 so called streaming processors or the Cell processor consisting of one central Power Processing Element (PPE) 8 coprocessors, so called Synergistic Processing Elements (SPEs). Beside the architectures themselves, parallel programming models as well as the efficient mapping of algorithms to the architectures are investigated.

Open Source Projects

HIPAcc: A Domain-Specific Language and GPU Target Code Generator for Image Processing Applications
HIPAcc allows to design image processing kernels and algorithms in a domain-specific language (DSL). From this high-level description, low-level target code for GPU accelerators is generated using source-to-source translation. As back ends, the framework supports CUDA, OpenCL, and Renderscript. The framework runs on GNU/Linux and Mac OS X and is licensed under the Simplified BSD License (open source).

Completed Projects

CoMap: Co-Design of massively parallel embedded processor architectures
The project deals with the systematic (a) mapping, (b) evaluation, and (c) exploration of massively parallel processor architectures that are designed for special purpose applications in the world of embedded computers. The investigated class of computer architectures can be described by massively parallel networked processing elements that, using today's hardware technology, may be implemented on a single chip (SoC - System on a Chip).
Funding body: German Research Foundation (DFG) under Grant Numbers TE 163/13-1 and 163/13-2
Design of special purpose processor architectures
Considered are the problems of conception and compiler support for application-specific instruction-set processors (ASIPs). Examples of such processors are digital signal processors (DSPs) and microcontrollers. Treated are the challenging problems of systematic design and simulation of application-specific processors and the development and exploration of better compilation methods to support them.
MMSys: Motion Management System
The project aims at the design of a high quality, efficient and cost-effective radiotherapy system for classification, positioning assistance and motion detection of patients. For this purpose, Time-of-flight (ToF) will be utilized, which is an emerging imaging technology for real-time acquisition of metric 3-D surface data.
Funding body: Bavarian Ministry of Economic Affairs, Infrastructure, Transport and Technology, in the context of the R&D program 'Information and Communications Technology' and the European Regional Development Fund (ERDF) under Grant Number IUK338/002

Reconfigurable Computing

Ongoing Projects

Reliable FPGA-based Adaptive Systems for Space and Avionics Applications
The aim of this project is the investigation and development of an adaptive FPGA-based system for space and avionic applications which allows to exchange modules at run-time. However, SRAM-based FPGAs are highly susceptible to so-called Single Event Effects (SEEs) when operating in such harsh environments. Therefore, we are investigating countermeasures, like scrubbing and triple modular redundancy in order to increase the reliability of such systems.
Funding body: Bavarian Ministry of Economic Affairs, Infrastructure, Transport and Technology, in the context of the R&D program 'Information and Communications Technology' and the European Regional Development Fund (ERDF) as part of ESI Application Center

Completed Projects

Concepts for Implementing and Optimizing a Prototypical Design of a Modular and Configurable Data Consolidation Device Unit for Civil Air Planes
The goals of this research project are concepts for monitoring and resolving of data inconsistencies in civil air planes with the help of a data consolidation devices.
Funding body: Diehl Aerospace GmbH, Überlingen
Dynamically Reconfigurable SQL Accelerator based on FPGAs
The aim of this project is the investigation and development of an FPGA-based module library combined with the runtime environment for the mapping of SQL queries in hardware. This library is composed of partial dynamic modules in order to save both synthesis and reconfiguration time. This flexible approach allows the on-the-fly assembly of data paths of SQL queries to achieve a very high data throughput.
Funding body: IBM Deutschland Research & Development GmbH, Böblingen
AIS (Autonome Integrierte Systeme)
The goal of AIS (supported by BMBF) is to research a new kind of design methodology for autonomous integrated systems. With this new design methodology components of architecture will be dimensioned with autonomous characteristics and provided for system design. In a process of exploration and integration of these components a combined autonomous design system methodology will be proposed. The design process will include - beside autonomous components and communication - an approach to consider also the operating system. See also the press release of the BMBF: html pdf
Founding body: Federal Ministry of Education and Research (BMBF), Grant Number: 01 M 3083
ESM (Erlangen Slot Machine): A flexible Platform for Dynamic Reconfigurable Computing
Our aim is to develop a flexible and easy to use hardware platform for dynamic runtime reconfiguration which will allow to efficiently implement a wide array of problems, in particular video streaming algorithms and reaction to node failures in the ReCoNets project.
For more information visit the ESM Wiki!
Funding body: German Research Foundation (DFG) under Grant Number TE 163/14-X
ReCoNodes: Optimization methodologies for reconfiguration management on reconfigurable hardware nodes
The aim of this project is to overcome the deficiency of design automation of reconfigurable devices, in particular FPGA-based architectures. This goal is likely to be reached by supplying models and optimization methodologies for dynamic hardware reconfiguration. Those models and methods are part of a kind of operating system for hardware reconfiguration in charge of the resource management at run-time.
Funding body: German Research Foundation (DFG) under Grant Number TE 163/14-X
ReCoNets: Design methodology for embedded system made upon small networks of hardware reconfigurable nodes and connections
The aim of this project is the research on design methodologies for a novel architectural class of computer systems characterized by networking and reconfigurability at the hardware level. This architectural class of computer system are specially designed for a given technical context: embedded systems. The reconfigurability is not only limited to a node of the network, but the connection can also be reconfigurable as well. Examples of application area of such reconfigurable networks are automobile electronic and body-area-network.
Funding body: German Research Foundation (DFG) under Grant Number TE 163/10-X

Self-organizing Systems

Ongoing Projects

InvasIC: Transregional Collaborative Research Centre 89 — Invasive Computing
In the proposed CRC/Transregio, we intend to investigate a completely novel paradigm for designing and programming future parallel computing systems called invasive computing. The main idea and novelty of invasive computing is to introduce resource-aware programming support in the sense that a given program gets the ability to explore and dynamically spread its computations to neighbour processors similar to a phase of invasion, then to execute portions of code of high parallelism degree in parallel based on the available (invasible) region on a given multi-processor architecture. Afterwards, once the program terminates or if the degree of parallelism should be lower again, the program may enter a retreat phase, deallocate resources and resume execution again, for example, sequentially on a single processor. In order to support this idea of self-adaptive and resource-aware programming, not only new programming concepts, languages, compilers and operating systems are necessary but also revolutionary architectural changes in the design of MPSoCs (Multi-Processor Systems-on-a-Chip) must be provided so to efficiently support invasion, infection and retreat operations involving concepts for dynamic processor, interconnect and memory reconfiguration.
Subproject A1, Basics of Invasive Computing
Subproject B5, Invasive NoCs - Autonomous, Self-Optimising Communication Infrastructures for MPSoCs
Funding body: German Research Foundation (DFG) under Grant Number TRR 89/1-2010

Completed Projects

2D/3D Video Surveillance
The aim of this project is to use the information of a 2D/3D camera for video surveillance. With our approach, we try to solve the task of video surveillance without a human actively watching the video.
Funding body: Bavarian Ministry of Economic Affairs, Infrastructure, Transport and Technology, in the context of the R&D program 'Information and Communications Technology' and the European Regional Development Fund (ERDF) under Grant Number IUK-0908-0002/IUK337/003
Organic Bus
In the project Organic Bus (supported by the DFG in the SPP 1183 Organic Computing) an organic approach for the analysis, design and optimization of bus-based communication systems is investigated. The goal of our approach is to overcome drawbacks of today's pure offline designs that are based on worst-case estimations, are not expandable, and may easily degenerate when the environment or requirements change at run-time.
Funding body: German Research Foundation (DFG) under Grant Number TE 163/15-1
ReKoSys: Cognitive Embedded Systems Based on Dynamically Reconfigurable Hardware
The aim of the ReKoSys project is to explore the use of cognitive functions in embedded systems using dynamically reconfigurable hardware. Applications in the areas of automotive networks and security technology form the framework in which the developed techniques will be tested.
Funding body: Bavarian Ministry of Economic Affairs, Infrastructure, Transport and Technology, in the context of the R&D program 'Information and Communications Technology' and the European Regional Development Fund (ERDF) under Grant Number IUK-0706-0003/IUK262/002
Cognitive vision system
To enhance cognitive abilities of our robots, several cognitive computer vision algorithms are being researched and applied. The application scenario is the real life daily tasks also. Another main focus is the development of cognitive camera systems in cooperation with the Fraunhofer Institut IIS.
  Contact Last modified: June 29 2016.   F.H.,M.G.,D.Z.,S.W.,