The steady advances in semiconductor technology allow for increasingly complex SoCs, including multiple (heterogeneous) micro processors, dedicated accelerators, large on-chip memories, sophisticated interconnection networks, and peripherals. However, design, verification, and test as well as parallel programming of such complex multi-core architectures are very challenging since they may have to deal with highly dynamic workloads in different application scenarios and environments. In addition, the architecture might alter itself, either intentionally (e.g., dynamic voltage/frequency scaling, power management) or unintentionally (e.g., failures, aging).
As a remedy, one recent research trend in multi-core computing is to design control loops across all platform layers, from application and run-time software down to the status of the underlying hardware. Concepts such as resource-aware programming and adaptive computing are promising candidates for optimizing multi-core systems at run-time with respect to several objectives (utilization, performance, temperature, energy, reliability, dependability, etc.). On the other hand, the enhanced flexibility and adaptivity of such systems raises questions on the predictability of program execution.
The Racing Workshop aims at bringing together researchers and experts from both academia and industry to discuss and exchange research advances from different disciplines in design and test of multi-core architectures as well as programming and run-time management. A distinctive feature of the workshop is its cross section through the entire software/hardware stack, ranging from programming down to multi-core hardware. Thus, Racing is targeted for all of those who are interested in understanding the big picture and the potential of resource-aware and adaptive multi-core computing, its challenges, available solutions, and enables for collaboration of the different domains.
Topics of the Racing Workshop include, but are not limited to:
Perspective authors are invited to submit an extended abstract (max. 6 pages) or work in progress (2 pages). All papers should be formatted as follows: A4 or letter pages, double column, single spaced, Times or equivalent font of minimum 10pt. All submissions have to be sent via the conference management system EasyChair. Please set up your own personal account if you do not already own an EasyChair account.
Accepted papers will be published on the workshop’s web page. Every accepted paper must have at least one author registered to the workshop by the time the camera-ready paper is submitted. In addition, authors will be invited to submit an extended version of their papers for publication in a journal's special issue, which will be announced at a later point in time.
Submission deadline: March 15, 2014
Notification of acceptance: April 15, 2014
Camera-ready final version: April 30, 2014
Jürgen Teich, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Frank Hannig, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Ali Ahmadinia, Glasgow Caledonian University, UK
Iuliana Bacivarov, ETH Zürich, Switzerland
Andreas Herkersdorf, TU München, Germany
Christoph Kessler, Linköping University, Sweden
Sébastien Pillement, University of Nantes, France
Andy D. Pimentel, University of Amsterdam, Netherlands
Thomas Schweizer, University of Tübingen, Germany
Sander Stuijk, Eindhoven University of Technology, Netherlands
Sascha Uhrig, TU Dortmund, Germany
16:00 – 16:05 Welcome
16:05 – 16:35 Keynote
16:05 – 16:35 Adaptive Real-Time Resource Management – The ACTORS Approach
Early real-time systems dealt with simple tasks of well known characteristics. The efforts and cost to obtain about their worst case behavior was acceptable in contexts with strict requirements. As applications have become more complex and less predictable since, obtaining detailed information is often no longer possible, or the efforts not justifiable. An example for these is high quality video processing, where e.g. decoding times of frames are highly content dependent and variable.
In this talk, we will present a resource management approach based on abstractions of resource states in the form of a small discrete number of levels as the basis for dealing with variability, providing a small sized view of the system state. A central resource manager takes adaptation decisions only on these levels, while real-time methods provide temporal isolation to ensure the assigned levels are maintained. In the ACTORS EU IST project, adaptivity of media applications is modeled as data-flow networks, using the CAL, a data flow oriented actors language.
Gerhard Fohler has been holding the Chair for Real-time Systems at TU Kaiserslautern since 2006. He received his Dipl. Ing. and Ph.D. degrees with honors from the TU Vienna, Prof. Hermann Kopetz, then was with the University of Massachusetts at Amherst, USA as postdoctoral researcher. Before joining TU Kaiserslautern, he was with MDH Sweden where he was promoted to full professor.
His research is based on issues in the field of real-time, embedded systems, with emphasis on adaptive real-time systems. Recently, it has been including related issues in real-time and control, real-time networking, real-time media processing, and wireless sensor networks.
He has been involved in a number of EU projects, coordinator and partner, and was core partner of the EU IST Networks-of-Excellence ARTIST.
He is Chairman of the Technical Committee on Real-time Systems of Euromicro, which is responsible for ECRTS, the prime European conference on real-time systems, member of the executive board of the real-time and embedded committees of the IEEE, where he chairs the sub-committee on conference affairs. He was program chair of the leading real-time conferences, and is associate editor of Springer's Real-time System Journal. 16:35 – 17:05 Tutorial Session: Invasive Computing (Part I)
16:35 – 17:05 Introduction to Invasive Computing
17:05 – 17:20 Coffee Break
17:20 – 18:20 Tutorial Session: Invasive Computing (Part II)
17:20 – 17:50 Massively Parallel Processor Architectures for Resource-aware Computing
Vahid Lari, Alexandru Tanase, Frank Hannig, and Jürgen Teich
17:50 – 18:20 Resource-Aware Programming for Robotic Vision
Johny Paul, Walter Stechele, Manfred Kröhnert, and Tamim Asfour
18:20 – 19:00 Poster and Demo Session
Poster: Emulated ASIC Power and Temperature Monitor System for FPGA Prototyping of an Invasive MPSoC
Elisabeth Glocker, Qingqing Chen, Asheque M. Zaidi, Ulf Schlichtmann, and Doris Schmitt-Landsiedel
Poster: Evaluating the Self-Optimization Process of the Adaptive Memory Management Architecture
Oliver Mattes and Wolfgang Karl
Poster: Resource Prediction for Humanoid Robots
Manfred Kröhnert, Nikolaus Vahrenkamp, Johny Paul, Walter Stechele, and Tamim Asfour
Demo: Invasive Tightly-Coupled Processor Arrays
Vahid Lari, Éricles Sousa, Frank Hannig, and Jürgen Teich
Demo: Resource-aware Computer Vision Application on Heterogeneous Multi-Tile Architecture
Johny Paul, Walter Stechele, Éricles Sousa, Vahid Lari, Frank Hannig, and Jürgen Teich
9:00 – 10:30 Session 1: Fault Tolerance and Reliability in Multicore Architectures
9:00 – 9:30 Heterogeneity-aware Fault Tolerance using a Self-Organizing Runtime System
Mario Kicherer and Wolfgang Karl
9:30 – 10:00 Resource-Aware Replication on Heterogeneous Multicores: Challenges and Opportunities
Björn Döbel, Robert Muschner, and Hermann Härtig
10:00 – 10:30 Towards Cross-layer Reliability Analysis of Transient and Permanent Faults
Hananeh Aliee, Liang Chen, Mojtaba Ebrahimi, Michael Glaß, Faramarz Khosravi, and Mehdi B. Tahoori
10:30 – 10:50 Coffee Break
10:50 – 12:20 Session 2: Efficiency and Predictability in Parallel and Distributed Computing Systems
10:50 – 11:20 Optimized Composition: Generating Efficient Code for Heterogeneous Systems from
Multi-Variant Components, Skeletons and Containers
Christoph Kessler, Usman Dastgeer, and Lu Li
11:20 – 11:50 Invited talk: Using Contracts for Controlling Concurrent Change
This talk will present the on-going effort in the German-funded Research Unit CCC (Controlling Concurrent Change) towards the in-field validation of software and hardware updates of safety critical systems. We will start with a general motivation of the project, arguing that moving part of the verification process to the field is in some contexts (such as the automotive industry) becoming a necessity. We will then describe the strategy chosen in CCC, which is based on contracting mechanisms used as interfaces between changing platform components and networks on the one side, and changing applications on the other side, so that the update validation process can be automated. In practice, a flexible distributed middleware layer will autonomously handle contracting and establish system self-protection and self-configuration to guarantee the required safety, security, and availability properties. Here, the two main challenges are: the interdependency between contracts through mapping and resource sharing; and the interdependency between different viewpoints such as timing, security etc.
Sophie Quinton is a research associate ("chargée de recherche") at Inria Grenoble - Rhône-Alpes in France. She received her M.Sc. degree in Computer Science from the University of Rennes, France, in 2005 and her PhD degree from the University of Grenoble, France, in 2011. She was a student at the École Normale Supérieure de Cachan from 2002 to 2005 and then a graduate research assistant in the VERIMAG laboratory, one of the leading academic labs in verification and model-based design of embedded systems. She later worked as a postdoc in the Embedded System Design Automation group of the Institute of Computer and Network Engineering at TU Braunschweig until November 2013. Her research interests cover compositional performance analysis of real-time systems and contract-based design and verification of systems of components. She is currently the leader of the project “Formal Methods for Contracting” within the German-funded Research Unit CCC (Controlling Concurrent Change). 11:50 – 12:20 Invited talk: The ARES CGRA Architecture – Concepts, Solutions, and Applications
This talk will give an overview of the ARES coarse-grained reconfigurable architecture (CGRA) starting with a general view of the architectural concepts how to design and combine processing elements in an efficient way. The mapping of applications onto this architecture will be presented afterwards. Subsequently, various use cases of this architecture will be described starting with the use of the ARES-CGRA as a reliability enhancer by combining spatial and temporal redundancy, dynamically. Then, the evaluation of a data processing unit for X-ray detection in space which has been implemented on a CGRA will be presented. Finally, the talk will show how the CGRA can be integrated into microprocessors for acceleration of dedicated applications and to reduce the power consumption in microprocessors.
Oliver Bringmann is full professor and is directing the Chair for Embedded Systems at the Department of Computer Science at the University of Tübingen and he is director at FZI Research Center for Information Technologies in Karlsruhe, Germany. He studied computer science at the University of Karlsruhe (KIT) and received the doctoral degree (PhD) in computer science from the University of Tübingen in 2001. Until April 2012 he was division manager of the research division Intelligent Systems and Production Engineering (ISPE) and department manager of the research group "Microelectronic System Design" and member of the management board at FZI. His research interests are on design, analysis, and verification of embedded systems and systems-on-chip as well as their application in the automotive, medical, mobile communication, and industrial automation domain. 12:20 – 13:30 Lunch
13:30 – 15:00 Session 3: Performance Analysis and Tuning
13:30 – 14:00 Automatic Detection of Performance Anomalies in Task-Parallel Programs
Andi Drebes, Karine Heydemann, Antoniu Pop, Albert Cohen, and Nathalie Drach
14:00 – 14:30 A Layered Modeling and Simulation Approach to investigate Resource-aware Computing in MPSoCs
Aurang Zaib, Prashanth Raju, Thomas Wild, and Andreas Herkersdorf
14:30 – 15:00 Autotuning and Self-Adaptability in Concurrency Libraries
Thomas Karcher, Christopher Guckes, and Walter F. Tichy
End of Workshop