Publications by Frank Hannig

Frank Hannig and Jürgen Teich.
Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals.
In Proceedings IEEE 15th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2004).
pp. 17-27, Galveston, TX, U.S.A., September 27-29, 2004.
Alexey Kupriyanov, Frank Hannig, and Jürgen Teich.
Automatic and Optimized Generation of Compiled High-Speed RTL Simulators.
In Proceedings of the Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES) held in conjunction with the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES 2004).
Washington, DC, U.S.A., September 22-25, 2004.
Frank Hannig, Hritam Dutta, and Jürgen Teich.
Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays - Architectural Parameters and Methodology.
To appear in International Journal of Embedded Systems (IJES), Inderscience, 2004.
Frank Hannig and Jürgen Teich.
Dynamic Piecewise Linear/Regular Algorithms.
In Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004).
pp. 79-84, Dresden, Germany, September 7-10, 2004.
Alexey Kupriyanov, Frank Hannig, and Jürgen Teich.
High-Speed Event-Driven RTL Compiled Simulation.
In Proceedings of the 4th International Samos Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2004).
Island of Samos, Greece, July 19-21, 2004.
In Lecture Notes in Computer Science (LNCS), Vol. 3133, pp. 519-529, Springer, 2004.
Frank Hannig and Jürgen Teich.
Resource Constrained and Speculative Scheduling of Dynamic Piecewise Regular Algorithms.
Technical Report 01-2004, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design. Am Weichselgarten 3, D-91058 Erlangen, Germany, June, 2004.
Frank Hannig, Hritam Dutta, and Jürgen Teich.
Regular Mapping for Coarse-grained Reconfigurable Architectures.
In Proceedings of the 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2004).
Vol. V, pp. 57-60, Montréal, Quebec, Canada, May 17-21, 2004.
Frank Hannig, Hritam Dutta, and Jürgen Teich.
Mapping of Regular Nested Loop Programs to Coarse-grained Reconfigurable Arrays - Constraints and Methodology.
In Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004).
Santa Fe, NM, U.S.A., April 26-30, 2004.
Frank Hannig and Jürgen Teich.
Energy Estimation and Optimization for Piecewise Regular Processor Arrays.
Chapter 6 in Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation.
Signal Processing and Communications Series, Vol. 20, pp. 107-126, Marcel Dekker, 2004.
Frank Hannig and Jürgen Teich.
Energy Estimation of Nested Loop Programs.
In Proceedings of the 14th Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA 2002).
Winnipeg, Manitoba, Canada, August 10-13, 2002.
Frank Hannig and Jürgen Teich.
Energy Estimation for Piecewise Regular Processor Arrays.
In Proceedings of the International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS-II).
Island of Samos, Greece, July 22-25, 2002.
Marcus Bednara, Frank Hannig, and Jürgen Teich.
Generation of Distributed Loop Control.
In Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS.
In Lecture Notes in Computer Science (LNCS), Vol. 2268, pp. 154-170, Springer, 2002.
Marcus Bednara, Frank Hannig, and Jürgen Teich.
Boundary Control: A new Distributed Control Architecture for Space-Time Tranformed (VLSI) Processor Arrays.
In Proceedings of the 35th IEEE Asilomar Conference on Signals, Systems and Computers.
Pacific Grove, California, U.S.A., November 4-7, 2001.
Frank Hannig and Jürgen Teich.
Design Space Exploration for Massively Parallel Processor Arrays.
In Proceedings of the Sixth International Conference on Parallel Computing Technologies (PaCT-2001).
Novosibirsk, Russia, September 3-7, 2001.
In Lecture Notes in Computer Science (LNCS), Vol. 2127, pp. 51-65, Springer, 2001.
Talks and Others
10/2004 Architektur und Compiler Co-Design
at the DFG SPP 1148 Workshop, Blaubeuren, Germany, October 4, 2004.
02/2004 ArchitectureComposer
CAD Software Demo at the University Booth at Design, Automation and Test in Europe (DATE 2004), Paris, France, February 16-20, 2004.
02/2004 Mapping of Regular Algorithms to Massively Parallel Architectures
at the Department of System Simulation, University Erlangen-Nuremberg, Germany, February 12, 2004.