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Lehrstuhl für Informatik 12
Publikationen
Department Informatik  >  Informatik 12  >  Veröffentlichungen

Publikationen am Lehrstuhl für Hardware-Software-Co-Design

Studentische AbschlussarbeitenTutorials, Keynotes, Invited Talks, etc.BibTexSuche
Jahr:

2017
20 C. Schmitt, M. Schmid, S. Kuckuk, H. Köstler, J. Teich and F. Hannig.
Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution.
To appear in Parallel Processing Letters. ©1
19 S. Ha and J. Teich.
The Handbook of Hardware/Software Codesign.
Editors, Springer, 2017. To appear. ©1
18 Z. Li, H. Park, A. Malik, K. Wang, Z. Salcic, B. Kuzmin, M. Glaß and J. Teich.
Using Design Space Exploration for Finding Schedules with Guaranteed Reaction Times of Synchronous Programs on Multi-core Architecture.
J. of Systems Architecture, Elsevier, 21 pages, 2017. To appear. ©1
17 F. Smirnov, M. Glaß, F. Reimann and J. Teich.
Optimizing Message Routing and Scheduling in Automotive Mixed-Criticality Time-Triggered Networks.
To appear in the Proceedings of the 54th ACM/EDAC/IEEE Design Automation Conference (DAC 2017), 6p., Austin, TX, U.S.A., June 18-22, 2017. ©1
16 J. Pirkl, A. Becher, J. Echavarria, J. Teich and S. Wildermann.
Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics.
To appear in Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems (SCOPES), pp. 1-4, June, 2017. ©1
15 J. Fickenscher, S. Reinhart, M. Bouzouraa, F. Hannig and J. Teich.
Convoy Tracking for ADAS on Embedded GPUs.
To appear in Proceedings of the IEEE Intelligent Vehicles Symposium (IV), Redondo Beach, CA, USA, June 11-14, 2017. ©3
14 A. Zaib, J. Heisswolf, A. Weichslgartner, T. Wild, J. Teich, J. Becker and A. Herkersdorf.
Efficient Task Spawning for Shared Memory and Message Passing in Many-core Architectures.
To appear in Journal of Systems Architecture (JSA), 2017. ©1
13 B. Pourmohseni, M. Glaß and J. Teich.
Automatic Operating Point Distillation for Hybrid Mapping Methodologies.
In Proceedings of Design, Automation and Test in Europe (DATE 2017), Lausanne, Switzerland, March 27-31, 2017. To appear.. ©1
12 F. Smirnov, M. Glaß, F. Reimann and J. Teich.
Formal Timing Analysis of Non-Scheduled Traffic in Automotive Scheduled TSN Networks.
To appear in Proceedings of Design, Automation and Test in Europe (DATE 2017), Lausanne, Switzerland, March 27-31, 2017. ©1
11 T. Schwarzer, A. Weichslgartner, M. Glaß, S. Wildermann, P. Brand and J. Teich.
Symmetry-eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures.
To appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017 . ©1
10 Z. Salcic, H. Park, J. Teich, A. Malik and M. Nadeem.
NoC-HMP: A Heterogeneous Multicore Processor for Embedded Systems Designed in SystemJ.
In ACM Transactions on Design Automation of Electronic Systems (TODAES), 2017. Accepted. ©1
9 H. Köstler, C. Schmitt, S. Kuckuk, S. Kronawitter, F. Hannig, J. Teich, U. Rüde and C. Lengauer.
A Scala Prototype to Generate Multigrid Solver Implementations for Different Problems and Target Multi-Core Platforms.
International Journal of Computational Science and Engineering, 14(2), pp. 150-163, 2017. ©1
8 H. Khdr, S. Pagani, É. Sousa, V. Lari, A. Pathania, F. Hannig, M. Shafique, J. Teich and J. Henkel.
Power Density-Aware Resource Management for Heterogeneous Tiled Multicores.
IEEE Transactions on Computers (TC), 66(3), pp. 488-501, 2017. ©3
[doi>10.1109/TC.2016.2595560]
7 O. Reiche, M. Özkan, F. Hannig, J. Teich and M. Schmid.
Loop Parallelization Techniques for FPGA Accelerator Synthesis.
In Journal of Signal Processing Systems (JSPS), 2017. ©1
[doi>10.1007/s11265-017-1229-7]
6 H. Aliee, E. Borgonovo, M. Glaß and J. Teich.
On the Boolean Extension of the Birnbaum Importance to Non-Coherent Systems.
In J. Reliability Engineering & System Safety, vol. 160,pp. 191-200, 2017. ©1
[doi>10.1016/j.ress.2016.12.013]
5 H. Aliee, A. Banaiyianmofrad, M. Glaß, J. Teich and N. Dutt.
Redundancy-aware Design Space Exploration for Memory Reliability in Many-cores.
In Proc. Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'17), February 8-9, Bremen, Germany, pp. 1-12, 2017. ISBN 978-3-8440-4996-1. ©1
4 J. Teich.
Run-Time Monitoring and Enforcement of Non-functional Program Properties of Invasive Programs: Terms and Definitions.
Technischer Bericht, Lehrstuhl für Informatik 12, Friedrich-Alexander-Universität Erlangen-Nürnberg, 2017. ©1
3 A. Weichslgartner.
Application Mapping Methodologies for Invasive NoC-Based Architectures.
Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, January 24, 2017. ©1
2 R. Rosales.
Holistic Actor-Oriented Modeling of Embedded Systems for ESL Power Consumption Evaluation.
Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, January 13, 2017. ©1
1 F. Khosravi, M. Glaß and J. Teich.
Automatic Reliability Analysis in the Presence of Probabilistic Common Cause Failures.
To appear in IEEE Transactions on Reliability, 2017. ©1
[doi>10.1109/TR.2016.2638320]

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