Friedrich-Alexander-Universität DruckenUnivisEnglish FAU-Logo
Techn. Fakultät Willkommen am Department Informatik FAU-Logo
Codesign
Lehrstuhl für Informatik 12
Daniel Ziener
CV
Research
Education
Publications
Department Informatik  >  Informatik 12  >  Personal  >  Daniel Ziener
Dr.-Ing. Daniel Ziener Daniel Ziener
Samariá Gorge, Crete, Greece
Address:
I'm now at Technische Universität Hamburg-Harburg:
https://www.tuhh.de/es/esd/people/dziener.html
Email:
daniel.ziener@informatik.uni-erlangen.de
CV
March 31, 1978 born in Alzenau i.Ufr., Germany
08/2002 Diploma degree in EE, University of Applied Sciences Aschaffenburg, Germany
09/2002 - 03/2003 Developer at the University of Applied Sciences Aschaffenburg, Germany
05/2003 - 06/2009 Researcher and developer at the Fraunhofer Institute for Integrated Circuits (IIS), Germany
since 2003 Researcher at the Department of Computer Science 12 (Hardware-Software-Co-Design), University of Erlangen-Nuremberg, Germany
since 2010 Head of the Reconfigurable Computing Group at the Department of Computer Science 12 (Hardware-Software-Co-Design), University of Erlangen-Nuremberg, Erlangen, Germany
07/2010 Dr.-Ing. degree in Computer Science, University of Erlangen-Nuremberg, Erlangen, Germany
since 11/2015 Substitute Professor, Technische Universität Hamburg-Harburg, Hamburg, Germany
Experience
Petri AG, Aschaffenburg, Germany
09/1994 - 07/1997
Apprenticeship: electrical engineering
IBM Entwicklung GmbH, Böblingen, Germany
09/2000 - 02/2001
Internship at IBM Germany Development Labs. Verification of dynamic logic SRAM models.
University of Applied Sciences Aschaffenburg, Germany
10/2001 - 08/2002
Diploma: Analysis and hardware implementation of a multi symbol arithmetic coder.
University of Applied Sciences Aschaffenburg, Germany
09/2002 - 03/2003
Project thesis: Analysis and implementation of an Alarm and Status Management System with an J2EE Application Server
Fraunhofer Institute for Integrated Circuits (IIS), Germany
05/2003 - 06/2009
Design and implementation of high speed FPGA cores for image and signal processing
Research Interests
IP core watermarking
Design of signal processing FPGA cores
Reliable and fault tolerant embedded systems
Efficient usage of FPGA structures
Secure embedded systems
Partial dynamic reconfiguration
Education
Lectures
Reconfigurable Computing
FPGA-Online Advanced Course (VHDL)
Exercises
Embedded Systems
Elektronik programmierbarer Digitalsysteme
Labs
SoC Design
Awards
Best Paper Award, FPT 2006 D. Ziener and J. Teich. FPGA Core Watermarking Based on Power Signature Analysis. In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2006), pp. 205-212, Bangkok, Thailand, December 13-15, 2006.
HiPEAC Award, 2010 D. Ziener, F. Baueregger and J. Teich. Using the Power Side Channel of FPGAs for Communication. In Proceedings of the 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 10), Charlotte, USA, May 02-04, pp. 237-244, 2010.
Publications
Books:
Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs Daniel Ziener.
Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs. Dissertation, University of Erlangen-Nuremberg, ISBN 978-3-86853-657-7, Verlag Dr. Hut, Munich, Germany, July, 2010.
[Buy] [Download]
All Publications:
2016
46 D. Ziener, F. Bauer, A. Becher, C. Dennl, K. Meyer-Wegener, U. Schürfeld, J. Teich, J. Vogt and H. Weber.
FPGA-Based Dynamically Reconfigurable SQL Query Processing.
ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 9, no. 4, Article 25, July 2016. ©1
45 D. Koch, D. Ziener and F. Hannig.
FPGA versus Software Programming: Why, When, and How?.
In Dirk Koch, Frank Hannig, and Daniel Ziener, editors, FPGAs for Software Programmers, chapter 1, pp. 1-21. Springer, 2016. ©1
[doi>10.1007/978-3-319-26408-0_1]
44 D. Koch, F. Hannig and D. Ziener.
FPGAs for Software Programmers.
327 pages, Springer, 2016, ISBN 978-3-319-26406-6. ©1
[doi>10.1007/978-3-319-26408-0]
43 A. Becher, J. Echavarria, D. Ziener, S. Wildermann and J. Teich.
A LUT-Based Approximate Adder.
In Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2016). Washington DC, USA, May 1-3, 2016. ©1
[doi>10.1109/FCCM.2016.16]
2015
42 A. Becher, D. Ziener, K. Meyer-Wegener and J. Teich.
A Co-Design Approach for Accelerated SQL Query Processing via FPGA-based Data Filtering.
In Proceedings of 2015 International Conference on Field-Programmable Technology (FPT '15), Queenstown, New Zealand, December 7--9, 2015. ©3
[doi>10.1109/FPT.2015.7393148]
41 A. Becher, J. Echavarria, D. Ziener and J. Teich.
Approximate Adder Structures on FPGAs.
Presented at the Workshop on Approximate Computing, Paderborn, Germany, October 15-16, 2015. ©1
40 F. Hannig, D. Koch and D. Ziener.
Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015).
104 pages, London, United Kingdom, 2015. arXiv: 1508.06320 [cs.AR]. ©1
39 R. Glein, F. Rittner, A. Becher, D. Ziener, J. Frickel, J. Teich and A. Heuberger.
Reliability of Space-Grade vs. COTS SRAM-Based FPGA in N-Modular Redundancy.
In Proceedings of 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Montreal, QC, Canada, June 15--18, 2015. ©1
[doi>10.1109/AHS.2015.7231159]
2014
38 A. Becher, F. Bauer, D. Ziener and J. Teich.
Energy-Aware SQL Query Acceleration through FPGA-Based Dynamic Partial Reconfiguration.
Proceedings of the Conference on Field-Programmable Logic and Applications (FPL 2014), Munich, Germany, pp. 662 - 669, Sep 2-4, 2014. ©3
[doi>10.1109/FPL.2014.6927502]
37 F. Hannig, D. Koch and D. Ziener.
Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014).
82 pages, Munich, Germany, 2014. arXiv: 1408.4423 [cs.AR]. ©1
36 B. Schmidt, D. Ziener and J. Teich.
Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning.
In Proceedings of the Reconfigurable Architectures Workshop (RAW), pp. 299-304, Phoenix, USA, May 2014. ©3
[doi>10.1109/IPDPSW.2014.41]
35 R. Glein, B. Schmidt, F. Rittner, J. Teich and D. Ziener.
A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor.
In Proceedings of Field-Programmable Custom Computing Machines (FCCM 2014), pp. 251-258, Boston, Massachusetts, USA, May 11-13, 2014. ©3
[doi>10.1109/FCCM.2014.79]
34 B. Schmidt, D. Ziener and J. Teich.
An Automatic Netlist and Floorplanning Approach to Improve the MTTR of Scrubbing Techniques.
Poster Presentation at the International Symposium on Field-Programmable Gate Arrays (FPGA) 2014. Monterey, California, USA. ©1
[doi>10.1145/2554688.2554730]
33 B. Schmidt, D. Ziener and J. Teich.
A Netlist Analysis Approach to Classify FPGA Configuration Bits in order to Optimize Scrubbing.
Talk at the Workshop on Reconfigurable Computing at International Conference on High-Performance and Embedded Architectures and Compilers 2014 (HiPEAC) Vienna, Austria, January 2014 . ©1
2013
32 C. Dennl, D. Ziener and J. Teich.
Acceleration of SQL Restrictions and Aggregations through FPGA-based Dynamic Partial Reconfiguration.
Proceedings of the IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM), Seattle, USA, Apr. 28-30, 2013. ©3
2012
31 S. Wildermann, F. Reimann, D. Ziener and J. Teich.
Symbolic System-level Design Methodology for Multi-Mode Reconfigurable Systems.
Journal on Design Automation for Embedded Systems, Springer, 2012. ©1
[doi>10.1007/s10617-012-9102-1]
30 T. Ziermann, A. Butiu, J. Teich and D. Ziener.
FPGA-based Testbed for Timing Behavior Evaluation of the Controller Area Network (CAN) .
In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, Dec.5-7, 2012. ©1
29 S. Wildermann, F. Reimann, D. Ziener and J. Teich.
System Level Synthesis Flow for Self-adaptive Multi-mode Reconfigurable Systems.
In Proceedings of Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), pp. 4-7, Oslo, Norway, September 01, 2012. ©1
28 C. Dennl, D. Ziener and J. Teich.
On-the-fly Composition of FPGA-Based SQL Query Accelerators Using A Partially Reconfigurable Module Library.
Proceedings of the IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM), pp. 45-52, Toronto, Canada, April 29th - May 1st, 2012. ©3
[doi>10.1109/FCCM.2012.18]
27 D. Koch, J. Torresen, C. Beckhoff, D. Ziener, C. Dennl, V. Breuer, J. Teich, M. Feilen and W. Stechele.
Partial Reconfiguration on FPGAs in Practice - Tools and Applications.
In Proceedings of the 2012 Architecture of Computing Systems (ARCS'12), Munich, Germany. Feb. 28-29, 2012. ©1
2011
26 T. Ziermann, B. Schmidt, M. Mühlenthaler, D. Ziener, J. Angermeier and J. Teich.
An FPGA Implementation of a Threat-based Strategy for Connect6.
Proceedings of the International Conference on Field-Programmable Technology (FPT'11), New Delhi, India. Dec. 12-14, 2011. ©1
25 J. Angermeier, D. Ziener, M. Glaß and J. Teich.
Runtime Stress-Aware Replica Placement on Reconfigurable Devices under Safety Constraints.
Proceedings of the International Conference on Field-Programmable Technology (FPT'11), pp. 1-6, New Delhi, India. Dec. 12-14, 2011. ©1
[doi>10.1109/FPT.2011.6133247]
24 S. Wildermann, F. Reimann, D. Ziener and J. Teich.
Symbolic Design Space Exploration for Multi-Mode Reconfigurable Systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 129-138, Taipei, Taiwan. Oct. 9-14, 2011. (Best Paper Candidate). ©1
[doi>10.1145/2039370.2039393]
23 S. Wildermann, D. Ziener and J. Teich.
Unifying Partitioning and Placement for SAT-based Exploration of Heterogeneous Reconfigurable SoCs.
Proceedings of the Conference on Field Programmable Logic and Applications (FPL 2011), pp. 429-434, Chania, Crete, Greece, Sep. 5-7, 2011. ©1
22 J. Angermeier, D. Ziener, M. Glaß and J. Teich.
Stress-Aware Module Placement on Reconfigurable Devices.
Proceedings of the Conference on Field-Programmable Logic and Applications (FPL 2011), pp. 277-281, Chania, Crete, Greece. Sep 5-7. 2011. ©1
21 D. Ziener, S. Wildermann, A. Oetken, A. Weichslgartner and J. Teich.
A Flexible Smart Camera System based on a Partially Reconfigurable Dynamic FPGA-SoC.
Proceedings of the Workshop on Computer Vision on Low-Power Reconfigurable Architectures at FPL 2011, pp. 29-30, Chania, Crete, Greece, Sep. 4, 2011. ©1
20 J. Teich and D. Ziener.
Verifying the Authorship of Embedded IP Cores: Watermarking and Core Identification Techniques.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'11), pp. 93-103, Las Vegas, USA, Jul. 18-21, 2011. ©1
2010
19 D. Ziener and J. Teich.
New Directions for FPGA IP Core Watermarking and Identification.
In Dagstuhl Seminar 10281 Proceedings, 2010. ©1
18 D. Ziener, M. Schmid and J. Teich.
Robustness Analysis of Watermark Verification Techniques for FPGA Netlist Cores.
In Design Methodologies for Secure Embedded Systems, A. Biedermann and H. Gregor Molter (Eds.), Lecture Notes in Electrical Engineering, volume 78, pp. 105-127, Springer-Verlag, Berlin Heidelberg, 2010. ©1
17 D. Ziener.
Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs.
Dissertation, Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, ISBN 978-3-86853-657-7, Verlag Dr. Hut, Munich, Germany, July, 2010. ©1
16 D. Ziener, F. Baueregger and J. Teich.
Multiplexing Methods for Power Watermarking.
In Proceedings of the IEEE Int. Symposium on Hardware-Oriented Security and Trust (HOST 2010), pp. 54-59, Anaheim, USA, June 13-14, 2010. ©2
15 D. Ziener, F. Baueregger and J. Teich.
Using the Power Side Channel of FPGAs for Communication.
In Proceedings of the 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'10), pp. 237-244, Charlotte, USA, May 02-04, 2010. ©1
14 M. May, N. Wehn, A. Bouajila, J. Zeppenfeld, W. Stechele, A. Herkersdorf, D. Ziener and J. Teich.
A Rapid Prototyping System for Error-Resilient Multi-Processor Systems-on-Chip.
Proceedings of Design, Automation and Test in Europe (DATE'10), Dresden, Germany, March 08-12, pp. 375-380, 2010. ©1
2009
13 V. Schöber, O. Bringmann, A. Herkersdorf, W. Stechele, N. Wehn, M. May, D. Ziener, A. Bouajila, D. Baldin, J. Zeppenfeld, B. Sanders, J. Teich, M. Sebastian, R. Ernst and D. Treytnar.
AIS-Autonomous Integrated Systems.
In newsletter edacentrum 04 2009, pp. 05-13, edacentrum, Hannover, 2009. ©1
12 D. Ziener and J. Teich.
Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs.
Int. Journal of Autonomous and Adaptive Communications Systems, Vol. 2, No. 3, pp. 256-275, Inderscience Enterprises Ltd, 2009. ©1
2008
11 M. Schmid, D. Ziener and J. Teich.
Netlist-Level IP Protection by Watermarking for LUT-Based FPGAs.
In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2008), pp. 209-216, Taipei, Taiwan, December 08-10, 2008. ©1
10 D. Ziener and J. Teich.
Concepts for Autonomous Control Flow Checking for Embedded CPUs.
In Proceedings of the 5th International Conference on Autonomic and Trusted Computing (ATC08), pp. 234-248, Oslo, Norway, June 23-25, 2008. ©1
9 D. Ziener and J. Teich.
Power Signature Watermarking of IP Cores for FPGAs .
Journal of Signal Processing Systems, Volume 51, Number 1 / April 2008, pages 123-136, Springer. ©1
2007
8 D. Ziener and J. Teich.
Watermarking Apparatus, Software Enabling an Implementation of an Electronic Circuit Comprising a Watermark, Method for Detecting a Watermark and Apparatus for Detecting a Watermark.
US-Patent US2007/0220263, Anmeldetag 19.10.2006 aus EP 1835425, veröffentlicht 20.09.2007, Patentklassen (IPC) H04L 9/00. ©1
7 D. Ziener and J. Teich.
Watermarking apparatus, software enabling an implementation of an electronic circuit comprising a watermark, method for detecting a watermark and apparatus for detecting a watermark.
Europäisches Patent EP1835425, Anmeldetag 17.03.2006, veröffentlicht 19.09.2007, Patentklassen (IPC) G06F 17/50; G06F 21/00. ©1
6 W. Stechele, O. Bringmann, R. Ernst, A. Herkersdorf, K. Hojenski, P. Janacik, F. Rammig, J. Teich, N. Wehn, J. Zeppenfeld and D. Ziener.
Concepts for Autonomic Integrated Systems.
In Proceedings of edaWorkshop07, Hannover, Germany, June 19-20, 2007. ©1
5 W. Stechele, O. Bringmann, R. Ernst, A. Herkersdorf, K. Hojenski, P. Janacik, F. Rammig, J. Teich, N. Wehn, J. Zeppenfeld and D. Ziener.
Autonomic MPSoCs for Reliable Systems.
In Proceedings of Zuverlässigkeit und Entwurf (ZuD 2007), pp. 137-138, Munich, Germany, March 26-28, 2007. ©1
2006
4 D. Ziener and J. Teich.
FPGA Core Watermarking Based on Power Signature Analysis.
In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2006), pp. 205-212, Bangkok, Thailand, December 13-15, 2006. ©1
3 D. Ziener, S. Aßmus and J. Teich.
Identifying FPGA IP-Cores based on Lookup Table Content Analysis.
In Proceedings of 16th International Conference on Field Programmable Logic and Applications, Madrid, Spain, pp. 481-486, August 28-30, 2006. ©1
2 H. Adel, G. Hofmann, R. Wansch and D. Ziener.
A Method for Measuring Time Delay Behavior of Antennas.
First AMTA Europe Symposium, Munich, May 1-4, 2006. ©1
2005
1 D. Ziener and J. Teich.
Evaluation of Watermarking methods for FPGA-based IP-cores.
Technical Report 01-2005, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, March 2005. ©1

Copyrights:
©1The documents distributed by this server have been provided by the contributing authors as a means to ensure timely dissemination of scholarly and technical work on a noncommercial basis. Copyright and all rights therein are maintained by the authors or by other copyright holders, notwithstanding that they have offered their works here electronically. It is understood that all persons copying this information will adhere to the terms and constraints invoked by each author's copyright. These works may not be reposted without the explicit permission of the copyright holder.
©2©2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
©3©2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
  Impressum Stand: 21 December 2015.   D.Z.