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Lehrstuhl für Informatik 12
Jürgen Teich
Department Informatik  >  Informatik 12  >  Personal  >  Jürgen Teich

Prof. Dr.-Ing. Jürgen Teich

Address:
Department of Computer Science 12
(Hardware-Software-Co-Design)
University of Erlangen-Nuremberg
Cauerstr. 11
D-91058 Erlangen
Germany
Phone: +49 9131 85-25150
Fax: +49 9131 85-25149

Email: teich@informatik.uni-erlangen.de

December 15, 1964 born in Kaiserslautern, Germany
1989 Diploma degree in EE, Univ. of Kaiserslautern, Germany
1993 Dr.-Ing. degree in EE, Univ. of Saarland, Germany
1994 Univ. of California at Berkeley, Dept. of EECS, postdoc in the PTOLEMY project
1995-1998 senior researcher and lecturer at the Federal Institute of Technology (ETH) Zurich, Switzerland in the research group of Prof. Lothar Thiele, Institute TIK
1996 PD Dr.-Ing., Habilitation entitled Synthesis and Optimization of Digital Hardware/Software Systems, ETH Zurich, Switzerland
1998-2002 Chairholder of the Computer Engineering Laboratory (C4), University of Paderborn, Germany
2003-2011 Chair for Hardware-Software-Co-Design (C4), Department of Computer Science, University of Erlangen-Nuremberg, Germany
Aug 2005 Visitor, Intel Corp., Santa Clara, U.S.A.
July-Oct 2006 Visiting Researcher, Xilinx Research Laboratories, San Jose, U.S.A.
Aug-Nov 2008 Visiting Professor, School of Computing, National University of Singapore (NUS), Singapore
2004-2012 Elected DFG-Reviewer for "Computer Architecture and Embedded Systems"
July-August 2012 Visiting Professor, Department of Electrical and Computer Engineering, The University of Auckland, New Zealand
July-August 2014 Visitor, Department of Electrical and Computer Engineering, McGill University, Montreal, Canada
Since 2011 Chair for Hardware-Software-Co-Design (W3), Department of Computer Science, University of Erlangen-Nuremberg, Germany
Since 2011 Elected Member of Academia Europaea, the Academy of Europe, Section Informatics

Embedded Systems
Scheduling Theory and Optimization
Massively Parallel VLSI Architectures
Invasive Computing

Published Books

Synthesis and Optimization of Digital Hardware/Software Systems
Specification and Verification of Digital Hardware/Software Systems
Design of Image Processing Embedded Systems Using Multidimensional Data Flow
Dynamically Reconfigurable Systems
Domain-Specific Processors - Systems, Architectures, Modeling and Simulation
Embedded Processor Design Challenges
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2007)
Architecture of Computing Systems - (ARCS 2016)

Conference organization activities

2003, Proceedings Chair, Design Automation and Test in Europe (DATE'03), Munich, Germany
2004, PhD Forum Chair, Field Programmable Logic and its applications (FPL'04), Antwerp, Belgium
2004, Proceedings Chair, Design Automation and Test in Europe (DATE'04), Paris, France
2005, Workshop Organization, The Future of Reconfigurable Computing, Design Automation and Test in Europe (DATE'04), Munich, Germany
2006, Workshop Organization, Dagstuhl Seminar 06141, Dynamically Reconfigurable Architectures, Schloss Dagstuhl, Wadern, Germany
2006, GECCO 2006: Mitglied TPC
2006, Local Chair, Topic Embedded Parallel Systems, EUROPAR'06, Dresden, Germany
2006, Panel Chair, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'06), Seoul, Korea
2006, Local Chair, Euro-Par 2006, European Conference on Parallel Computing, Parallel Embedded Systems, Dresden, Germany
2006, International Conference on Field-Programmable Technology (ICFPT) 2006: TPC
2007, Conference Organization, 10. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Erlangen, Germany
2007, Program Chair, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'07), ESWEEK 2007, Salzburg, Austria
2007, ARCS 2007: Mitglied TPC
2007, GECCO 2007: Mitglied TPC
2007, International Conference on Field-Programmable Technology (ICFPT) 2007: TPC
2007, SCOPES 2007: TPC
2008, Design Automation Conference (DAC'08), Mitglied des TPC
2008, Autonomic and Trusted Computing (ATC), Mitglied des PC
2008, Topic Chair, CODES+ISSS 2008, Multi-Processors and MPSoC
2008, Design Automation Conference (DAC) 2008, Mitglied des TPC
2008, Design, Automation and Test in Europe (DATE) 2008, Mitglied TPC und EDAA Phd forum committee
2008, The Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'2008): Mitglied des TPC
2008, International Conference on Field-Programmable Technology (ICFPT) 2008: TPC
2008, MPSoC 2008: Eingeladener Vortragender
2008, SCOPES 2008: TPC
2008, IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS) 2008: TPC
2008, IC SAMOS 2008: Mitglied des Steuerkreises und TPCs
2008, IEEE Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP08), Mitglied des TPC
2008, Program Chair, International Conference on Field Programmable Logic and Applications (FPL'08), Heidelberg, Germany
2008, Genetic and Evolutionary Computation Conference (GECCO-2008): Mitglied des TPC
2008, Reconfigurable Architectures Workshop (RAW 2008): Mitglied des TPC
2008, Zuverlässigkeit und Entwurf 2008: Mitglied des PC
2008, ARCS 2008: Mitglied TPC
2008, GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'2008): Mitglied des PC
2008, Topic Chair, Multiprocessors and MPSoC, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'08), ESWEEK 2008, Atlanta, USA
2009, Design Automation Conference (DAC'09), Mitglied des TPC
2009, Design, Automation and Test in Europe (DATE) 2009, Mitglied TPC und EDAA Phd forum committee und Organisator eines Friday-Workshops
2009, International Symposium on FPGAs (FPGA 2009): Mitglied des PC
2009, IEEE Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP09), Mitglied des TPC
2009, VLSI-DAT 2009: Mitglied TPC
2009, International Conference on Field-Programmable Technology (ICFPT) 2009, Sydney, Australia, TPC
2009, Asia and South-Pacific Design Automation Conference (ASP-DAC) 2009: TPC Mitglied, Track Embedded and Real-Time Systems
2009, International Conference on Evolutionary Multi-Criterion Optimization (EMO'09): Mitglied des TPC
2009, Reconfigurable Architectures Workshop (RAW 2009): Mitglied des TPC
2009, EMSOFT'09, Miglied des TPC, ESWEEK 2009, Grenoble, France
2009, GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'2009): Mitglied des PC
2009, GECCO 2009: Mitglied TPC
2009, SCOPES 2009: TPC
2009, ARCS 2009: Mitglied TPC
2009, International Conference on Field Programmable Logic and Applications (FPL'09), Mitglied des Organizing Committees, Prague, Czech Republic
2009, Zuverlässigkeit und Entwurf 2009, Mitglied des PC
2009, Autonomic and Trusted Computing (ATC), Mitglied des PC
2009, Invited Keynote Speech, International Conference on Field-Programmable Technology (ICFPT) 2009, Sydney, Australia
2009, Topic Chair, Multiprocessors and MPSoC, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'09), ESWEEK 2009, Grenoble, France
2010, Design Automation Conference (DAC'10), Mitglied des TPC
2010, VLSI-DAT 2010: Mitglied TPC, Taiwan
2010, GECCO 2010: Mitglied TPC, EMO Track
2010, Program Chair, IEEE Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP10), Rennes, France
2010, Reconfigurable Architectures Workshop (RAW 2010): Mitglied des TPC
2010, SCOPES 2010: TPC
2010, International Symposium on FPGAs (FPGA 2010): Mitglied des PC
2010, International Conference on Field Programmable Logic and Applications (FPL'10), Mitglied des Organizing Committees, Milano, Italy
2010, First IEEE Workshop on Self-Organizing Real-Time Systems - SORT 2010, TPC
2010, Multiprocessors and MPSoC, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'10), ESWEEK 2010, Scottsdale, Arizona, USA. Track Chair.
2010, RECONFIG 2010, Int. Conf. on ReConFigurable Computing and FPGAs, Cancun, Mexico. Track Chair
2010, Workshop Organization, Dagstuhl Seminar 10281, Dynamically Reconfigurable Architectures, Schloss Dagstuhl, Wadern, Germany
2010, ARCS 2010. TPC Member C
2010, Autonomic and Trusted Computing (ATC), Member TPC
2010, Zuverlässigkeit und Entwurf 2010, Mitglied des PC
2010, Design, Automation and Test in Europe (DATE) 2010, Member TPC and Member EDAA Jury Outstanding Dissertation Award
2010, ICCAD 2010, Member TPC, Embedded Systems Track
2010, International Conference on Field-Programmable Technology (ICFPT) 2010, Beijing, China. Member TPC
2011, EDAA Dissertation Award 2010, Topic 1: new directions in embedded system design and embedded software. Topic Chair
2011, International Conference on Evolutionary Multi-Criterion Optimization (EMO'11), Ouro Preto, Brazil. Member TPC
2011, Design, Automation and Test in Europe (DATE) 2011, TPC Member
2011, ARCS 2011: Mitglied TPC
2011, SEAL-2011: Simulated Evolution and Learning. TPC Member
2011, PARELEC 2011: The 6th Int. Symp. on Parallel Computing in Electrical Engineering. Member TPC
2011, International Symposium on FPGAs (FPGA 2011). Member TPC
2011, Zuverlässigkeit und Entwurf 2011. Mitglied TPC
2011, International Conference on Field-Programmable Technology (ICFPT) 2011, Delhi, India. Member TPC
2011, SCOPES 2011. Member TPC
2011, GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'2011): Mitglied des PC
2011, Reconfigurable Architectures Workshop (RAW 2011): Mitglied des TPC
2011, Genetic and Evolutionary Computation Conference (GECCO-2011): Mitglied des TPC Track EMO
2011, IEEE Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP11), Mitglied des TPC
2011, International Conference on Field Programmable Logic and Applications (FPL'11), Mitglied des Organizing Committees, Chania, Crete, Greece
2011, Track Chair, RECONFIG 2011, Int. Conf. on ReConFigurable Computing and FPGAs
2011, IEEE Int. Conf. on Computer Design (ICCD) 2011, Amhurst, MA, USA, Member TPC, Processor Architecture Track
2011, ICCAD 2011, Mitglied des TPC, Embedded Systems Track
2011, Autonomic and Trusted Computing (ATC), Mitglied des PC
2011, Track Chair, System Synthesis and Design Space Exploration, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'11), ESWEEK 2011, Taipei, Taiwan
2011, Second IEEE Workshop on Self-Organizing Real-Time Systems - SORT 2011, TPC
Since 2011, Associate Editor for ACM Transactions on Design Automation of Electronic Systems (TODAES)
2012, ARCS 2012: Mitglied TPC
2012, Design, Automation and Test in Europe (DATE) 2012, Proceedings Chair and TPC Member and Member EDAA Jury Outstanding Dissertation Award, Dresden, Germany
2012, Reconfigurable Architectures Workshop (RAW 2012): Mitglied des TPC
2012, International Conference on Field-Programmable Technology (ICFPT) 2012, Seoul, Corea, TPC
2012, International Symposium on FPGAs (FPGA 2012): Mitglied des TPC
2012, VLSI 2012, the 25th Conference on VLSI Design, Hyderabad, India, 2012: Mitglied des TPC
2012, SCOPES 2012: Mitglied des TPC
2012, GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'2012): Mitglied des PC
2012, Genetic and Evolutionary Computation Conference (GECCO-2012): Mitglied des TPC Track EMO
2012, Third IEEE Workshop on Self-Organizing Real-Time Systems - SORT 2012, TPC
2012, IEEE Int. Conf. on Computer Design (ICCD) 2012, Member TPC, Processor Architecture Track
2012, International Conference on Field Programmable Logic and Applications (FPL'12), Mitglied des Organizing Committees, Oslo, Norway
2012, IEEE Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP12), Mitglied des TPC
2012, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'12), Track Chair Large Scale System Architecture, ESWEEK 2012, Tampere, Finland
2012, Autonomic and Trusted Computing (ATC), Mitglied des PC
2012 RECONFIG 2012, Int. Conf. on ReConFigurable Computing and FPGAs, Cancun, Mexico. Track Co-Chair
2012, ICCAD 2012, Mitglied des TPC, Embedded Systems Hardware Track
2012, Zuverlässigkeit und Entwurf 2012: Mitglied des PC
2012, Invited Keynote, Exploiting Dynamic Hardware Reconfigurability for Efficiency, Performance, and Reliability, NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2012), Erlangen, Germany, June 27, 2012
2013, VLSI 2013, the 25th Conference on VLSI Design, Pune, India, 2013: Reviewer
2013, ADAPT 2013, Int. Workshop on Adaptive Self-tuning Computing Systems (co-located with HiPEAC 2013), Berlin, Member TPC
2013, ARCS 2013, Workshop Self-Organization in Organic and Autonomic Computing Systems, Prague, Czech Republic: Mitglied TPC
2013, SAOS 2013, Int. Workshop on Self-optimization in Organic and Autonomic Computing Systems (co-located with ARCS 2013), Prague, Member TPC
2013, FPGA 2013, International Symposium on FPGAs: TPC Member
2013, M-SCOPES 2013, St. Goar, Germany, TPC Member
2013, GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'2013): Mitglied des PC
2013, Design, Automation and Test in Europe (DATE) 2013, Proceedings Chair and TPC Member, Grenoble, France, March 2013
2013, SORT 2013, Fourth IEEE Workshop on Self-Organizing Real-Time Systems, Member TPC
2013, Genetic and Evolutionary Computation Conference (GECCO-2013): Mitglied des TPC Track EMO
2013, ESOS 2013, Workshop on Self-Organizing Systems (co-located with ICAC 2013), San Jose, Member TPC
2013, ETFA 2013, 18th IEEE Int. Conf. on Emerging Technologies and Factory Automation, Cagliari, Italy, September 2013, Track Co-Chair, Real Time and Networked Embedded Systems
2013, The 21st IEEE Int. Symposium on Field-Programmable Custom Computing Machines (FCCM'2013), Seattle, Washington, USA, April 2013. TPC Member
2013, International Conference on Field Programmable Logic and Applications (FPL'13), Member Organizing Committee, Porto, Portugal, September 2013
2013 RECONFIG 2013, Int. Conf. on ReConFigurable Computing and FPGAs, Cancun, Mexico. Track Co-Chair
2013, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'13), ESWEEK 2013, Montreal, Canada. Member TPC
2013, Invited Keynote, Invasive Computing - The Quest for Many-Core Efficiency and Predictability, 26th Int. Conf. on Architecture of Computing Systems, Prague, Czech Republic, February 20, 2013
2013, International Conference on Field-Programmable Technology (ICFPT) 2013, Kyoto, Japan, TPC
2013, Autonomic and Trusted Computing (ATC), Mitglied des PC
2013, IEEE Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP13), Mitglied des TPC
2013, Invited Keynote, Invasive Computing - The Quest for Many-Core Efficiency and Predictability, 6th Swedish Workshop on Multicore Computing, Halmstad, Sweden, November 25, 2013
2014, 8th Int. Symposium on Networks-on-Chip (NOCS 2014), Ferrara, Italy, 2014. TPC Member
2014, The 22nd IEEE Int. Symposium on Field-Programmable Custom Computing Machines (FCCM'2014), Boston, USA, May 11-13, 2014: TPC Member
2014, GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'2014): Mitglied des PC
2014, ARCS 2014, Luebeck, Germany, February 2014: Member TPC
2014, ADAPT 2014, Int. Workshop on Adaptive Self-tuning Computing Systems (co-located with HiPEAC 2014), Vienna, Member TPC
2014, RTAS 2014, 20th IEEE Real-Time and Embedded Technology and Applications Symposium, (co-located with CPSWEEK 2014), Berlin, Member TPC
2014, Design, Automation and Test in Europe (DATE) 2014, Special Day Chair and TPC Member, Dresden, Germany, March 2014
2014, FPGA 2014, International Symposium on FPGAs, Monterey, CA, February 2014: TPC Member
2014, edaWorkshop14, Hannover, May 2014: TPC Member
2014, IFIP First International Workshop on Design Space Exploration of Cyber-Physical Systems2014 (co-located with CPSWeek), Berlin, Germany, April 2014: Member TPC
2014, SAOS 2014, Int. Workshop on Self-optimization in Organic and Autonomic Computing Systems (co-located with ARCS 2014), Luebeck, Germany, February 2014: Member TPC
2014, M-SCOPES 2014, St. Goar, Germany, June 2014. TPC Member
2014, Racing 2014, 1st Workshop on Resource awareness and adaotivity in multi-core computing (co-located with the IEEE European Test Symposium), Paderborn, Germany, May 2014. General Chair.
2014, International Conference on Field Programmable Logic and Applications (FPL'14), Munich, Germany, 2014: Member TPC
2014, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'14), ESWEEK 2014, New Delhi, India, TPC Member
2014, 12th IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia 2014), New Delhi, India, October 2014, TPC Member
2014, International Conference on Field-Programmable Technology (ICFPT) 2014, Shanghai, China, 2014: TPC Member
2014, Genetic and Evolutionary Computation Conference (GECCO-2014): Mitglied des TPC Track EMO
2014, Autonomic and Trusted Computing (ATC), Mitglied des PC
2014, Int. Conf. on ReConFigurable Computing and FPGAs (RECONFIG 2014), Cancun, Mexico, 2014: TPC Member
2014, IEEE Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP14), Mitglied des TPC
2015, 8th International Conference on Evolutionary Multi-Criterion Optimization (EMO 2015), Guimaraes, Portugal, 2015: Member TPC
2015, The 23rd IEEE Int. Symposium on Field-Programmable Custom Computing Machines (FCCM'2015), Vancouver, Canada, May 3-5, 2015: TPC Member
2015, Int. Conf. on ReConFigurable Computing and FPGAs (RECONFIG 2015), Cancun, Mexico, 2015,: TPC Member
2015, GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'2015): Mitglied des PC
2015, ARCS 2015, Porto, Portugal, March 24-27, 2015: Member TPC
2015, SAOS 2015, Int. Workshop on Self-optimization in Organic and Autonomic Computing Systems (co-located with ARCS 2015), Porto, Portugal, March 2015: Member TPC
2015, ADAPT 2015, Int. Workshop on Adaptive Self-tuning Computing Systems (co-located with HiPEAC 2015), Amsterdam: Member TPC
2015, VLSI Design 2015, 28th Int. Conf. on VLSI Design, Bangalore, India: Member TPC
2015, International Symposium on FPGAs (FPGA 2015), Monterey, USA, 2015: Member TPC
2015, International Conference on Field Programmable Logic and Applications (FPL'15), London, UK, 2015: Member TPC
2015, edaWorkshop15, Hannover, May 2014: TPC Member
2015, NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2015), Montreal, Canada, June 15-18, 2015: TPC Member
2015, SORT 2015, Sixth IEEE Workshop on Self-Organizing Real-Time Systems, Auckland, New Zealand. Member TPC
2015, M-SCOPES 2015, St. Goar, Germany, June 2015. TPC Member
2015, 9th Int. Symposium on Networks-on-Chip (NOCS 2015), Vancouver, Canada, September 28-30, 2015. TPC Member
2015, 13th Int. Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia 2015), Amsterdam, NL, October 08-09, 2015. TPC Member
2015, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'15), ESWEEK 2015, Amsterdam, The Netherlands, October 2015. TPC Member
2015, Genetic and Evolutionary Computation Conference (GECCO-2015): TPC Member Track EMO
2015, IEEE Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP15). TPC Member
2015, 36th IEEE Real-Time Systems Symposium (RTSS 2015), TPC Member, San Antonio, USA, December 2015
2015, Workshop on Approximate Computing (AC15), TPC Member, Paderborn, Germany, October 2015
2015, International Conference on Field-Programmable Technology (ICFPT) 2015, Queenstown, New Zealand, 2015: TPC Member
2015, Design, Automation and Test in Europe (DATE) 2015, Vice Program Chair and TPC Member, Grenoble, France, March 2015
2015, Design Automation Conference (DAC 2015), Track Chair, Embedded System Design Methodologies, San Francisco, USA, 2015
2016, VLSI Design 2016, 29th Int. Conf. on VLSI Design, Kolkata, India: Member TPC
2016, GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'2016): Mitglied des PC
2016, SCOPES 2016, St. Goar, Germany, May 23-25, 2016. TPC Member
2016, ARCS 2016, Erlangen, Germany, April 04-07, 2016: General Co-Chair
2016, International Symposium on FPGAs (FPGA 2016), Monterey, USA, 2016. Member TPC
2016, Design, Automation and Test in Europe (DATE) 2016, Program Chair, 2016
2016, Genetic and Evolutionary Computation Conference (GECCO-2016): TPC Member
2016, ACM International Conference on Computing Frontiers (CF16): TPC Member
2016, The 24th IEEE Int. Symposium on Field-Programmable Custom Computing Machines (FCCM'2016), Washington DC, USA, May 1-3, 2016: TPC Member
2016, FPGA4GPC - The International Conference on FPGA Reconfiguration for General-Purpose Computing, Hamburg, Germany, May 9-10, 2016: TPC Member
2016, 10th Int. Symposium on Networks-on-Chip (NOCS 2016), Nara, Japan, Aug 31-Sep 2, 2016. TPC Member
2016, IEEE Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP16), London, UK. TPC Member
2016, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'16), ESWEEK 2016, Pittsburgh, USA, October 2016. TPC Member
2016, International Conference on Field Programmable Logic and Applications (FPL'16), Lausanne, CH, 2016: Member TPC
2016, 14th Int. Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia 2016), Pittsburgh, USA, October 2016. TPC Member
2016, 14th ACM-IEEE Int. Conference on Formal Methods and Models for System Design (MEMOCODE'16), Kanpur, India, November 2016. TPC Member
2016, 3rd Workshop on Low-Power Dependable Computing (LPDC), Hangzhou, China, November 2016. TPC Member
2016, Workshop on Approximate Computing (AC16), TPC Member, Pittsburgh, USA, October 2016. TPC Member
2016, RECONFIG 2016, Int. Conf. on ReConFigurable Computing and FPGAs, Cancun, Mexico, 2016. Track Co-Chair.
2016, International Conference on Field-Programmable Technology (ICFPT) 2016, Xian, China, 2016: TPC Member
2017, Design, Automation and Test in Europe (DATE) 2017, Lausanne, CH, March 2017. TPC Member

Publications

2016
656 C. Schmitt, M. Schmid, S. Kuckuk, H. Köstler, J. Teich and F. Hannig.
Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution.
To appear in Parallel Processing Letters. ©1
655 Z. Salcic, M. Nadeem, H. Park and J. Teich.
Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-Core Processor.
In Proc. IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16), Lyon Congress Center, Lyon, France, September 21-23, 2016. ©1
654 J. Teich, M. Glaß, S. Roloff, W. Schröder-Preikschat, G. Snelting, A. Weichslgartner and S. Wildermann.
Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution using Invasive Computing.
In Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16), Lyon, France, September 21-23, 2016. ©1
653 J. Ah Sue, R. Hasholzner, J. Brendel, M. Kleinsteuber and J. Teich.
A Binary Time Series Model of LTE Scheduling for Machine Learning Prediction.
InProceedings 10th IEEE International Conference on Self-Adaptive and Self-Organizing Systems (SASO 2016), University of Augsburg, Augsburg, Germany, 12-16 September 2016. ©1
652 M. Özkan, O. Reiche, F. Hannig and J. Teich.
FPGA-Based Accelerator Design from a Domain-Specific Language.
To appear in Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL), Lausanne, Switzerland, August 29 - September 2, 2016. ©1
651 K. Häublein, M. Reichenbach, O. Reiche, M. Özkan, D. Fey, F. Hannig and J. Teich.
Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures.
To appear in Proceedings of the 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Island of Samos, Greece, July 18-21, 2016. ©1
650 H. Khdr, S. Pagani, É. Sousa, V. Lari, A. Pathania, F. Hannig, M. Shafique, J. Teich and J. Henkel.
Power Density-Aware Resource Management for Heterogeneous Tiled Multicores.
To appear in the IEEE Transactions on Computers (TC), 2016 . ©1
649 M. Witterauf, A. Tanase, F. Hannig and J. Teich.
Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays.
To appear in Proceedings of the 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), IEEE, London, United Kingdom, July 6-8, 2016. ©3
648 H. Aliee, M. Glaß, J. Teich and E. Borgonovo.
Guiding Genetic Algorithms Using Importance Measures for Reliable Design of Embedded Systems.
Accepted at 29th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. ©1
647 L. Fanucci and J. Teich.
Recap of the 2016 DATE Conference & Exhibition.
IEEE Design & Test of Computers, vol. 33, no. 4, pp. 114-117, 2016. ©1
[doi>10.1109/MDAT.2016.2570223]
646 M. Schmid, O. Reiche, F. Hannig and J. Teich.
HIPAcc.
In Dirk Koch, Frank Hannig, and Daniel Ziener, editors, FPGAs for Software Programmers, chapter 12, pp. 205-223. Springer, 2016. ©1
[doi>10.1007/978-3-319-26408-0_12]
645 S. Roloff, A. Pöppl, T. Schwarzer, S. Wildermann, M. Bader, M. Glaß, F. Hannig and J. Teich.
ActorX10: An Actor Library for X10.
In Proceedings of the 6th ACM SIGPLAN X10 Workshop (X10), pp. 24-29, ACM, Santa Barbara, CA, USA, June 14, 2016. ©1
[doi>10.1145/2931028.2931033]
644 F. Smirnov, M. Glaß, F. Reimann and J. Teich.
Formal Reliability Analysis of Switched Ethernet Automotive Networks under Transient Transmission Errors.
In Proceedings of the 53nd ACM/EDAC/IEEE Design Automation Conference (DAC 2016), 6p., Austin, TX, U.S.A., June 5-9, 2016, best paper candidate. ©1
643 A. Weichslgartner, S. Wildermann, J. Götzfried, F. Freiling, M. Glaß and J. Teich.
Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs.
In Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems (SCOPES), pp 153-162, Sankt Goar, Germany, May 23-25, 2016. ©1
[doi>10.1145/2906363.2906370]
642 A. Becher, J. Echavarria, D. Ziener, S. Wildermann and J. Teich.
A LUT-Based Approximate Adder.
To appear in Proceedings of the 24th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2016). Washington DC, U.S.A., May 1-3, 2016. ©1
641 R. Rosales, C. Herglotz, M. Glaß, A. Kaup and J. Teich.
Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode Decision Process Using Actor-based Modeling.
In Proceedings of the International Conference on Architecture of Computing Systems (ARCS), pp 263-276, Nürnberg, Germany, April 4-7, 2016. ©1
[doi>10.1007/978-3-319-30695-7_20]
640 J. Heisswolf, S. Friederich, L. Masing, A. Weichslgartner, A. Zaib, C. Stein, M. Duden, J. Teich, A. Herkersdorf and J. Becker.
A Novel NoC-Architecture for Fault Tolerance and Power Saving.
In Proceedings of the third International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS), pp. 8, Nuremberg, Germany, April 4-5, 2016. ©1
639 E. Borgonovo, H. Aliee, M. Glaß and J. Teich.
A New Time-Independent Reliability Importance Measure.
In European Journal of Operational Research (EJOR), 2016. ©1
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638 L. Fanucci and J. Teich.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016.
Dresden, Germany, March 14-18, 2016. ACM. ©1
637 S. Roloff, F. Hannig and J. Teich.
InvadeSIM: A Simulator for Heterogeneous Multi-Processor Systems-on-Chip.
Presentation at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March 14-18, 2016. ©1
636 B. Wang, Y. Xu, R. Hasholzner, C. Drewes, R. Rosales, S. Graf, J. Falk, M. Glaß and J. Teich.
Exploration of Power Domain Partitioning for Application-Specific SoCs in System-Level Design.
In Proceedings of the 19. GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2016), pp. 102-113, Freiburg, Germany, March 1-2, 2016. ©1
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635 Y. Xu and J. Teich.
Hierarchical Statistical Leakage Analysis and its Application.
J. ACM Transactions on Design Automation of Electronic Systems (TODAES), 2016. Accepted. ©1
634 A. Weichslgartner and J. Teich.
Position Paper: Towards Redundant Communication through Hybrid Application Mapping.
In Proceedings of the third International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS), pp. 4, Nuremberg, Germany, April 4-5, 2016. ©1
633 A. Tanase, M. Witterauf, E. Sousa, V. Lari, F. Hannig and J. Teich.
LoopInvader: A Compiler for Tightly Coupled Processor Arrays.
Presentation at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March 14-18, 2016. ©1
632 C. Schmitt, S. Kuckuk, F. Hannig, J. Teich, H. Köstler, U. Rüde and C. Lengauer.
Systems of Partial Differential Equations in ExaSlang.
To appear in Software for Exascale Computing - SPPEXA 2013-2015, Volume 113 of Lecture Notes in Computational Science and Engineering, ISBN 978-3-319-40526-1, Springer, 2016. ©1
[doi>10.1007/978-3-319-40528-5]
631 R. Membarth, O. Reiche, F. Hannig, J. Teich, M. Körner and W. Eckert.
HIPAcc: A Domain-Specific Language and Compiler for Image Processing.
IEEE Transactions on Parallel and Distributed Systems, 27(1), pp. 210-224, 2016. ©3
[doi>10.1109/TPDS.2015.2394802]
2015
630 V. Lari, J. Teich, A. Tanase, M. Witterauf, F. Khosravi and B. Meyer.
Techniques for On-Demand Structural Redundancy for Massively Parallel Processor Arrays.
Journal of Systems Architecture (JSA), 61(10):615–627, 2015. ©1
[doi>10.1016/j.sysarc.2015.10.004]
629 A. Becher, D. Ziener, K. Meyer-Wegener and J. Teich.
A Co-Design Approach for Accelerated SQL Query Processing via FPGA-based Data Filtering.
In Proceedings of 2015 International Conference on Field-Programmable Technology (FPT '15), Queenstown, New Zealand, December 7--9, 2015. ©3
[doi>10.1109/FPT.2015.7393148]
628 D. Ziener, F. Bauer, A. Becher, C. Dennl, K. Meyer-Wegener, U. Schürfeld, J. Teich, J. Vogt and H. Weber.
FPGA-Based Dynamically Reconfigurable SQL Query Processing.
ACM Transactions on Reconfigurable Technology and Systems (Accepted). ©1
627 E. Sousa, F. Hannig and J. Teich.
Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays.
In Proceedings of the International Embedded Systems Symposium (IESS), pp. 01-10, Foz do Iguaçu, Brazil, Nov. 03-06, 2015. ©1
626 A. Becher, J. Echavarria, D. Ziener and J. Teich.
Approximate Adder Structures on FPGAs.
Presented at the Workshop on Approximate Computing, Paderborn, Germany, October 15-16, 2015. ©1
625 O. Reiche, K. Häublein, M. Reichenbach, M. Schmid, F. Hannig, J. Teich and D. Fey.
Synthesis and Optimization of Image Processing Accelerators using Domain Knowledge.
In Journal of Systems Architecture (JSA), 61(10), pp. 646-658, 2015. ©1
[doi>10.1016/j.sysarc.2015.09.004]
624 J. Falk, T. Schwarzer, M. Glaß, J. Teich, C. Zebelein and C. Haubelt.
Quasi-Static Scheduling of Data Flow Graphs in the Presence of Limited Channel Capacities.
In Proceedings of the 13th IEEE Symposium on Embedded Systems for Real-time Multimedia (ESTIMEDIA), Amsterdam, The Netherlands, October 8-9, 2015. ©1
[doi>10.1109/ESTIMedia.2015.7351766]
623 S. Roloff, S. Wildermann, F. Hannig and J. Teich.
Invasive Computing for Predictable Stream Processing: A Simulation-based Case Study.
In Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia (ESTIMEDIA´15), IEEE, Amsterdam, The Netherlands, October 8-9, 2015. ©1
622 H. Köstler, C. Schmitt, S. Kuckuk, S. Kronawitter, F. Hannig, J. Teich, U. Rüde and C. Lengauer.
A Scala Prototype to Generate Multigrid Solver Implementations for Different Problems and Target Multi-Core Platforms.
In International Journal of Computational Science and Engineering. To appear. ©1
621 J. Paul, W. Stechele, B. Oechslein, C. Erhardt, J. Schedel, D. Lohmann, W. Schröder-Preikschat, M. Kröhnert, T. Asfour, É. Sousa, V. Lari, F. Hannig, J. Teich, A. Grudnitsky, L. Bauer and J. Henkel.
Resource Awareness on Heterogeneous MPSoCs for Image Processing.
Journal of Systems Architecture, 61(10), pp. 668-680, 2015. ©1
[doi>10.1016/j.sysarc.2015.09.002]
620 A. Tanase, M. Witterauf, J. Teich and F. Hannig.
Symbolic Loop Parallelization for Balancing I/O and Memory Accesses on Processor Arrays.
In Proceedings of the 13th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), pp. 188-197, IEEE, Austin, TX, USA, September 21-23, 2015. ©1
[doi>10.1109/MEMCOD.2015.7340486]
619 H. Aliee, E. Borgonovo, M. Glaß and J. Teich.
Importance Measures in Time-dependent Reliability Analysis and System Design.
In Proceedings of the Annual European Safety and Reliability Conference (ESREL '15), Zurich, Switzerland, September 7-10, 2015. ©1
618 J. Falk, T. Schwarzer, L. Zhang, M. Glaß and J. Teich.
Automatic Communication-driven Virtual Prototyping and Design for Networked Embedded Systems.
Microprocessors and Microsystems 39(8), pp. 1012–1028 (2015), Elsevier, Available online, Sep. 2 2015. ©1
[doi>10.1016/j.micpro.2015.08.008]
617 A. Tanase, M. Witterauf, J. Teich, F. Hannig and V. Lari.
On-Demand Fault-Tolerant Loop Processing on Massively Parallel Processor Arrays.
In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 194-201, Toronto, Canada, July 27-29, 2015. ©1
[doi>10.1109/ASAP.2015.7245734]
616 M. Schmid, O. Reiche, F. Hannig and J. Teich.
Loop Coarsening in C-based High-Level Synthesis.
In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 166-173, Toronto, Canada, Jul. 27-29, 2015. ©1
[doi>10.1109/ASAP.2015.7245730]
615 M. Witterauf, A. Tanase, F. Hannig and J. Teich.
Adaptive Fault Tolerance in Tightly Coupled Processor Arrays with Invasive Computing.
In Proceedings of the 11th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), pp. 205-208, Fiuggi, Italy, July 12-18, 2015. ©1
614 J. Seyler, N. Navet, L. Fejoz and J. Teich.
Insights on the Configuration and Performances of SOME/IP Service Discovery.
SAE International Journal of Passenger Cars - Electronic and Electrical Systems, 8(1), pp. 124-129, 2015. ©1
613 J. Heisswolf, A. Weichslgartner, A. Zaib, S. Friederich, L. Masing, C. Stein, M. Duden, R. Klöpfer, J. Teich, T. Wild, A. Herkersdorf and J. Becker.
Fault-tolerant Communication in Invasive Networks on Chip.
In Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 1-8, Montreal, Canada, June 15-18, 2015. ©1
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612 R. Glein, F. Rittner, A. Becher, D. Ziener, J. Frickel, J. Teich and A. Heuberger.
Reliability of Space-Grade vs. COTS SRAM-Based FPGA in N-Modular Redundancy.
In Proceedings of 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Montreal, QC, Canada, June 15--18, 2015. ©1
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611 M. Glaß, H. Aliee, L. Cheng, M. Ebrahimi, F. Khosravi, V. Kleeberger, A. Listl, D. Müller-Gritschneider, F. Oboril, U. Schlichtmann, M. Tahoori, J. Teich, N. Wehn and C. Weis.
Application-aware cross-layer reliability analysis and optimization.
it - Information Technology, Volume 57(3): 159-169, 2015. ©1
[doi>10.1515/itit-2014-1080]
610 S. Graf, S. Reinhard, M. Glaß, J. Teich and D. Platte.
Robust Design of E/E Architecture Component Platforms.
In Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC 2015), 6p., San Francisco, CA, USA, June 7-11, 2015. ©1
[doi>10.1145/2744769.2747941]
609 S. Roloff, D. Schafhauser, F. Hannig and J. Teich.
Execution-driven Parallel Simulation of PGAS Applications on Heterogeneous Tiled Architectures.
In Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 44:1-44:6, ACM, San Francisco, CA, USA, June 7-11, 2015. ©3
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608 J. Teich.
Adaptive Isolation for Predictable MPSoC Stream Processing.
Proc. of the 18th Int. Workshop on Software and Compilers for Embedded Systems (SCOPES 2015), Schloss Rheinfels, St. Goar, Germany, p. 2, June 1-3, 2015.. ©1
[doi>10.1145/2764967.2771821]
607 E. Sousa, F. Hannig, J. Teich, Q. Chen and U. Schlichtmann.
Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays.
In Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES), pp. 121-124, ACM, St. Goar, Germany, June 1-3, 2015. ©1
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606 T. Schwarzer, J. Falk, M. Glaß, J. Teich, C. Zebelein and C. Haubelt.
Throughput-optimizing Compilation of Dataflow Applications for Multi-Cores using Quasi-Static Scheduling.
In Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES), pp. 68-75 ,St. Goar, Germany, June 1-3, 2015. ©1
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605 J. Teich, S. Boppu, F. Hannig and V. Lari.
Compact Code Generation and Throughput Optimization for Coarse-Grained Reconfigurable Arrays.
In Transforming Reconfigurable Systems: A Festschrift Celebrating the 60th Birthday of Prof. Peter Cheung, Editors W. Luk, and George A. Constantinides, Chapter 10, pp.167--206, Imperial College Press, London, UK, April 2015. ©1
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604 V. Lari, A. Tanase, J. Teich, M. Witterauf, F. Khosravi, F. Hannig and B. Meyer.
A Co-Design Approach for Fault-Tolerant Loop Execution on Coarse-Grained Reconfigurable Arrays.
In Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, Montreal, pp. 1-8, Canada, June 15-18, 2015. ©1
[doi>10.1109/AHS.2015.7231157]
603 M. Witterauf, A. Tanase, J. Teich, V. Lari, A. Zwinkau and G. Snelting.
Adaptive Fault Tolerance through Invasive Computing.
In Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, Montreal, pp. 1-8, Canada, June 15-18, 2015. ©1
[doi>10.1109/AHS.2015.7231155]
602 S. Wildermann, A. Weichslgartner and J. Teich.
Design Methodology and Run-time Management for Predictable Many-Core Systems.
Proceedings of the 6th IEEE Workshop on Self-Organizing Real-Time Systems (SORT 2015), pp. 103-110, Auckland, New Zealand, April 13, 2015. ©1
[doi>10.1109/ISORCW.2015.48]
601 A. Zaib, J. Heisswolf, A. Weichslgartner, T. Wild, J. Teich, J. Becker and A. Herkersdorf.
Network Interface with Task Spawning Support for NoC-based DSM Architectures.
In Proceedings of 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS), pp. 186-198, Porto, Portugal, March 26, 2015. ©1
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600 A. Weichslgartner, J. Heisswolf, A. Zaib, T. Wild, A. Herkersdorf, J. Becker and J. Teich.
Position Paper: Towards Hardware-Assisted Decentralized Mapping of Applications for Heterogeneous NoC Architectures.
In Proceedings of the second International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS), pp. 4, Porto, Portugal, March 24, 2015. ©1
599 S. Graf, M. Glaß, J. Teich and D. Platte.
A Methodology for the Optimized Design of an E/E Architecture Component Platform.
In Proceedings of the Stuttgart International Symposium, pp. 203-215, Stuttgart, Germany, March 17-18, 2015. ©1
[doi>10.1007/978-3-658-08844-6_14]
598 O. Reiche, K. Häublein, M. Reichenbach, F. Hannig, J. Teich and D. Fey.
Automatic Optimization of Hardware Accelerators for Image Processing.
In Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS), pp. 10-15, Grenoble, France, March 13, 2015. arXiv: 1502.07448 [cs.PL]. ©1
597 F. Khosravi, M. Müller, M. Glaß and J. Teich.
Uncertainty-Aware Reliability Analysis and Optimization.
In Proceedings of Design, Automation and Test in Europe (DATE 2015), pp. 97-102, Grenoble, France, March 9-13, 2015. ©1
[doi>10.7873/DATE.2015.0319]
596 J. Seyler, T. Streichert, M. Glaß, N. Navet and J. Teich.
Formal Analysis of the Startup Delay of SOME/IP Service Discovery.
In Proceedings of Design, Automation and Test in Europe (DATE 2015), pp. 49-54, Grenoble, France, March 9-13, 2015. ©1
[doi>10.7873/DATE.2015.0469]
595 S. Graf, M. Glaß and J. Teich.
Symbolic Message Routing for Multi-Objective Optimization of Automotive E/E Architecture Component Platforms.
In Proceedings of 18. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2015), pp. 115-124, Chemnitz, Germany, March 3-4, 2015, . ©1
594 C. Schmitt, M. Schmid, F. Hannig, J. Teich, S. Kuckuk and H. Köstler.
Generation of Multigrid-based Numerical Solvers for FPGA Accelerators.
In Proceedings of the 2nd International Workshop on High-Performance Stencil Computations (HiStencils), pp. 9-15, Amsterdam, The Netherlands, January 20, 2015. ©1
593 L. Zhang, M. Glaß, N. Ballmann and J. Teich.
Bridging Algorithm and ESL Design: MATLAB/Simulink Model Transformation and Validation.
In Marie-Minerve Louërat and Torsten Maehne (Eds.): Languages, Design Methods, and Tools for Electronic System Design, pp. 189-206, ISBN 978-3-319-06316-4, Springer, 2015. ©1
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2014
592 V. Narayanan and J. Teich.
Introduction to the Special Issue on Domain-Specific Multicore Computing.
J. ACM Transactions on Embedded Computing Systems (TECS), vol. 13, no. 4s, pages 129:1-129:2. ©1
[doi>10.1145/2588609]
591 S. Apel, M. Bolten, A. Größlinger, F. Hannig, H. Köstler, C. Lengauer, U. Rüde and J. Teich.
ExaStencils: Advanced Stencil-Code Engineering.
inSiDE, 12(2):60-63, 2014. ©1
590 C. Schmitt, S. Kuckuk, F. Hannig, H. Köstler and J. Teich.
ExaSlang: A Domain-Specific Language for Highly Scalable Multigrid Solvers.
In Proceedings of the 4th International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC), pp. 42-51, New Orleans, LA, USA, November 17, 2014. ©1
[doi>10.1109/WOLFHPC.2014.11]
589 D. Gangadharan, E. Sousa, V. Lari, F. Hannig and J. Teich.
Application-driven Reconfiguration of Shared Resources for Timing Predictability of MPSoC Platforms.
In Proceedings of Asilomar Conference on Signals, Systems, and Computers (ASILOMAR), pp. 398-403, Pacific Grove, CA, USA, November 2-5, 2014. ©1
[doi>10.1109/ACSSC.2014.7094471]
588 R. Membarth, O. Reiche, C. Schmitt, F. Hannig, J. Teich, M. Stürmer and H. Köstler.
Towards a Performance-portable Description of Geometric Multigrid Algorithms using a Domain-specific Language.
In Journal of Parallel and Distributed Computing (JPDC). 74(12), pp. 3191-3201, 2014. ©1
[doi>10.1016/j.jpdc.2014.08.008]
587 A. Tanase, M. Witterauf, J. Teich and F. Hannig.
Symbolic Inner Loop Parallelisation for Massively Parallel Processor Arrays.
In Proceedings of the 12th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), pp. 219-228, Lausanne, Switzerland, October 19-21, 2014. ©3
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586 H. Aliee, M. Glaß, F. Khosravi and J. Teich.
An Efficient Technique for Computing Importance Measures in Automatic Design of Dependable Embedded Systems.
In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2014), pp. 34:1-34:10, New Delhi, India, October 12-17, 2014. ©1
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585 O. Reiche, M. Schmid, F. Hannig, R. Membarth and J. Teich.
Code Generation from a Domain-specific Language for C-based HLS of Hardware Accelerators.
In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New Dehli, India, October 12-17, 2014. ©1
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584 A. Weichslgartner, D. Gangadharan, S. Wildermann, M. Glaß and J. Teich.
DAARM: Design-Time Application Analysis and Run-Time Mapping for Predictable Execution in Many-Core Systems.
In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2014), 10 p., New Delhi, India, October 12-17, 2014. ©1
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583 S. Graf, F. Reimann, M. Glaß and J. Teich.
Towards Scalable Symbolic Routing for Multi-Objective Networked Embedded System Design and Optimization.
In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2014), pp. 2:1--2:10, New Delhi, India, October 12-17, 2014. ©1
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582 J. Paul, W. Stechele, E. Sousa, V. Lari, F. Hannig, J. Teich, M. Kröhnert and T. Asfour.
Self-Adaptive Harris Corner Detection on Heterogeneous Many-core Processor.
In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, October 8-10, 2014. ©1
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581 Y. Xu, B. Wang and J. Teich.
Parametric Yield Optimization Using Leakage-Yield-Driven Floorplanning.
In Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 1-6, Palma de Mallorca, Spain, September 29-October 1, 2014. ©1
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580 B. Wang, Y. Xu, R. Rosales, R. Hasholzner, M. Glaß and J. Teich.
End-to-End Power Estimation for Heterogeneous Cellular LTE SoCs in Early Design Phases.
In Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 1-8, Palma de Mallorca, Spain, September 29-October 1, 2014. ©1
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579 S. Wildermann and J. Teich.
Self-Integration for Virtualization of Embedded Many-Core Systems.
In Proceedings of the Workshop on Self-Improving System Integration (SISSY 2014), 8 p., London, UK, September 8, 2014. ©1
578 E. Glocker, S. Boppu, Q. Chen, U. Schlichtmann, J. Teich and D. Schmitt-Landsiedel.
Temperature modeling and emulation of an ASIC temperature monitor system for Tightly-Coupled Processor Arrays (TCPAs) on FPGA.
In Journal of Advances in Radio Science,Vol. 12, pages 103–109, 2014. ©1
577 A. Becher, F. Bauer, D. Ziener and J. Teich.
Energy-Aware SQL Query Acceleration through FPGA-Based Dynamic Partial Reconfiguration.
Proceedings of the Conference on Field-Programmable Logic and Applications (FPL 2014), Munich, Germany, pp. 662 - 669, Sep 2-4, 2014. ©3
[doi>10.1109/FPL.2014.6927502]
576 M. Schmid, N. Apelt, F. Hannig and J. Teich.
An Image Processing Library for C-based High-Level Synthesis.
In Proceedings of the 24th International Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, September 2-4, 2014. ©3
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575 A. Grebhahn, S. Kuckuk, C. Schmitt, H. Köstler, N. Siegmund, S. Apel, F. Hannig and J. Teich.
Experiments on Optimizing the Performance of Stencil Codes with SPL Conqueror.
In Parallel Processing Letters, 24(3):Article 1441001, 19 pages, September 2014. ©1
[doi>10.1142/S0129626414410011]
574 M. Schmid, O. Reiche, C. Schmitt, F. Hannig and J. Teich.
Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs.
In Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP), pp. 21-26, Munich, Germany, September 1, 2014. arXiv: 1408.4721 [cs.CV]. ©1
573 C. Lengauer, S. Apel, M. Bolten, A. Größlinger, F. Hannig, H. Köstler, U. Rüde, J. Teich, A. Grebhahn, S. Kronawitter, S. Kuckuk, H. Rittich and C. Schmitt.
ExaStencils: Advanced Stencil-Code Engineering.
In Proceedings of Euro-Par 2014: Parallel Processing Workshops, Porto, Portugal, August 25-29, 2014, volume 8806 of Lecture Notes in Computer Science (LNCS), pp. 553-564, Springer, 2014. ©1
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572 S. Graf, M. Glaß, J. Teich and C. Lauer.
Design Space Exploration for Automotive E/E Architecture Component Platforms.
In Proceedings of the Euromicro Conference on Digital Systems Design (DSD 2014), pp. 651-654, Verona, Italy, Aug 27-29, 2014. ©1
[doi>10.1109/DSD.2014.43]
571 J. Teich, A. Tanase and F. Hannig.
Symbolic Mapping of Loop Programs onto Processor Arrays.
Journal of Signal Processing Systems, 77(1-2):31-59, 2014. ©1
[doi>10.1007/s11265-014-0905-0]
570 C. Schmitt, S. Kuckuk, H. Köstler, F. Hannig and J. Teich.
An Evaluation of Domain-Specific Language Technologies for Code Generation.
In Proceedings of the 14th International Conference on Computational Science and its Applications (ICCSA), pp. 18-26, Guimaraes, Portugal, June 30-July 3, 2014. ©1
[doi>10.1109/ICCSA.2014.16]
569 L. Zhang, J. Falk, T. Schwarzer, M. Glaß and J. Teich.
Communication-driven Automatic Virtual Prototyping for Networked Embedded Systems.
In Proceedings of the Euromicro Conference on Digital Systems Design (DSD 2014), pp. 435-442, Verona, Italy, Aug 27-29, 2014. ©1
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568 J. Seyler, S. Rahimov, T. Streichert, M. Glaß and J. Teich.
DPSK Modulated Wakeup Mechanism for Point-to-Point Networks with Partial Network Support.
In Proceedings of the 9th IEEE International Symposium on Industrial Embedded Systems (SIES), pp. 238 - 243, Pisa, Italy, June 19-21, 2014. ©1
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567 E. Sousa, D. Gangadharan, F. Hannig and J. Teich.
Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures.
In Proceedings of the EUROMICRO Digital System Design Conference (DSD), pp. 74-81, Verona, Italy, Aug. 27-29, 2014. ©1
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566 R. Rosales, M. Glaß, J. Teich, B. Wang, Y. Xu and R. Hasholzner.
MAESTRO - Holistic Actor-oriented Modeling of Non-Functional Properties and Firmware Behavior for MPSoCs.
In ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 19 Issue 3, Article No. 23, ACM New York, NY, USA, June 2014. ©1
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565 F. Khosravi, F. Reimann, M. Glaß and J. Teich.
Multi-Objective Local-Search Optimization using Reliability Importance Measuring.
In Proceedings of the 51st Design Automation Conference (DAC 2014), pp. 1-6, San Francisco, CA, USA, June 1-5, 2014. ©1
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564 J. Heisswolf, A. Zaib, A. Zwinkau, S. Kobbe, A. Weichslgartner, J. Teich, J. Henkel, G. Snelting, A. Herkersdorf and J. Becker.
CAP: Communication Aware Programming.
In Proceedings of the 51st Design Automation Conference (DAC 2014), pp. 105:1--105:6, San Francisco, CA, USA, June 1-5, 2014. ©1
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563 S. Boppu, F. Hannig and J. Teich.
Compact Code Generation for Tightly-Coupled Processor Arrays.
Journal of Signal Processing Systems, 77(1-2):5-29, 2014. ©1
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562 F. Hannig and J. Teich.
Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014).
62 pages, Paderborn, Germany, 2014. arXiv: 1405.2281 [cs.DC]. ©1
561 V. Lari, A. Tanase, F. Hannig and J. Teich.
Massively Parallel Processor Architectures for Resource-aware Computing.
In Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014), pp. 1-7, Paderborn, Germany, May 29-30, 2014. arXiv: 1405.2907 [cs.AR]. ©1
560 B. Schmidt, D. Ziener and J. Teich.
Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning.
In Proceedings of the Reconfigurable Architectures Workshop (RAW), pp. 299-304, Phoenix, USA, May 2014. ©3
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559 M. Schmid, A. Tanase, V. Badhouria, F. Hannig, J. Teich and D. Ghoshal.
Domain-Specific Augmentations for High-Level Synthesis.
In Proceedings of the 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 173-177, IEEE, Zurich, Switzerland, Jun. 18-20, 2014. ©1
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558 D. Gangadharan, S. Chakraborty and J. Teich.
Quality-aware Video Decoding on Thermally-constrained MPSoC Platforms.
In Proceedings of the 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 256-263, IEEE, Zurich, Switzerland, Jun. 18-20, 2014. ©1
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557 M. Schmid, F. Hannig, A. Tanase and J. Teich.
High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model.
In Parallel Computing: Accelerating Computational Science and Engineering (CSE), volume 25 of Advances in Parallel Computing, pp. 497-506, IOS Press, 2014. ©1
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556 F. Reimann, M. Glaß, J. Teich, A. Cook, L. Gómez, D. Ull, H. Wunderlich, U. Abelein and P. Engelke.
Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures.
In Proceedings of the 51st Design Automation Conference (DAC 2014), 8 p., San Francisco, CA, USA, June 1-5, 2014. ©1
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555 D. Gangadharan, A. Tanase, F. Hannig and J. Teich.
Timing Analysis of a Heterogeneous Architecture with Massively Parallel Processor Arrays.
DATE Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES), Dresden, Germany, March 28, 2014. ©1
554 R. Membarth, O. Reiche, F. Hannig and J. Teich.
Code Generation for Embedded Heterogeneous Architectures on Android.
In Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pp. 86:1-86:6, Dresden, Germany, March 24-28, 2014. ©3
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553 J. Seyler, T. Streichert, J. Warkentin, M. Spägele, M. Glaß and J. Teich.
A Self-Propagating Wakeup Mechanism for Point-to-Point Networks with Partial Network Support.
In Proceedings of Design, Automation and Test in Europe (DATE 2014), 6 p., Dresden, Germany, March 24-28, 2014. ©1
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552 U. Abelein, A. Cook, P. Engelke, M. Glaß, F. Reimann, L. Rodríguez Gómez, T. Russ, J. Teich, D. Ull and H. Wunderlich.
Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures.
In Proceedings of Design, Automation and Test in Europe (DATE 2014), 6 p., Dresden, Germany, March 24-28, 2014. ©1
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551 R. Glein, B. Schmidt, F. Rittner, J. Teich and D. Ziener.
A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor.
In Proceedings of Field-Programmable Custom Computing Machines (FCCM 2014), pp. 251-258, Boston, Massachusetts, USA, May 11-13, 2014. ©3
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550 S. Graf, M. Glaß, J. Teich and C. Lauer.
Multi-Variant-based Design Space Exploration for Automotive Embedded Systems.
In Proceedings of Design, Automation and Test in Europe (DATE 2014), 6 p., Dresden, Germany, March 24-28, 2014. ©1
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549 S. Wildermann, M. Glaß and J. Teich.
Multi-Objective Distributed Run-time Resource Management for Many-Cores.
In Proceedings of Design, Automation and Test in Europe (DATE 2014), 6 p., Dresden, Germany, March 24-28, 2014. ©1
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548 C. Zebelein, C. Haubelt, J. Falk, T. Schwarzer and J. Teich.
Model-Based Actor Multiplexing with Application to Complex Communication Protocols.
In Proceedings of Design, Automation and Test in Europe (DATE 2014), 4p., Dresden, Germany, March 24-28, 2014. ©1
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547 R. Rosales, M. Glaß and J. Teich.
Mahler: Sketch-based Model-driven Virtual Prototyping.
In Proceedings of the International Conference on Architecture of Computing Systems (ARCS), pp. 85-97, Lübeck, Germany, February 25-28, 2014. ©1
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546 J. Heisswolf, A. Zaib, A. Weichslgartner, M. Karle, M. Singh, T. Wild, J. Teich, A. Herkersdorf and J. Becker.
The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure.
In Proceedings of the first International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS), pp. 1-8, Lübeck, Germany, Feb. 25, 2014. ©1
545 S. Roloff, F. Hannig and J. Teich.
Towards Actor-oriented Programming on PGAS-based Multicore Architectures.
In Proceedings of the first International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS), pp. 1-2, Lübeck, Germany, February 25, 2014. ©1
544 A. Herkersdorf, H. Aliee, M. Engel, M. Glaß, C. Gimmler-Dimont, J. Henkel, V. Kleeberger, M. Kochte, J. Kühn, D. Mueller-Gritschneider, S. Nassif, H. Rauchfuß, W. Rosenstiel, U. Schlichtmann, M. Shafique, M. Tahoori, J. Teich, N. Wehn, C. Weis and H. Wunderlich.
Resilience Articulation Point (RAP): Cross-layer Dependability Modeling for Nanometer System-on-Chip Resilience.
In Microelectronics Reliability, Volume 54(6–7): 1066-1074, June-July, Elsevier, ISSN 0026-2714, 2014. ©1
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543 H. Aliee, M. Glaß, R. Wanka and J. Teich.
Automatic Graph-based Success Tree Construction and Analysis.
In Proceedings of the 60th Annual Reliability and Maintainability Symposium (RAMS 2014), pp. 563-569, Colorado Springs, U.S.A., January 27-30, 2014. (Best Paper Award). ©1
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2013
542 J. Falk, C. Haubelt, C. Zebelein and J. Teich.
Integrated Modeling Using Finite State Machines and Dataflow Graphs.
In Shuvra S. Bhattacharyya and Ed F. Deprettere and Rainer Leupers and Jarmo Takala, editors, Handbook of Signal Processing Systems, pp. 975-2013, Springer, 2013. ©1
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541 M. Schmid, M. Blocherer, F. Hannig and J. Teich.
Real-Time Range Image Preprocessing on FPGAs.
In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), pp.1-8, Cancun, Mexico, Dec. 09 - 11, 2013. ©1
540 M. Blocherer, S. Boppu, V. Lari, F. Hannig and J. Teich.
Transactor-based debugging of massively parallel processor array architectures.
1st International Workshop on Multicore Application Debugging (MAD), Garching, Germany, November 14-15, 2013. ©1
539 S. Glock, R. Rosales, F. Reutelhuber, M. Glaß, J. Teich, G. Fischer, R. Weigel and T. Ussmueller.
Scenario-Based Energy Estimation of Heterogeneous Integrated Systems at System Level.
In Proceedings of the 43rd European Microwave Conference (EuMC 2013), pp. 342-345, Nuremberg, Germany, Oct. 6-11, 2013. ©1
538 J. Henkel, V. Narayanan, S. Parameswaran and J. Teich.
Run-Time Adaptation for Highly-Complex Multi-Core Systems.
In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2013), 8 p., Montreal, Canada, Sep. 29 - Oct. 4, 2013. ©3
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537 S. Graf, M. Glaß, D. Wintermann, J. Teich and C. Lauer.
IVaM: Implicit Variant Modeling and Management for Automotive Embedded Systems.
In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2013), 10 p., Montreal, Canada, Sep. 29 - Oct. 4, 2013. ©1
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536 L. Zhang, M. Glaß, J. Teich and N. Ballmann.
Bridging Algorithm and ESL Design: Matlab/Simulink Model Transformation and Validation.
In Proceedings of Forum on specification & Design Languages (FDL 2013), 8 p., Paris, France, Sep. 24-26, 2013. ©1
535 C. Zebelein, C. Haubelt, J. Falk, T. Schwarzer and J. Teich.
Representing Mapping and Scheduling Decisions within Dataflow Graphs.
In Proceedings of Forum on Specification & Design Languages (FDL 2013), 8 p., Paris, France, Sep. 24-26, 2013. ©1
534 F. Reimann, S. Graf, F. Streit, M. Glaß and J. Teich.
Timing Analysis of Ethernet AVB-based Automotive E/E Architectures.
Proceedings of IEEE International Conference on Emerging Technology & Factory Automation (ETFA), 8 p., Cagliari, Italy, Sep. 10-13, 2013. ©1
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533 S. Wildermann and J. Teich.
Decomposing Run-time Resource Management in Heterogeneous Reconfigurable Systems.
Proceedings of Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 4 p., Porto, Portugal, Sep. 5, 2013. ©1
532 A. Zaib, J. Heisswolf, A. Weichslgartner, T. Wild, J. Teich, J. Becker and A. Herkersdorf.
AUTO-GS: Self-optimization of NoC Traffic Through Hardware Managed Virtual Connections.
In Proceedings of the 16th Euromicro Conference on Digital System Design, pp. 761–768, Santander, Spain, Sep. 4-6, 2013. ©1
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531 E. Sousa, A. Tanase, F. Hannig and J. Teich.
A Prototype of an Adaptive Computer Vision Algorithm on MPSoC Architecture.
Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), pp. 361-362, Cagliari, Italy, Oct. 8-10, 2013. ©1
530 J. Heisswolf, A. Zaib, A. Weichslgartner, T. Wild, J. Teich, A. Herkersdorf and J. Becker.
Virtual Networks - Distributed Communication Resource Management.
In ACM Transactions on Reconfigurable Technology and Systems (TRETS), 6(2):8:1–8:14, Aug., 2013. ©1
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529 E. Sousa, A. Tanase, F. Hannig and J. Teich.
Accuracy and Performance Analysis of Harris Corner Computation on Tightly-Coupled Processor Arrays.
Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), pp. 88-95, Cagliari, Italy, Oct. 8-10, 2013. ©1
528 M. Glaß, S. Graf, F. Reimann and J. Teich.
Design and Evaluation of Future Ethernet AVB-based ECU Networks.
In Alberto Sangiovanni-Vincentelli, Haibo Zeng, Marco Di Natale and Peter Marwedel (Eds.): Embedded Systems Development: From Functional Models to Implementations, pp. 205-220, ISBN 978-1-4614-3878-6, Springer, 2013. ©1
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527 M. Lukasiewycz, M. Glaß, J. Teich and S. Chakraborty.
Exploration of Distributed Automotive Systems using Compositional Timing Analysis.
In Alberto Sangiovanni-Vincentelli, Haibo Zeng, Marco Di Natale and Peter Marwedel (Eds.): Embedded Systems Development: From Functional Models to Implementations, pp. 189-204, ISBN 978-1-4614-3878-6, Springer, 2013. ©1
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526 S. Roloff, A. Weichslgartner, J. Heißwolf, F. Hannig and J. Teich.
NoC Simulation in Heterogeneous Architectures for PGAS Programming Model.
In Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems (M-SCOPES), pp. 77-85, St. Goar, Germany, Jun. 19-21, 2013. ©1
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525 A. Tanase, V. Lari, F. Hannig and J. Teich.
Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing.
Proceedings of the International Conference on Parallel Computing (ParCo), pp. 53-62 Munich, Germany, Sep. 10-13, 2013. ©1
524 J. Teich, A. Tanase and F. Hannig.
Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays.
Proceedings of the 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 9 p., IEEE, Washington, D.C., USA, Jun. 5-7, 2013 [Best Paper Award]. ©3
523 S. Boppu, F. Hannig and J. Teich.
Loop Program Mapping and Compact Code Generation for Programmable Hardware Accelerators.
Proceedings of the 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 10–17. IEEE, Washington, D.C., USA, Jun. 5-7, 2013. ©3
522 V. Lari, S. Boppu, F. Hannig, J. Teich and T. Scott.
Hybrid Prototyping of Tightly-Coupled Processor Arrays for MPSoC Designs.
Designer Track Poster Presentation at the 50th Design Automation Conference (DAC 2013), Austin, TX, USA, Jun. 2-6, 2013. ©1
521 Y. Xu, B. Wang, R. Hasholzner, R. Rosales and J. Teich.
On Robust Task-Accurate Performance Estimation.
Proceedings of the 50th Design Automation Conference (DAC 2013), pp. 171-177, Austin, TX, USA, Jun. 2-6, 2013 [HiPEAC Award]. ©1
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520 J. Teich, W. Schröder-Preikschat and A. Herkersdorf.
Invasive Computing - Common Terms and Granularity of Invasion.
J. CoRR, vol. abs/1304.6067, 2013. http://arxiv.org/abs/1304.6067. ©1
519 J. Heisswolf, A. Weichslgartner, A. Zaib, R. König, T. Wild, J. Teich, A. Herkersdorf and J. Becker.
Hardware Supported Adaptive Data Collection for Networks on Chip.
Proceedings of 20th Reconfigurable Architectures Workshop (RAW 2013), Boston, USA, pp. 153–162, May 2013. ©1
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518 F. Hannig, M. Schmid, V. Lari, S. Boppu and J. Teich.
System Integration of Tightly-Coupled Processor Arrays using Reconfigurable Buffer Structures.
Proceedings of the ACM International Conference on Computing Frontiers (CF), Ischia, Italy, May 14-16, 2013. ©1
517 S. Boppu, V. Lari, F. Hannig and J. Teich.
Transactor-based Prototyping of Heterogeneous Multiprocessor System-On-Chip Architectures.
Proceedings of the Synopsys Users Group Conference (SNUG), Munich, Germany, May 14, 2013. ©1
516 C. Dennl, D. Ziener and J. Teich.
Acceleration of SQL Restrictions and Aggregations through FPGA-based Dynamic Partial Reconfiguration.
Proceedings of the IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM), Seattle, USA, Apr. 28-30, 2013. ©3
515 T. Ziermann, S. Wildermann and J. Teich.
Self-organizing Core Allocation.
Proceedings of the 25th Workshop on Parallel Systems and Algorithms (PARS), Erlangen, Germany, April 11-12, 2013, volume 30 of Mitteilungen - Gesellschaft für Informatik e. V., Parallel-Algorithmen und Rechnerstrukturen, Gesellschaft für Informatik e. V., 2013. ©1
514 E. Sousa, A. Tanase, V. Lari, F. Hannig, J. Teich, J. Paul, W. Stechele, M. Kröhnert and T. Asfour.
Acceleration of Optical Flow Computations on Tightly-Coupled Processor Arrays.
Proceedings of the 25th Workshop on Parallel Systems and Algorithms (PARS), pp. 80-89, Erlangen, Germany, April 11-12, 2013, volume 30 of Mitteilungen - Gesellschaft für Informatik e. V., Parallel-Algorithmen und Rechnerstrukturen, Gesellschaft für Informatik e. V., 2013. ©1
513 J. Falk, C. Zebelein, C. Haubelt and J. Teich.
A Rule-Based Quasi-Static Scheduling Approach for Static Islands in Dynamic Dataflow Graphs.
ACM Transactions on Embedded Computing Systems (TECS), 12(3):74:1–74:31, Apr. 2013 . ©1
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512 A. Herkersdorf, M. Engel, M. Glaß, J. Henkel, V. Kleeberger, M. Kochte, J. Kühn, S. Nassif, H. Rauchfuss, W. Rosenstiel, U. Schlichtmann, M. Shafique, M. Tahoori, J. Teich, N. Wehn, C. Weis and H. Wunderlich.
Cross-Layer Dependability Modeling and Abstraction in System on Chip.
In Proceedings of the 9th Workshop on Silicon Errors in Logic - System Effects (SELSE), Stanford University, U.S.A., Mar. 26-27, 2013. ©1
511 S. Wildermann, T. Ziermann and J. Teich.
Game-Theoretic Analysis of Decentralized Core Allocation Schemes on Many-core Systems.
In Proceedings of Design, Automation and Test in Europe (DATE 2013), pp.1498-1503, Grenoble, France, Mar. 18-22, 2013. ©1
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510 H. Aliee, M. Glaß, F. Reimann and J. Teich.
Automatic Success Tree-Based Reliability Analysis for the Consideration of Transient and Permanent Faults.
In Proceedings of Design, Automation and Test in Europe (DATE 2013), pp. 1621-1626, Grenoble, France, Mar. 18-22, 2013. ©3
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509 V. Lari, S. Boppu, F. Hannig, S. Muddasani, B. Kuzmin and J. Teich.
Resource-Aware Video Processing on Tightly-Coupled Processor Arrays.
Hardware and Software Demo, University Booth at Design, Automation and Test in Europe (DATE), Grenoble, France, Mar. 18-22, 2013. ©1
508 S. Graf, M. Glaß and J. Teich.
Investigating the Impact of Energy-Efficient Ethernet on Automotive Applications via High-level Modeling.
In Proceedings of Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), pp. 117-128, Rostock, Germany, Mar. 12-14, 2013. ©1
507 C. Zebelein, C. Haubelt, J. Falk and J. Teich.
Model-Based Representation of Schedules for Dataflow Graphs.
Proceedings of Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2013), pp. 105-116, Rostock, Germany, Mar. 12-14, 2013. ©1
506 F. Reimann, M. Glaß and J. Teich.
Migration Strategies for Ethernet-based E/E Architectures.
In Proceedings of the Embedded World Conference, 8 p., Nuremberg, Germany, Feb. 26-28, 2013. ©1
505 B. Wang, Y. Xu, R. Rosales, R. Hasholzner and J. Teich.
ESL Power Estimation: A Design Case Study for Early Design Phases.
Proceedings of the Embedded World Conference, WEKA Fachzeitschriften Verlag, 2013, pp. 1-11 Nuremberg, Germany, Feb. 26-28, 2013 . ©1
504 F. Reimann, M. Glaß, J. Teich and U. Abelein.
Szenarienbasierte Integration von Diagnosefunktionalität in E/E Architekturen.
In Proceedings of Automotive meets Electronics (AmE), GMM-Fachbericht 75, pp. 15-20, Dortmund, Germany, Feb. 19-20, 2013. ©1
503 R. Kiesel, S. Freisler, O. Löhlein, C. Haubelt, M. Streubühr and J. Teich.
Multi-Platform Performance Evaluation of Pedestrian Detection at the Electronic System Level.
In Proceedings of Automotive meets Electronics (AmE), GMM-Fachbericht 75, pp. 98-103, Dortmund, Germany, Feb. 19-20, 2013. ©1
502 Y. Xu, B. Wang, R. Rosales, R. Hasholzner and J. Teich.
On Confident Task-Accurate Performance Estimation.
In Proceedings of the International Conference on Architecture of Computing Systems (ARCS), pp. 25-37, Prague, Czech Republic, Feb. 2013. ©1
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501 T. Ziermann, Z. Salcic and J. Teich.
HW/SW Tradeoffs for Dynamic Message Scheduling in Controller Area Network (CAN).
In Proceedings of the International Conference on Architecture of Computing Systems (ARCS), pp. 159-170, Prague, Czech Republic, Feb. 2013. ©1
2012
500 V. Lari, S. Muddasani, S. Boppu, F. Hannig, M. Schmid and J. Teich.
Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays.
ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 18, No. 1, Article 2, Pages 2:1–2:25, December 2012. ©1
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499 S. Wildermann, F. Reimann, D. Ziener and J. Teich.
Symbolic System-level Design Methodology for Multi-Mode Reconfigurable Systems.
Journal on Design Automation for Embedded Systems, Springer, 2012. ©1
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498 R. Membarth, F. Hannig, J. Teich and H. Köstler.
Towards Domain-specific Computing for Stencil Codes in HPC.
In Proceedings of the 2nd International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC), pp. 1133-1138, Salt Lake City, UT, USA, November 16, 2012. ©3
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497 J. Gladigau, C. Haubelt and J. Teich.
Model-Based Virtual Prototype Acceleration.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 31(10): 1572-1585, 2012 . ©1
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496 S. Muddasani, S. Boppu, F. Hannig, B. Kuzmin, V. Lari and J. Teich.
A Prototype of an Invasive Tightly-Coupled Processor Array.
In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), pp. 393-394, Karlsruhe, Germany, October 23-25, 2012. ©1
495 T. Ziermann, Z. Salcic and J. Teich.
Improving Performance of Controller Area Network (CAN) by Adaptive Message Scheduling.
In Higuera-Toledano, M. Teresa; Brinkschulte, Uwe; Rettberg, Achim (Eds.): Self-Organization in Embedded Real-Time Systems, pp. 95-120, Springer Verlag Berlin Heidelberg, 2012. ©1
494 T. Ziermann, A. Butiu, J. Teich and D. Ziener.
FPGA-based Testbed for Timing Behavior Evaluation of the Controller Area Network (CAN) .
In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, Dec.5-7, 2012. ©1
493 M. Glaß, H. Yu, F. Reimann and J. Teich.
Cross-Level Compositional Reliability Analysis for Embedded Systems.
In Proceedings of the 31th International Conference on Computer Safety, Reliability and Security (SAFECOMP 2012), pp. 111-124, Magdeburg, Germany, September 25-28, 2012. ©1
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492 J. Teich, A. Weichslgartner, B. Oechslein and W. Schröder-Preikschat.
Invasive Computing - Concepts and Overheads.
In Proceedings of the Forum on Specification & Design Languages (FDL), pp. 193-200, Vienna, Austria, September 18-20, 2012. ©1
491 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Mastering Software Variant Explosion for GPU Accelerators.
In Proceedings of the 10th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar), pp. 123-132, Rhodes Island, Greece, August 27, 2012. ©1
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490 S. Wildermann, F. Reimann, D. Ziener and J. Teich.
System Level Synthesis Flow for Self-adaptive Multi-mode Reconfigurable Systems.
In Proceedings of Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), pp. 4-7, Oslo, Norway, September 01, 2012. ©1
489 R. Rosales, T. Klie, S. Glock, Y. Xu, B. Wang, R. Hasholzner, J. Teich and R. Weigel.
Eine Aktor-Orientierte Methodik zur Power-Modellierung auf Systemebene.
Design&Elektronik Entwicklerforum "Embedded-System-Entwicklung". WEKA Fachzeitschriften Verlag, 2012, pp. 1-9. Munich, Germany, July 2012. ©1
488 V. Lari, S. Muddasani, S. Boppu, F. Hannig and J. Teich.
Design of Low Power On-Chip Processor Arrays.
In Proceedings of the 23rd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), pp. 165-168, Delft, Netherland, Jul. 9-11, 2012. ©3
487 S. Roloff, F. Hannig and J. Teich.
Simulation of Resource-Aware Applications on Heterogeneous Architectures.
In Proceedings of the 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), pp. 127-130, Fiuggi, Italy, July 8-14, 2012. ©1
486 A. Tanase, F. Hannig and J. Teich.
Symbolic loop parallelization of static control programs.
In Proceedings of the 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), pp. 33–36, Fiuggi, Italy, July 8-14, 2012. ©1
485 J. Teich.
Exploiting Dynamic Hardware Reconfigurability for Efficiency, Performance, and Reliability.
Keynote, 2012 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2012, Erlangen, Germany, June 25-28, 2012. IEEE 2012, ISBN 978-1-4673-1915-7. ©1
484 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators based on a Domain-Specific Language for Medical Imaging.
In Proceedings of the 11th International Symposium on Parallel and Distributed Computing (ISPDC), pp. 211-218, Munich, Germany, June 25-29, 2012. ©3
[doi>10.1109/ISPDC.2012.36]
483 M. Glaß, J. Teich and L. Zhang.
A Co-simulation Approach for System-Level Analysis of Embedded Control Systems.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2012), pp. 355-362, Samos, Greece, July 16-19, 2012. Invited Paper. ©1
482 M. Eberl, M. Glaß, J. Teich and U. Abelein.
Considering Diagnosis Functionality during Automatic System-Level Design of Automotive Networks.
In Proceedings of the 49th Design Automation Conference (DAC 2012), pp. 205-213, San Francisco, USA, Jun. 3-7, 2012. ©1
[doi>10.1145/2228360.2228400]
481 A. Tanase, F. Hannig and J. Teich.
Towards Symbolic Loop Parallelization for Tightly-Coupled Processor Arrays.
Work-In-Progress Presentation at the 49th Design Automation Conference (DAC), San Francisco, USA, June 3-7, 2012. ©1
480 C. Zebelein, C. Haubelt, J. Falk and J. Teich.
A Model-Based Inter-Process Resource Sharing Approach for High-Level Synthesis of Dataflow Graphs.
In Proc. of the 2012 Electronic System Level Synthesis Conference, pp. 17 - 22, San Francisco, California, USA, Jun. 2-3, 2012. ©1
479 J. Teich.
Hardware/Software Co-Design: Past, Present, and Predicting the Future.
Proceedings of the IEEE, vol. 100, no. 5, May 2012. Invited paper. pp. 1411-1430. ©1
[doi>10.1109/JPROC.2011.2182009]
478 J. Heisswolf, A. Zaib, A. Weichslgartner, R. König, T. Wild, J. Teich, A. Herkersdorf and J. Becker.
Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS.
In Proceedings of 19th Reconfigurable Architectures Workshop (RAW 2012), pp. 234 - 241, Shanghai, China, May 2012 . ©1
[doi>10.1109/IPDPSW.2012.25]
477 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Generating Device-specific GPU Code for Local Operators in Medical Imaging.
In Proceedings of the 26th IEEE International Parallel & Distributed Processing Symposium (IPDPS), pp. 569-581, Shanghai, China, May 21-25, 2012. ©3
[doi>10.1109/IPDPS.2012.59]
476 S. Roloff, F. Hannig and J. Teich.
Fast Architecture Evaluation of Heterogeneous MPSoCs by Host-Compiled Simulation.
In Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems (SCOPES), pp. 52-61, St. Goar, Germany, May 15-16, 2012. ©1
475 C. Dennl, D. Ziener and J. Teich.
On-the-fly Composition of FPGA-Based SQL Query Accelerators Using A Partially Reconfigurable Module Library.
Proceedings of the IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM), pp. 45-52, Toronto, Canada, April 29th - May 1st, 2012. ©3
[doi>10.1109/FCCM.2012.18]
474 R. Kiesel, M. Streubühr, C. Haubelt, A. Terzis and J. Teich.
Virtual Prototyping for Efficient Multi-Core ECU Development of Driver Assistance Systems.
In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XII), Samos, Greece, Jul. 16-19, 2012. ©3
473 S. Graf, T. Russ, M. Glaß and J. Teich.
Considering MOST150 during Virtual Prototyping of Automotive E/E Architectures.
In Proceedings of Automotive meets Electronics (AmE 2012) GMM Fachbericht 72, pp. 116-121, Dortmund, Germany, April 17-18, 2012. ©1
472 M. Schmid, F. Hannig and J. Teich.
Power Management Strategies for Serial RapidIO Endpoints in FPGAs.
Proceedings of the IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM'12), pp. 101-108, Toronto, Canada, April 29th - May 1st, 2012. ©3
471 Y. Xu, B. Li, R. Hasholzner, B. Rohfleisch, C. Haubelt and J. Teich.
Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis.
In Proceedings of Design, Automation and Test in Europe (DATE 2012), pp.346-351, Dresden, Germany, March 12-16, 2012.. ©1
[doi>10.1109/DATE.2012.6176495]
470 P. Milbredt, M. Glaß, M. Lukasiewycz, A. Steininger and J. Teich.
Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach.
In Proceedings of Design, Automation and Test in Europe (DATE 2012), pp. 276-279, Dresden, Germany, March 12-16, 2012. ©1
469 S. Graf, M. Glaß and J. Teich.
Unreliable Data Transmissions and Limited Hardware Communication Buffers in Automotive E/E Virtual Prototypes.
Proceedings of Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV´12), pp. 13-24, Kaiserslautern, Germany, March 05-07, 2012. ©1
468 L. Zhang, M. Glaß, M. Streubühr, J. Teich, A. v. Schwerin and K. Liu.
Actor-oriented Modeling and Simulation of Cut-through Communication in Network Controllers.
Proceedings of Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV´12), pp. 193-204,Kaiserslautern, Germany, March 05-07, 2012. ©1
467 C. Zebelein, J. Falk, C. Haubelt and J. Teich.
Exploiting Model-Knowledge in High-Level Synthesis.
In Workshop für Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV’12), Seite 181-191, Kaiserslautern, Mar. 5-7, 2012. ©1
466 Y. Xu, R. Rosales, B. Wang, M. Streubühr, R. Hasholzner, C. Haubelt and J. Teich.
A Very Fast and Quasi-Accurate Power-State-Based System-Level Power Modeling Methodology.
In Proceedings of the International Conference on Architecture of Computing Systems (ARCS), pages 37-49, Munich, Germany, March 2012. (Best Paper Award Nomination). ©1
[doi>10.1007/978-3-642-28293-5_4]
465 L. Zhang, M. Streubühr, M. Glaß, J. Teich, A. v. Schwerin and K. Liu.
System-Level Modeling and Simulation of Networked PROFINET IO Controllers.
Proceedings of the Embedded World Conference, Nuremberg, Germany, February 28 - March 01, 2012. ©1
464 D. Koch, J. Torresen, C. Beckhoff, D. Ziener, C. Dennl, V. Breuer, J. Teich, M. Feilen and W. Stechele.
Partial Reconfiguration on FPGAs in Practice - Tools and Applications.
In Proceedings of the 2012 Architecture of Computing Systems (ARCS'12), Munich, Germany. Feb. 28-29, 2012. ©1
463 R. Membarth, J. Lupp, F. Hannig, J. Teich, M. Körner and W. Eckert.
Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging.
In Proceedings of the 25th International Conference on Architecture of Computing Systems (ARCS), pp. 147-159, Munich, Germany, February 28 - March 02, 2012. ©1
[doi>10.1007/978-3-642-28293-5_13]
462 S. Wildermann, J. Angermeier, E. Sibirko and J. Teich.
Placing Multi-mode Streaming Applications on Dynamically Partially Reconfigurable Architectures.
International Journal of Reconfigurable Computing. Volume 2012 (2012), Article ID 608312, 12 pages. . ©1
[doi>doi:10.1155/2012/608312]
461 S. Roloff, F. Hannig and J. Teich.
Approximate Time Functional Simulation of Resource-Aware Programming Concepts for Heterogeneous MPSoCs.
In Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 187-192, Sydney, Australia, January 30-February 2, 2012. ©1
[doi>10.1109/ASPDAC.2012.6164943]
460 S. Fekete, T. Kamphans, N. Schweer, C. Tessars, J. van der Veen, J. Angermeier, D. Koch and J. Teich.
Dynamic Defragmentation of Reconfigurable Devices.
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 5 Issue 2, Article No. 8, June 2012. ©1
459 M. Lukasiewycz, M. Glaß, J. Teich and P. Milbredt.
FlexRay Static Segment Scheduling.
In S. Chakraborty and J. Eberspächer (Eds.): Advances in Real-Time Systems, pp. 323-339, Springer Verlag Berlin Heidelberg, 2012. ©1
[doi>10.1007/978-3-642-24349-3_16]
2011
458 S. Wildermann, F. Reimann, J. Teich and Z. Salcic.
Operational Mode Exploration for Reconfigurable Systems with Multiple Applications.
Proceedings of the International Conference on Field-Programmable Technology (FPT'11), New Delhi, India. Dec. 12-14, 2011. ©1
[doi>10.1109/FPT.2011.6132693]
457 T. Ziermann, B. Schmidt, M. Mühlenthaler, D. Ziener, J. Angermeier and J. Teich.
An FPGA Implementation of a Threat-based Strategy for Connect6.
Proceedings of the International Conference on Field-Programmable Technology (FPT'11), New Delhi, India. Dec. 12-14, 2011. ©1
456 J. Angermeier, D. Ziener, M. Glaß and J. Teich.
Runtime Stress-Aware Replica Placement on Reconfigurable Devices under Safety Constraints.
Proceedings of the International Conference on Field-Programmable Technology (FPT'11), pp. 1-6, New Delhi, India. Dec. 12-14, 2011. ©1
[doi>10.1109/FPT.2011.6133247]
455 S. Boppu, F. Hannig, J. Teich and R. Perez-Andrade.
Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays.
Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), pp. 392-397, Cancun, Mexico, Nov. 30 - Dec.2, 2011. ©1
454 V. Lari, S. Boppu, S. Muddasani, F. Hannig and J. Teich.
Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays.
International Workshop on Adaptive Power Management with Machine Intelligence at International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov. 10, 2011. ©1
453 S. Wildermann, F. Reimann, D. Ziener and J. Teich.
Symbolic Design Space Exploration for Multi-Mode Reconfigurable Systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 129-138, Taipei, Taiwan. Oct. 9-14, 2011. (Best Paper Candidate). ©1
[doi>10.1145/2039370.2039393]
452 P. Marwedel, J. Teich, G. Kouveli, I. Bacivarov, L. Thiele, S. Ha, C. Lee, Q. Xu and L. Huang.
Mapping of Applications to MPSoCs.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 109-118, Taipei, Taiwan. Oct. 9-14, 2011. ©1
451 J. Henkel, L. Bauer, J. Becker, O. Bringmann, U. Brinkschulte, S. Chakraborty, M. Engel, R. Ernst, H. Härtig, L. Hedrich, A. Herkersdorf, R. Kapitza, D. Lohmann, P. Marwedel, M. Platzner, W. Rosenstiel, U. Schlichtmann, O. Spinczyk, M. Tahoori, J. Teich, N. Wehn and H. Wunderlich.
Design and Architectures for Dependable Embedded Systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 69-78, Taipei, Taiwan. Oct. 9-14, 2011. ©1
450 M. Streubühr, R. Rosales, R. Hasholzner, C. Haubelt and J. Teich.
ESL Power and Performance Estimation for Heterogeneous MPSoCs Using SystemC.
In Forum on specification and Design Languages 2011, pp. 202-209, Oldenburg, Germany, Sep. 13-15, 2011. ©3
449 V. Lari, A. Narovlyanskyy, F. Hannig and J. Teich.
Decentralized Dynamic Resource Management Support for Massively Parallel Processor Arrays.
In Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), pp. 87-94, Santa Monica, CA, USA, Sep. 11-14, 2011. ©3
448 J. Angermeier, D. Ziener, M. Glaß and J. Teich.
Stress-Aware Module Placement on Reconfigurable Devices.
Proceedings of the Conference on Field-Programmable Logic and Applications (FPL 2011), pp. 277-281, Chania, Crete, Greece. Sep 5-7. 2011. ©1
447 S. Wildermann, D. Ziener and J. Teich.
Unifying Partitioning and Placement for SAT-based Exploration of Heterogeneous Reconfigurable SoCs.
Proceedings of the Conference on Field Programmable Logic and Applications (FPL 2011), pp. 429-434, Chania, Crete, Greece, Sep. 5-7, 2011. ©1
446 D. Ziener, S. Wildermann, A. Oetken, A. Weichslgartner and J. Teich.
A Flexible Smart Camera System based on a Partially Reconfigurable Dynamic FPGA-SoC.
Proceedings of the Workshop on Computer Vision on Low-Power Reconfigurable Architectures at FPL 2011, pp. 29-30, Chania, Crete, Greece, Sep. 4, 2011. ©1
445 T. Ziermann, Z. Salcic and J. Teich.
Self-organized Message Scheduling for Asynchronous Distributed Embedded Systems.
Proceedings of the 8th International Conference on Autonomic and Trusted Computing, Banff, Canada, pp. 132-148, Sep. 2-4, 2011. ©1
[doi>10.1007/978-3-642-23496-5_10]
444 R. Membarth, A. Lokhmotov and J. Teich.
Generating GPU Code from a High-level Representation for Image Processing Kernels.
In Proceedings of the 5th Workshop on Highly Parallel Processing on a Chip (HPPC), pp. 270-280, Bordeaux, France, August 30, 2011. ©1
[doi>10.1007/978-3-642-29737-3_31]
443 J. Gladigau, A. Gerstlauer, C. Haubelt, M. Streubühr and J. Teich.
Automatic System-Level Synthesis: From Formal Application Models to Generic Bus-Based MPSoCs.
Transactions on HiPEAC: Volume 5, Issue 4, pp. 1-22, Springer, 2011. ©1
442 J. Teich and D. Ziener.
Verifying the Authorship of Embedded IP Cores: Watermarking and Core Identification Techniques.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'11), pp. 93-103, Las Vegas, USA, Jul. 18-21, 2011. ©1
441 M. Lukasiewycz, M. Glaß, F. Reimann and J. Teich.
Opt4J - A Modular Framework for Meta-heuristic Optimization.
Proceedings of the Genetic and Evolutionary Computing Conference (GECCO 2011), pp. 1723-1730, Dublin, Ireland, Jul. 12-16, 2011. ©1
440 G. Kouveli, F. Hannig, J. Lupp and J. Teich.
Towards Resource-Aware Programming on Intel's Single-Chip Cloud Computer Processor.
In 3rd Many-core Applications Research Community (MARC) Symposium, Ettlingen, Germany, Jul. 5-6, 2011, volume 7598 of KIT Scientific Reports, pp. 111-114, KIT Scientific Publishing, 2011. ©1
439 F. Hannig, S. Roloff, G. Snelting, J. Teich and A. Zwinkau.
Resource-Aware Programming and Simulation of MPSoC Architectures through Extension of X10.
In Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems (SCOPES), pp. 48-55, St. Goar, Germany, June 27-28, 2011. ©1
[doi>10.1145/1988932.1988941]
438 D. Kissler, D. Gran, Z. Salcic, F. Hannig and J. Teich.
Scalable Many-Domain Power Gating in Coarse-grained Reconfigurable Processor Arrays.
IEEE Embedded Systems Letters, 3(2):58-61, 2011. ©1
437 T. Ziermann, S. Wildermann and J. Teich.
OrganicBus: Organic Self-organising Bus-Based Communication Systems.
In Organic Computing - A Paradigm Shift for Complex Systems, pp. 489-501, Springer Basel, 2011. ©1
[doi>10.1007/978-3-0348-0130-0_32]
436 R. Kiesel, M. Streubühr, C. Haubelt, O. Löhlein and J. Teich.
Calibration and Validation of Software Performance Models for Pedestrian Detection Systems.
In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XI), pp. 182-189, Samos, Greece, Jul. 18-21, 2011. ©1
435 A. Kern, H. Zhang, T. Streichert and J. Teich.
Testing Switched Ethernet Networks in Automotive Embedded Systems.
In Proceedings of the 6th IEEE International Symposium on Industrial Embedded Systems (SIES 2011), pp. 150-155, Västerås, Sweden, Jun. 15-17, 2011. ©1
434 F. Reimann, M. Lukasiewycz, M. Glaß, C. Haubelt and J. Teich.
Symbolic System Synthesis in the Presence of Stringent Real-Time Constraints.
Proceedings of the 48th Design Automation Conference (DAC 2011), pp. 393-398, San Diego, USA, Jun. 5-10, 2011. ©1
433 A. Kern, H. Zinner, T. Streichert, J. Nöbauer and J. Teich.
Accuracy of Ethernet AVB Time Synchronization Under Varying Temperature Conditions for Automotive Networks.
Proceedings of the 48th Design Automation Conference (DAC 2011), pp. 597-602, San Diego, USA, Jun. 5–10, 2011. ©1
432 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Frameworks for GPU Accelerators: A Comprehensive Evaluation using 2D/3D Image Registration.
In Proceedings of the 9th IEEE Symposium on Application Specific Processors (SASP), pp. 78-81, San Diego, CA, USA, June 5-6, 2011. ©3
[doi>10.1109/SASP.2011.5941083]
431 R. Membarth, H. Dutta, F. Hannig and J. Teich.
Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards.
In Transactions on High-Performance Embedded Architectures and Compilers (Transactions on HiPEAC), 5(3), 2011. ©3
430 P. Kutzer, J. Gladigau, C. Haubelt and J. Teich.
Automatic Generation of System-Level Virtual Prototypes from Streaming Application Models.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, pp. 128-134, Karlsruhe, Germany, May 24-27, 2011. ©1
429 V. Lari, F. Hannig and J. Teich.
Distributed Resource Reservation in Massively Parallel Processor Arrays.
In Proceedings of the International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 318-321, Anchorage, AK, USA, May 16-17, 2011. ©3
428 S. Graf, M. Streubühr, M. Glaß and J. Teich.
Analyzing Automotive Networks using Virtual Prototypes.
In Proceedings of Automotive meets Electronics (AmE 2011) GMM Fachbericht 69, pp. 10-15, Dortmund, Germany, May 4-5, 2011. ©1
427 A. Weichslgartner, S. Wildermann and J. Teich.
Dynamic Decentralized Mapping of Tree-Structured Applications on NoC Architectures.
In Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2011), pp. 201-208, Pittsburgh, USA, May 1-4, 2011. ©1
[doi>10.1145/1999946.1999979]
426 T. Ziermann, S. Wildermann, N. Mühleis and J. Teich.
Distributed Self-organizing Bandwidth Allocation for Priority-based Bus Communication.
In Concurrency and Computation: Practice and Experience, Wiley Online Library, 2011. ©1
[doi>10.1002/cpe.1759, 2011]
425 N. Mühleis, M. Glaß, L. Zhang and J. Teich.
A Co-Simulation Approach for Control Performance Analysis during Design Space Exploration of Cyber-Physical Systems.
ACM SIGBED Review - Work-in-Progress (WiP) Session of the 2nd International Conference on Cyber Physical Systems (ICCPS 2011). Volume 8(2): pp. 23-26, 2011. ©1
424 J. Angermeier, E. Sibirko, R. Wanka and J. Teich.
Bitonic Sorting on Dynamically Reconfigurable Architectures.
In Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing (IPDPS'11), pp. 314-317, Anchorage, USA, May 16-20, 2011, . ©1
[doi>10.1109/IPDPS.2011.164]
423 T. Ziermann, Z. Salcic and J. Teich.
DynOAA - Dynamic Offset Adaptation Algorithm for Improving Response Times of CAN Systems.
Proceedings of Design, Automation and Test in Europe (DATE'11), IEEE Computer Society, Grenoble, France, pp. 269-272, Mar. 14-18, 2011. ©3
422 J. Falk, C. Zebelein, C. Haubelt and J. Teich.
A Rule-Based Static Dataflow Clustering Algorithm for Efficient Embedded Software Synthesis.
Proceedings of Design, Automation and Test in Europe (DATE'11), IEEE Computer Society, Grenoble, France, pp. 521-526, Mar. 14-18, 2011. ©3
421 A. Kern, T. Streichert and J. Teich.
An Automated Data Structure Migration Concept - From CAN to Ethernet/IP in Automotive Embedded Systems (CANoverIP).
Proceedings of Design, Automation and Test in Europe (DATE'11), IEEE Computer Society, Grenoble, France, pp. 112-117, Mar. 14-18, 2011 . ©1
420 P. Kutzer, M. Streubühr, C. Haubelt, J. Teich and A. von Schwerin.
Actor-oriented Modeling of Industrial Ethernet in the Automation Domain Using SystemC .
Proceedings of the Embedded World Conference, pp. 1-10, Nuremberg, Germany, Mar. 1-3, 2011. ©1
419 N. Mühleis, M. Glaß and J. Teich.
Control Performance-Aware System Level Design.
In Proceedings of the 8th Workshop on Cyber-Physical Systems – Enabling Multi-Nature Systems (CPMNS 2011), pp. 15-20, Bremen, Germany, Feb. 23-24, 2011. ©1
418 J. Keinert and J. Teich.
Design of Image Processing Embedded Systems Using Multidimensional Data Flow.
Series Embedded Systems, Springer, New York, 1st edition, 2011. ©1
417 A. Kern, D. Reinhard, T. Streichert and J. Teich.
Gateway Strategies for Embedding of Automotive CAN-frames into Ethernet-packets and Vice Versa.
Proceedings of Architecture of Computing Systems Conference (ARCS'11), pp. 259-270, Lake Como, Italia, Feb. 22-25, 2011. ©1
416 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Frameworks for Multi-core Architectures: A Comprehensive Evaluation using 2D/3D Image Registration.
In Proceedings of the 24th International Conference on Architecture of Computing Systems (ARCS), pp. 62-73, Lake Como, Italy, February 22-25, 2011. ©1
[doi>10.1007/978-3-642-19137-4_6]
415 R. Membarth, F. Hannig, J. Teich, G. Litz and H. Hornegger.
Detector Defect Correction of Medical Images on Graphics Processors.
In Proceedings of the SPIE: Medical Imaging 2011: Image Processing, pp. 79624M 1-12, Lake Buena Vista, Orlando, FL, USA, February 12-17, 2011. ©1
[doi>10.1117/12.877656]
414 D. Kissler, F. Hannig and J. Teich.
Efficient Evaluation of Power/Area/Latency Design Trade-offs for Coarse-Grained Reconfigurable Processor Arrays.
Journal of Low Power Electronics, 7(1):29-40, 2011. ©1
413 J. Teich, J. Henkel, A. Herkersdorf, D. Schmitt-Landsiedel, W. Schröder-Preikschat and G. Snelting.
Invasive Computing: An Overview.
In Multiprocessor System-on-Chip, M. Hübner and J. Becker (Eds.), Chapter 11, pages 241-268, Springer, 2011. ©1
2010
412 J. Falk, C. Zebelein, J. Keinert, C. Haubelt, J. Teich and S. Bhattacharyya.
Analysis of SystemC actor networks for efficient synthesis.
ACM Transactions on Embedded Computing Systems, 10(2):94–127, 2010. ©1
411 J. Angermeier, S. Wildermann, E. Sibirko and J. Teich.
Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures.
Proceedings of International Conference on ReConFigurable Computing and FPGAs, pp. 91-96, December 13-15, 2010, Cancun, Mexico. ©1
410 F. Hannig, M. Schmid, J. Teich and H. Hornegger.
A Deeply Pipelined and Parallel Architecture for Denoising Medical Images.
In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT), pp. 485-490, Beijing, China, December 8-10, 2010. ©3
409 D. Ziener and J. Teich.
New Directions for FPGA IP Core Watermarking and Identification.
In Dagstuhl Seminar 10281 Proceedings, 2010. ©1
408 M. Glaß, M. Lukasiewycz, F. Reimann, C. Haubelt and J. Teich.
Symbolic System Level Reliability Analysis.
In Proceedings of the International Conference on Computer-Aided Design (ICCAD), pp. 185-189, San Jose, USA, November 07-11, 2010. Tutorial Paper. ©1
407 S. Wildermann, A. Oetken, J. Teich and Z. Salcic.
Self-Organizing Computer Vision for Robust Object Tracking in Smart Cameras.
In Proceedings of the 7th International Conference on Autonomic and Trusted Computing, pp. 1-16, Xi'an, China, October 26-29, 2010. (Best Paper). ©1
406 F. Reimann, M. Glaß, C. Haubelt, M. Eberl and J. Teich.
Improving Platform-Based System Synthesis by Satisfiability Modulo Theories Solving.
In Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 135-144, Scottsdale, USA. October 24-29 2010. ©3
405 D. Ziener, M. Schmid and J. Teich.
Robustness Analysis of Watermark Verification Techniques for FPGA Netlist Cores.
In Design Methodologies for Secure Embedded Systems, A. Biedermann and H. Gregor Molter (Eds.), Lecture Notes in Electrical Engineering, volume 78, pp. 105-127, Springer-Verlag, Berlin Heidelberg, 2010. ©1
404 J. Teich.
Invasive Computing - Basic Concepts and Foreseen Benefits.
Artist Network of Excellence on Embedded System Design Summer School Europe 2010, Autrans, France, September 7, 2010, Invited Tutorial. ©1
403 A. Oetken, S. Wildermann, J. Teich and D. Koch.
A Bus-based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs.
In Proceedings of International Conference on Field-Programmable Logic and Applications (FPL'10), pp. 234-239, Milan, Italy, 2010. ©3
402 J. Falk, J. Keinert, C. Haubelt, J. Teich and C. Zebelein.
Integrated Modeling Using Finite State Machines and Dataflow Graphs.
In Handbook of Signal Processing Systems, pp. 1041-1075, Springer, 2010. ©1
401 J. Teich.
Invasive Computing - An Overview.
Invited Talk, The University of Sydney, Australia, August 9, 2010. ©1
400 J. Teich.
Invasive Computing - A Novel Paradigm for Parallel Computing.
Presentation at the School of Computing, National University of Singapore (NUS), Singapore, August 6. 2010. ©1
399 M. Streubühr, J. Gladigau, C. Haubelt and J. Teich.
Efficient Approximately-Timed Performance Modeling for Architectural Exploration of MPSoCs.
In D. Borrione editor, Advances in Design Methods from Modeling Languages for Embedded Systems and SoC's, volume 63 of Lecture Notes in Electrical Engineering. pp. 59-72, Springer Netherlands, 2010. ©1
398 A. Kern, C. Schmutzler, T. Streichert, M. Hübner and J. Teich.
Network Bandwidth Optimization of Ethernet-based Streaming Applications in Automotive Embedded Systems.
In Proceedings of the Internaional Conference on Computer Communication Networks (ICCCN) 2010 – Track on Network Algorithms, Performance Evaluation and Theory (NAPET), Zurich, Switzerland, August 2-5, 2010. ©1
397 J. Gladigau, A. Gerstlauer, M. Streubühr, C. Haubelt and J. Teich.
A System-Level Synthesis Approach from Formal Application Models to Generic Bus-Based MPSoCs.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), pp. 118-125, Samos, Greece, July 19-22, 2010. ©3
396 F. Charot, F. Hannig, J. Teich and C. Wolinski.
Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP).
IEEE Computer Society, 2010, ISBN 978-1-4244-6967-3. ©3
395 C. Haubelt and J. Teich.
Digitale Hardware/Software-Systeme: Spezifikation und Verifikation.
1. Auflage, ©Springer-Verlag, Berlin, Heidelberg, Germany, 2010. ©1
394 D. Ziener, F. Baueregger and J. Teich.
Multiplexing Methods for Power Watermarking.
In Proceedings of the IEEE Int. Symposium on Hardware-Oriented Security and Trust (HOST 2010), pp. 54-59, Anaheim, USA, June 13-14, 2010. ©2
393 J. Teich.
Invasive Computing - A Novel Parallel Computing Paradigm.
Invited Talk, Workshop Multiprocessor System-On-Chip (MPSOC): Programmability, Run-Time Support and Hardware Platforms for High Performance Applications, 47th Design Automation Conference (DAC), Anaheim, USA, June 13, 2010. ©1
392 M. Glaß, M. Lukasiewycz, C. Haubelt and J. Teich.
Towards Scalable System-Level Reliability Analysis.
In Proceedings of the 2010 ACM/EDAC/IEEE Design Automation Conference (DAC 2010), pp. 234-239, Anaheim, CA, U.S.A., June 13-18, 2010. ©1
391 T. Ziermann, N. Mühleis, S. Wildermann and J. Teich.
Self-organizing Distributed Reinforcement Learning Algorithm to Achieve Fair Bandwidth Allocation for Priority-based Bus Communication.
In Proceedings of the 1st IEEE Workshop on Self-Organizing Real-Time systems (SORT 2010), pp. 11-20, Carmona, Spain, 11 May 2010. ©2
390 J. Sim, W. Wong, G. Walla, T. Ziermann and J. Teich.
Interprocedural Placement-Aware Configuration Prefetching for FPGA-based Systems.
In Proceedings of the 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'10), Charlotte, USA, pp. 179 - 182, May 02-04, 2010, HiPEAC Award. ©1
389 D. Ziener, F. Baueregger and J. Teich.
Using the Power Side Channel of FPGAs for Communication.
In Proceedings of the 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'10), pp. 237-244, Charlotte, USA, May 02-04, 2010. ©1
388 J. Angermeier, J. Teich, T. Kamphans and S. Fekete.
Virtual Area Management: Multitasking on Dynamically Partially Reconfigurable Devices.
In Proceedings of 17th Reconfigurable Architectures Workshop (RAW 2010), Atlanta, USA, April 2010. ©1
387 T. Ziermann and J. Teich.
Adaptive Traffic Scheduling Techniques for Mixed Real-Time and Streaming Applications on Reconfigurable Hardware.
In Proceedings of 17th Reconfigurable Architectures Workshop (RAW 2010), Atlanta, USA, April 19-20, 2010. ©2
386 J. Teich.
Invasives Rechnen.
Eingeladener Vortrag, 30. Sitzung Leitungskreis der Fachgruppe RSS (Rechnergestützter Schaltungs- und Systementwurf), VDE, Frankfurt am Main, April 9, 2010. ©1
385 T. Ziermann and J. Teich.
Electromagnetic Compatibility (EMC) of CAN+.
Proceedings of Automotive meets Electronics (AmE 2010), pp. 25-30, Dortmund, Germany, April 15-16, 2010. ©1
384 F. Reimann, A. Kern, C. Haubelt, T. Streichert and J. Teich.
Echtzeitanalyse Ethernet-basierter E/E-Architekturen im Automobil.
In: GMM-Fachbericht -- Automotive meets Electronics (AmE 2010), (64), 2010, p. 9–14. ©1
383 J. Teich.
The DFG Priority Program 1148 Reconfigurable Computing - Achievements and Lessons Learned.
DATE Friday Workshop The European Landscape of Reconfigurable Computing: Lessons Learned, new Perspectives and Innovations, Dresden, Germany, March 2010. Invited Talk. ©1
382 H. Dutta, F. Hannig and J. Teich.
PARO - A Design Tool for Synthesis of Hardware Accelerators for SoCs.
Tool Presentation at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March 8-12, 2010. ©1
381 M. Lukasiewycz, M. Glaß and J. Teich.
Robust Design of Embedded Systems.
In Proceedings of Design, Automation and Test in Europe (DATE 2010), pp. 1578-1583, Dresden, Germany, March 08-12, 2010. ©1
380 C. Zebelein, J. Falk, C. Haubelt, J. Teich and R. Dorsch.
Efficient High-Level Modeling in the Networking Domain.
In Proceedings of Design, Automation and Test in Europe (DATE 2010) Dresden, Germany, pp. 1189-1194, March 8-12, 2010. ©1
379 M. May, N. Wehn, A. Bouajila, J. Zeppenfeld, W. Stechele, A. Herkersdorf, D. Ziener and J. Teich.
A Rapid Prototyping System for Error-Resilient Multi-Processor Systems-on-Chip.
Proceedings of Design, Automation and Test in Europe (DATE'10), Dresden, Germany, March 08-12, pp. 375-380, 2010. ©1
378 M. Schmid, F. Hannig, J. Teich, R. Diefenbach, H. Pettendorf and H. Hornegger.
Discourse on Extending Embedded Medical Image Processing Systems Using the High Speed Serial RapidIO Interconnect.
Proceedings of the Embedded World Conference, Nuremberg, Germany, March 03-05, 2010. ©1
377 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Comparison of Parallelization Frameworks for Shared Memory Multi-Core Architectures.
In Proceedings of the Embedded World Conference, Nuremberg, Germany, March 03-05, 2010. ©1
376 R. Kiesel, O. Löhlein, A. Terzis, M. Streubühr, C. Haubelt and J. Teich.
Actor-oriented Modeling of Driver Assistance Systems for Efficient Multi-Core ECU Implementation.
In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, pp 117-126, Dresden, Germany, Feb. 2010. ©1
375 J. Falk, C. Zebelein, C. Haubelt, J. Teich and R. Dorsch.
Integrating Hardware/Firmware Verification Efforts Using SystemC High-Level Models.
In 13. ITG/GI/GMM Workshop für Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Fraunhofer IIS/EAS Dresden, pp. 137-146, February 22-24, 2010. ©1
374 C. Haubelt, D. Koch, F. Reimann, T. Streichert and J. Teich.
ReCoNets – Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections.
In Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications, p. 223-244, Springer, Heidelberg, February 2010. 10.1007/978-90-481-3485-4_11. ©1
373 S. Fekete, T. Kamphans, N. Schweer, C. Tessars, J. van der Veen, A. Ahmadinia, J. Angermeier, D. Koch, M. Majer and J. Teich.
ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices.
In Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications, p. 199-222, Springer, Heidelberg, February 2010. ©1
372 M. Platzner, J. Teich and N. Wehn.
Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications.
Springer, Heidelberg, February 2010. ©1
371 J. Angermeier, C. Bobda, M. Majer and J. Teich.
Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform.
In Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications, p. 51-71, Springer, Heidelberg, February 2010. ©1
370 M. Glaß, M. Lukasiewycz, C. Haubelt and J. Teich.
Lifetime Reliability Optimization for Embedded Systems: A System-Level Approach.
Proceedings of IEEE International Workshop on Reliability Aware System Design and Test (RASDAT '10), pp. 17-22, Bangalore, India, January 07-08, 2010. ©1
2009
369 V. Schöber, O. Bringmann, A. Herkersdorf, W. Stechele, N. Wehn, M. May, D. Ziener, A. Bouajila, D. Baldin, J. Zeppenfeld, B. Sanders, J. Teich, M. Sebastian, R. Ernst and D. Treytnar.
AIS-Autonomous Integrated Systems.
In newsletter edacentrum 04 2009, pp. 05-13, edacentrum, Hannover, 2009. ©1
368 S. Wildermann, J. Teich and T. Ziermann.
Run time Mapping of Adaptive Applications onto Homogeneous NoC-based Reconfigurable Architectures.
In Proceedings of the International Conference on Field-Programmable Technology (FPT'09), pp. 514-517, Sydney, Australia, December 9-11, 2009. ©1
367 A. Amouri, F. Arifin, F. Hannig and J. Teich.
FPGA Implementation of an Invasive Computing Architecture.
In Proceedings of the International Conference on Field-Programmable Technology (FPT), pp. 135-142, Sydney, Australia, December 9-11, 2009. ©2
366 J. Teich.
From Dynamic Reconfiguration to Self-Configuration: Invasive Algorithms and Architectures.
Keynote, 2009 International Conference on Field-Programmable Technology (FPT'09), Sydney, Australia, pp. 11-12, December 9-11, 2009. ©1
365 H. Greve, S. Egelkraut, M. Rösch, M. Glaß, M. März, J. Franke, J. Teich and L. Frey.
Zuverlässigkeitsuntersuchung von PBGA Lotverbindungen für Automobilanwendungen.
In Proceedings of IMAPS 2009, Munich, Germany, October 27-28, 2009. ©1
364 F. Arifin, R. Membarth, A. Amouri, F. Hannig and J. Teich.
FSM-Controlled Architectures for Linear Invasion.
In Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 59-64, Florianópolis, Brazil, October 12-14, 2009. ©2
[doi>10.1109/VLSISOC.2009.6041331]
363 M. Lukasiewycz, M. Glaß and J. Teich.
Exploiting Data-Redundancy in Reliability-Aware Networked Embedded System Design.
In Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 229-238, Grenoble, France, October 11-16 2009. ©1
362 M. Lukasiewycz, M. Glaß, P. Milbredt and J. Teich.
FlexRay Schedule Optimization of the Static Segment.
In Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 363-372, Grenoble, France, October 11-16 2009. ©1
361 A. Gerstlauer, C. Haubelt, A. Pimentel, T. Stefanov, D. Gajski and J. Teich.
Electronic System-Level Synthesis Methodologies.
In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(10), pages 1517-1530, October 2009. ©1
360 M. Streubühr, J. Gladigau, C. Haubelt and J. Teich.
Efficient Approximately-Timed Performance Modeling for Architectural Exploration of MPSoCs.
In Forum on specification and Design Languages 2009, pp. 1-6, Sophia Antipolis, France, Sep. 22-24, 2009. ©1
359 V. Lari, F. Hannig and J. Teich.
System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance.
In proceedings of the 38th International Conference on Parallel Processing Workshops - the 4th International Symposium on Embedded Multicore Systems-on-Chip (MCSoC'09), pp. 528-534, Vienna, Austria, Sep. 22-25, 2009. ©2
358 S. Wildermann, T. Ziermann and J. Teich.
Self-organizing Bandwidth Sharing in Priority-based Medium Access.
In Proceedings of the Third IEEE International Conference on Self-Adaptive and Self-Organizing Systems (SASO), pp.144-153, San Francisco, California, Sep. 14-18, 2009 . ©1
357 S. Wildermann, G. Walla, T. Ziermann and J. Teich.
Self-Organizing Multi-cue Fusion for FPGA-based Embedded Imaging.
In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), pp. 132 - 137, Prague, Czech Republic, Aug. 31 - Sep. 02, 2009. ©1
356 M. Glaß, M. Lukasiewycz, J. Teich, U. Bordoloi and S. Chakraborty.
Designing Heterogeneous ECU Networks via Compact Architecture Encoding and Hybrid Timing Analysis.
In Proceedings of the 2009 ACM/EDAC/IEEE Design Automation Conference (DAC 2009), pp. 43-46, San Francisco, CA, U.S.A., July 26-31, 2009. ©1
355 R. Membarth, F. Hannig, H. Dutta and J. Teich.
Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors.
In Proceedings of the 9th International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS Workshop), pp. 277-288, July 20-23, 2009. ©1
[doi>10.1007/978-3-642-03138-0_31]
354 R. Membarth, F. Hannig, H. Dutta and J. Teich.
Optimization Flow for Algorithm Mapping on Graphics Cards.
In Proceedings of ACACES 2009 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems, pp. 229-232, Barcelona, Spain, July 12-18, 2009. ©1
353 R. Membarth, P. Kutzer, H. Dutta, F. Hannig and J. Teich.
Acceleration of Multiresolution Imaging Algorithms: A Comparative Study.
In Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 211-214, Boston, MA, USA, July 7-9, 2009. ©2
[doi>10.1109/ASAP.2009.8]
352 D. Ziener and J. Teich.
Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs.
Int. Journal of Autonomous and Adaptive Communications Systems, Vol. 2, No. 3, pp. 256-275, Inderscience Enterprises Ltd, 2009. ©1
351 J. Teich.
SystemCoDesigner: Automatic Design Space Exploration and Rapid Prototyping from Behavioral Models.
Invited Talk, 2nd Workshop on MPSoC, ArtistDesign Network of Excellence, St. Goar, Germany, 2009. ©1
350 J. Teich.
SystemCoDesigner - Automatic Design Space Exploration and Prototyping from Behavioral Models.
2nd Workshop on Mapping of Applications to MPSoCs, EU Network of Excellence Artistdesign, Invited talk, Schloss Rheinfels, St. Goar, Germany, June 29, 2009. ©1
349 J. Angermeier, A. Amouri and J. Teich.
General Methodology for Mapping Iterative Aproximation Algorithms to Adaptive Dynamically Partially Reconfigurable Systems.
Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pp. 302-307, Prague, Czech Republic, August 31, 2009. ©1
348 J. Gladigau, C. Haubelt and J. Teich.
Symbolic Scheduling of SystemC Dataflow Designs.
In M. Radetzki, editor, Languages for Embedded Systems and their Applications, volume 36 of Lecture Notes in Electrical Engineering, pages 183–199. Springer Netherlands, 2009.
Available at SpringerLink: here. ©1
347 J. Keinert and J. Teich.
Data Flow Based System Level Design and Analysis of Image Processing Applications.
Poster on the EDAA PhD forum at DATE 2009, Nice, April 2009. ©1
346 J. Teich and D. Gajski.
The Future of ESL Synthesis.
DATE´09 Friday Workshop W3, Nice, France, 24.3.2009. Workshop Organization. ©1
345 J. Keinert, C. Haubelt and J. Teich.
Data Flow Based System Level Design and Analysis of Concurrent Image Processing Applications.
Proceedings of DATE'09 Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Nice, April 2009, pp. 215-216. ©1
344 H. Dutta, J. Zhai, F. Hannig and J. Teich.
Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines.
Proceedings of 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), pp. 161-168, Boston, MA, USA, July 7-9, 2009. ©1
343 T. Ziermann, S. Wildermann and J. Teich.
CAN+: A New Backward-compatible Controller Area Network (CAN) Protocol with up to 16x Higher Data Rates.
Proceedings of Design, Automation and Test in Europe (DATE 2009), IEEE Computer Society, Nice, France, pp. 1088-1093, April 20-24, 2009. ©1
342 J. Keinert, H. Dutta, F. Hannig, C. Haubelt and J. Teich.
Model-Based Synthesis and Optimization of Static Multi-Rate Image Processing Algorithms.
Proceedings of Design, Automation and Test in Europe (DATE 2009), IEEE Computer Society, Nice, France, April 20-24, 2009, pp. 135-140. ©1
341 J. Teich and C. Haubelt.
Principles: Analysis, Optimization and Exploration.
DATE´09 Monday Tutorial: System-Level Modeling, Analysis and Synthesis of Embedded Multi-Core Designs, Nice, Farnce, 2009. Invited Talk. ©1
340 M. Lukasiewycz, M. Streubühr, M. Glaß, C. Haubelt and J. Teich.
Combined System Synthesis and Communication Architecture Exploration for MPSoCs.
Proceedings of Design, Automation and Test in Europe (DATE 2009), pp. 472-477, IEEE Computer Society, Nice, France, April 20-24, 2009. ©1
339 M. Glaß, M. Lukasiewycz, C. Haubelt and J. Teich.
Incorporating Graceful Degradation into Embedded System Design.
Proceedings of Design, Automation and Test in Europe (DATE 2009), pp. 320-323, IEEE Computer Society, Nice, France, April 20-24, 2009. ©1
338 D. Koch, C. Beckhoff and J. Teich.
A Communication Architecture for Complex Runtime Reconfigurable Systems and its Implementation on Spartan-3 FPGAs.
Proceedings of the 17th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2009), pp. 233-236, Monterey, California, USA
Extended paper version:. ©2
337 J. Teich.
Invasives Rechnen.
GIBU-Jahrestreffen 2009, Schloss Dagstuhl, Wadern, 6.4.2009. Invited Talk. ©1
336 J. Sim, W. Wong and J. Teich.
Optimal Placement-aware Trace-based Scheduling of Hardware Reconfigurations for FPGA Accelerators.
Proceedings 17th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2009), Napa, California, pp. 279-282, April, 2009. ©1
335 D. Koch, C. Beckhoff and J. Teich.
Minimizing Internal Fragmentation by Fine-grained Two-dimensional Module Placement for Runtime Reconfigurable Systems.
Proceedings 17th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2009), pp. 251-254, Napa, California, April, 2009. ©1
334 J. Teich.
Embedded System Design.
3rd Chinese-German Summer School, 11.5.2009, Erlangen, Germany. Invited Lecture. ©1
333 T. Ziermann, J. Teich and S. Wildermann.
CAN+: Techniques and Prototype for Achieving Increased Data Rates on the Basis of Common CAN Bus Structures.
Proceedings of 9th Stuttgart International Symposium, pp. 327-339, Stuttgart, Germany, March 24-25, 2009 . ©1
332 H. Dutta, F. Hannig and J. Teich.
Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis.
In Proceedings of the 22nd International Conference on Architecture of Computing Systems (ARCS), Delft, The Netherlands, pp. 233-245, March 10-13, 2009. ©1
331 F. Hannig, H. Dutta and J. Teich.
Parallelization Approaches for Hardware Accelerators - Loop Unrolling versus Loop Partitioning.
In Proceedings of the 22nd International Conference on Architecture of Computing Systems (ARCS), Delft, The Netherlands, pp. 16-27, March 10-13, 2009. ©1
330 M. Streubühr, M. Jäntsch, C. Haubelt and J. Teich.
From Model-based Design to Virtual Prototypes for Automotive Applications.
In Proceedings of the Embedded World Conference, pp. 1-10, Nuremberg, Germany, March 03-05, 2009. ©1
329 J. Gladigau, C. Haubelt, M. Streubühr, J. Teich, A. Schneider, J. Knäblein and M. Lindig.
Testfallgenerierung für SystemC-Designs mit abstrakten Modellbeschreibungen.
In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Seite 157-166, Berlin, Germany, March 2-4, 2009. ©1
328 D. Kissler, A. Strawetz, F. Hannig and J. Teich.
Power-efficient Reconfiguration Control in Coarse-grained Dynamically Reconfigurable Architectures.
Journal of Low Power Electronics, 5(1):96-105, American Scientific Publishers, 2009. ©1
327 H. Dutta, D. Kissler, F. Hannig, A. Kupriyanov, J. Teich and B. Pottier.
A Holistic Approach for Tightly Coupled Reconfigurable Parallel Processors.
Microprocessors and Microsystems, 33(1):53-62, 2009. ©1
326 J. Keinert, M. Streubühr, T. Schlichter, J. Falk, J. Gladigau, C. Haubelt, J. Teich and M. Meredith.
SYSTEMCODESIGNER - An Automatic ESL Synthesis Approach by Design Space Exploration and Behavioral Synthesis for Streaming Applications.
In ACM Transactions on Design Automation of Electronic Systems, 14(1), pp. 1-23, 2009. ©1
325 M. Streubühr, C. Haubelt and J. Teich.
System Level Performance Simulation for Heterogeneous Multi-Processor Architectures.
1st HiPEAC Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), in conjunction with the 4th HiPEAC Conference, pp. 47-52, Paphos, Cyprus, January 25, 2009. ©1
324 D. Koch, C. Beckhoff and J. Teich.
Hardware Decompression Techniques for FPGA-based Embedded Systems.
ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol.2, no. 9, June 2009. ©1
2008
323 M. Schmid, D. Ziener and J. Teich.
Netlist-Level IP Protection by Watermarking for LUT-Based FPGAs.
In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2008), pp. 209-216, Taipei, Taiwan, December 08-10, 2008. ©1
322 J. Falk, J. Keinert, C. Haubelt, J. Teich and S. Bhattacharyya.
A Generalized Static Data Flow Clustering Algorithm for MPSoC Scheduling of Multimedia Applications.
In Proc. of the 8th ACM & IEEE international conference on Embedded software (EMSOFT'2008), pp. 189-198, Atlanta, Georgia, USA, October 20-22, 2008. ©1
321 F. Reimann, M. Glaß, M. Lukasiewycz, J. Keinert, C. Haubelt and J. Teich.
Symbolic Voter Placement for Dependability-Aware System Synthesis.
In Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 237-242, Atlanta, GA USA, October 19-24 2008. ©1
320 J. Teich.
Reconfigurability of Future Massively Parallel SoCs.
Talk at the Department of Electrical and Computer Engineering, National University of Singapore, October 17, 2008. ©1
319 J. Keinert, C. Haubelt and J. Teich.
Automatic Synthesis of Design Alternatives for Fast Stream-Based Out-of-Order Communication.
Proceedings of the 2008 IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, (VLSI-SoC 2008) pp. 265-270, Rhodes Island, Greece, October 13-15, 2008. ©1
318 J. Teich.
Invasive Algorithms and Architectures.
it - Information Technology, http://it-information-technology.de, Oldenbourg Wissenschaftsverlag, vol. 50(5):300-310, 2008. ©1
317 J. Teich.
Actor-Based Electronic System Level (ESL) Design Using SystemC.
Talk at the School of Computing, National University of Singapore, September 26, 2008. ©1
316 J. Gladigau, C. Haubelt and J. Teich.
Symbolic Quasi-Static Scheduling of Actor-Oriented SystemC Models.
Proceedings of Forum on specification & Design Languages 2008 (FDL08), Digital Object Identifier 10.1109/FDL.2008.4641412, pages 1-6, Stuttgart, Germany, Sep. 23-25, 2008. ©2
315 M. Glaß, M. Lukasiewycz, F. Reimann, C. Haubelt and J. Teich.
Symbolic Reliability Analysis of Self-healing Networked Embedded Systems.
In Proceedings of the 27th International Conference on Computer Safety, Reliability and Security (SAFECOMP 2008), pp. 139-152, Newcastle upon Tyne, UK, September 22-25, 2008. ©1
314 M. Lukasiewycz, M. Glaß and J. Teich.
A Feasibility-preserving Crossover and Mutation Operator for Constrained Combinatorial Problems.
In Proceedings of the 10th International Conference on Parallel Problem Solving from Nature (PPSN 2008), pp. 919-928, Dortmund, Germany, September 13-17, 2008. ©1
313 S. Fekete, J. van der Veen, A. Ahmadinia, D. Göhringer, M. Majer and J. Teich.
Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.16(9):1210-1219, September 2008. ©1
312 S. Wildermann and J. Teich.
A Sequential Learning Resource Allocation Network for Image Processing Applications.
Proceedings of the 8th International Conference on Hybrid Intelligent Systems (HIS 2008), pp. 132-137, Barcelona, Spain, September 10-12, 2008. ©2
311 C. Claus, W. Stechele, M. Kovatsch, J. Angermeier and J. Teich.
A comparison of embedded reconfigurable video-processing architectures.
Proceedings of 18th International Conference on Field Programmable Logic and Applications (FPL 2008), Heidelberg, Germany, September 8 - 10, 2008, pp. 587-590.. ©1
310 C. Wolinski, K. Kuchcinski, J. Teich and F. Hannig.
Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures.
Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), pp. 391-396, Heidelberg, Germany, September 8-10, 2008. ©1
309 D. Koch, C. Beckhoff and J. Teich.
ReCoBus-Builder – a Novel Tool and Technique to Build Statically and Dynamically Reconfigurable Systems for FPGAs.
Proceedings of International Conference on Field-Programmable Logic and Applications (FPL 08), pp. 119-124, Heidelberg, Germany. ©1
308 D. Koch, T. Streichert, C. Haubelt and J. Teich.
Logic Chip, Method and Computer Program for Providing a Configuration Information for a Configurable Logic Chip.
Patent PCT/EP2008/007343, filed 8.9.2008. ©1
307 D. Koch, T. Streichert, C. Haubelt and J. Teich.
Logic Chip, Logic System and Method for Designing a Logic Chip.
Patent PCT/EP2008/007342, filed 8.9.2008. ©1
306 S. Fekete, J. van der Veen, J. Angermeier, D. Koch and J. Teich.
No-Break Dynamic Defragmentation of Reconfigurable Devices.
Proceedings of International Conference on Field-Programmable Logic and Applications (FPL 08), pp. 113-118, Heidelberg, Germany. ©1
305 C. Wolinski, K. Kuchcinski, J. Teich and F. Hannig.
Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures.
Proceedings of the 11th Euromicro Conference on Digital System Design (DSD), pp.345-352, Parma, Italy, September 3-5, 2008. ©1
304 R. Schaffer, R. Merker, F. Hannig and J. Teich.
Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism.
Proceedings of the 11th Euromicro Conference on Digital System Design (DSD), pp. 391-398, Parma, Italy, September 3-5, 2008. ©1
303 C. Haubelt, J. Teich and R. Dorsch.
Entdecke die Möglichkeiten.
In Design&Elektronik (8):22-27, 2008, WEKA. ©1
302 M. Glaß, M. Lukasiewycz, R. Wanka, C. Haubelt and J. Teich.
Multi-Objective Routing and Topology Optimization in Networked Embedded Systems.
In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2008), pp. 74-81, Samos, Greece, July 21-24, 2008. ©1
301 C. Haubelt, J. Falk, C. Zebelein, J. Keinert, J. Teich and S. Bhattacharyya.
SystemCoDesigner - An ESL Design Methodology Based on the FunState MoC.
Talk at 2nd Artist Workshop on Models of Computation and Communication, Eindhoven, The Netherlands, July 3, 2008. ©1
300 J. Teich.
Reconfigurability Issues of Future Massively Parallel SoCs.
8th International Forum on Application-Specific Multi-Processor SoC (MPSoC'08), 23 - 27 June 2008, Aachen, Germany. ©1
299 S. Wildermann and J. Teich.
Theoretical Analysis of Fair Bandwidth Sharing in Priority-based Medium Access.
Technical Report 06-2008, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, June 2008. ©1
298 D. Ziener and J. Teich.
Concepts for Autonomous Control Flow Checking for Embedded CPUs.
In Proceedings of the 5th International Conference on Autonomic and Trusted Computing (ATC08), pp. 234-248, Oslo, Norway, June 23-25, 2008. ©1
297 H. Dutta, F. Hannig and J. Teich.
PARO: A Design Tool for Automatic Generation of Hardware Accelerators..
In Proceedings of ACACES 2008 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems,. ©1
296 J. Teich and F. Schäfer.
ESL Methodologies for Platform-Based Synthesis.
Special Session, 2008 ACM/EDAC/IEEE Design Automation Conference (DAC 2008), Anaheim, USA, June 08-13, 2008. ©1
295 M. Lukasiewycz, M. Glaß, C. Haubelt, J. Teich, R. Regler and B. Lang.
Concurrent Topology and Routing Optimization in Automotive Network Integration.
In Proceedings of the 2008 ACM/EDAC/IEEE Design Automation Conference (DAC 2008), pp. 626-629, Anaheim, CA, U.S.A., June 08-13, 2008. ©1
294 M. Majer, S. Wildermann, J. Angermeier, S. Hanke and J. Teich.
Co-Design Architecture and Implementation for Point-Based Rendering on FPGAs.
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping (RSP 2008), pp. 142-148, Monterey, California, June 2-5, 2008. ©2
293 C. Zebelein, J. Falk, C. Haubelt and J. Teich.
Classification of General Data Flow Actors into Known Models of Computation.
In Proc. of the Sixth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2008), pp. 119-128, Anaheim, CA, USA, June 5-7, 2008. ©1
292 M. Lukasiewycz, M. Glaß, C. Haubelt and J. Teich.
A Feasibility-preserving Local Search Operator for Constrained Discrete Optimization Problems.
In Proceedings of the 2008 IEEE Congress on Evolutionary Computation (CEC 2008), pp. 1968-1975, Hong Kong, China, June 01-06, 2008. ©1
291 A. Kupriyanov, F. Hannig, D. Kissler and J. Teich.
MAML: An ADL for Designing Single and Multiprocessor Architectures.
In Prabhat Mishra and Nikil Dutt (eds.). Chapter 12 in Processor Description Languages, pp. 295-327. In Systems on Silicon Series, Morgan Kaufmann, June 2008. ©1
290 D. Kissler, A. Strawetz, F. Hannig and J. Teich.
Power-efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures.
In Proceedings of the 18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Lisbon, Portugal, September 10-12, 2008. LNCS vol. 5349, pp. 307–317. Springer, Heidelberg (2009). ©1
289 J. Angermeier and J. Teich.
Heuristics for Scheduling Reconfigurable Devices with Consideration of Reconfiguration Overheads.
Proceedings 15th Reconfigurable Architectures Workshop (RAW 2008), pp. 1-8, Miami, Florida, April 2008. ©1
288 D. Koch, C. Haubelt and J. Teich.
Efficient Reconfigurable On-Chip Buses for FPGAs.
Proceedings 16th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2008), pp. 287-290, Palo Alto, California, April 14-15, 2008. ©1
287 C. Wolinski, K. Kuchcinski, J. Teich and F. Hannig.
Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures.
In Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 306-309, Palo Alto, CA, USA, April 14-15, 2008. ©1
286 J. Teich.
Invasion - A New Parallel Computing and Architecture Paradigm.
Dagstuhl Seminar No. 08141, Organic Computing - Controlled Self-organization, IBFI, March 31- April 4, 2008. ©1
285 D. Ziener and J. Teich.
Power Signature Watermarking of IP Cores for FPGAs .
Journal of Signal Processing Systems, Volume 51, Number 1 / April 2008, pages 123-136, Springer. ©1
284 F. Hannig, H. Ruckdeschel, H. Dutta and J. Teich.
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications.
Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing (ARC), Lecture Notes in Computer Science (LNCS), pp. 287-293, Springer, London, United Kingdom, March 26-28, 2008. ©1
283 J. Angermeier, U. Batzer, M. Majer, J. Teich, C. Claus and W. Stechele.
Reconfigurable HW/SW Architecture of a Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System.
Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing (ARC), Lecture Notes in Computer Science (LNCS), pp. 149-159, Springer, London, United Kingdom, March 26-28, 2008. ©1
282 H. Dutta, F. Hannig and J. Teich.
The PARO Design Tool for Automatic Generation of Hardware Accelerators.
Interactive Presentation at Friday Workshop, The New Wave of the High-Level Synthesis, Design, Automation and Test in Europe (DATE), Munich, Germany, March 10-14, 2008. ©1
281 J. Teich, F. Hannig, H. Dutta, D. Kissler and M. Hartl.
Domain-Specific Reconfigurable MPSoC-Systems - Challenges and Trends.
Talk at Friday Workshop, Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures, Design, Automation and Test in Europe (DATE), Munich, Germany, March 10-14, 2008. ©1
280 D. Kissler, H. Dutta, A. Kupriyanov, F. Hannig and J. Teich.
A High-Speed Dynamic Reconfigurable Multilevel Parallel Architecture.
Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), Munich, Germany, March 10-14, 2008. ©1
279 M. Glaß, M. Lukasiewycz, F. Reimann, C. Haubelt and J. Teich.
Symbolic Reliability Analysis and Optimization of ECU Networks.
Proceedings of Design, Automation and Test in Europe (DATE 2008), IEEE Computer Society, pp. 158-163, Munich, Germany, March 10-14, 2008. ©1
278 M. Streubühr, M. Jäntsch, C. Haubelt, J. Teich and A. Schneider.
Semi-Automatic Generation of mixed Hardware-Software Prototypes from Simulink Models.
11. GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Freiburg, Germany, pp. 139-148, March 03-05, 2008. ©1
277 F. Hannig, H. Ruckdeschel and J. Teich.
The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications.
In Proceedings of the GI/ITG/GMM-Workshop - Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, pp. 129-138, Freiburg, Germany, March 3-5, 2008. ©1
276 J. Gladigau, F. Blendinger, C. Haubelt and J. Teich.
Symbolische Modellprüfung Aktor-orientierter High-level SystemC-Modelle mit Intervalldiagrammen.
11. GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Freiburg, Germany, pp. 109-118, March 03-05, 2008. ©1
275 T. Streichert, C. Haubelt, D. Koch and J. Teich.
Concepts for Self-Adaptive and Self-Healing Networked Embedded Systems.
Organic Computing, Rolf Würtz (Ed.), Springer Series Understanding Complex Systems, pp. 241-260, Springer, 2008. ©1
274 J. Keinert, C. Haubelt and J. Teich.
Synthesis of Multi-Dimensional High-Speed FIFOs for Out-of-Order Communication.
Proceedings of the International Conference on Architecture of Computing Systems (ARCS 2008), pp. 130-143, Dresden, Germany, February 25-28, 2008. ©1
273 R. Brendle, T. Streichert, D. Koch, C. Haubelt and J. Teich.
Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks.
Proceedings of the International Conference on Architecture of Computing Systems (ARCS 2008), pp. 117-129, Dresden, Germany, February 25-28, 2008. ©1
272 T. Streichert, M. Glaß, R. Wanka, C. Haubelt and J. Teich.
Topology-Aware Replica Placement in Fault-Tolerant Embedded Networks.
Proceedings of the International Conference on Architecture of Computing Systems (ARCS 2008), pp. 23-37, Dresden, Germany, February 25-28, 2008. ©1
271 S. Wildermann and J. Teich.
3D Person Tracking with a Color-Based Particle Filter.
G. Sommer and R. Klette (Eds.): RobVis 2008, LNCS 4931, pp. 327–340, Springer-Verlag Berlin Heidelberg, 2008. ©1
270 F. Hannig, H. Dutta, H. Ruckdeschel and J. Teich.
Quantitative Evaluation of Behavioral Synthesis Approaches for Reconfigurable Devices.
In Proceedings of the 2nd HiPEAC Workshop on Reconfigurable Computing (WRC), pp. 73-82, Gothenburg, Sweden, January 27, 2008. ©1
269 M. Lukasiewycz, M. Glaß, C. Haubelt and J. Teich.
Efficient Symbolic Multi–Objective Design Space Exploration.
In Proceedings of the 13th Asia and South Pacific Design Automation Conference (ASP-DAC 2008), pp. 691-696, Seoul, Korea. ©1
2007
268 D. Koch, C. Beckhoff and J. Teich.
Bitstream Decompression for High Speed FPGA Configuration from Slow Memories.
In Proceedings of the IEEE International Conference on Field-Programmable Technology 2007 (ICFPT'07), pp. 161-168. ©1
267 J. Falk, C. Haubelt and J. Teich.
Task Graph Clustering with Internal State.
Technical Report 01-2007, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, December 2007. ©1
266 J. Keinert, J. Falk, C. Haubelt and J. Teich.
Actor-Oriented Modeling and Simulation of Sliding Window Image Processing Algorithms.
Proceedings of the 2007 IEEE/ACM/IFIP Workshop of Embedded Systems for Real-Time Multimedia (ESTIMEDIA 2007), pp. 113-118, Salzburg, Oct. 4-5, 2007. ©1
265 T. Streichert, M. Glaß, C. Haubelt and J. Teich.
Design space exploration of reliable networked embedded systems.
In Journal on Systems Architecture (JSA). Volume 53(10): 751-763, 2007. ©1
264 M. Lukasiewycz, M. Glaß, C. Haubelt and J. Teich.
SAT-Decoding in Evolutionary Algorithms for Discrete Constrained Optimization Problems.
In Proceedings of the 2007 IEEE Congress on Evolutionary Computation (CEC 2007), Singapore, Singapore, pp. 935-942, September 25-28, 2007. ©1
263 D. Ziener and J. Teich.
Watermarking Apparatus, Software Enabling an Implementation of an Electronic Circuit Comprising a Watermark, Method for Detecting a Watermark and Apparatus for Detecting a Watermark.
US-Patent US2007/0220263, Anmeldetag 19.10.2006 aus EP 1835425, veröffentlicht 20.09.2007, Patentklassen (IPC) H04L 9/00. ©1
262 D. Ziener and J. Teich.
Watermarking apparatus, software enabling an implementation of an electronic circuit comprising a watermark, method for detecting a watermark and apparatus for detecting a watermark.
Europäisches Patent EP1835425, Anmeldetag 17.03.2006, veröffentlicht 19.09.2007, Patentklassen (IPC) G06F 17/50; G06F 21/00. ©1
261 J. Gladigau, C. Haubelt, B. Niemann and J. Teich.
Mapping Actor-Oriented Models to TLM Architectures.
In Proceedings FDL'07, Forum on specification and Design Languages 2007, Barcelona, Spain, September 18-20, 2007. ©1
260 D. Koch, T. Streichert, C. Haubelt and J. Teich.
Efficient Reconfigurable On-Chip Buses.
Europäisches Patent EP07017975, Anmeldetag 13.09.2007. ©1
259 J. Falk, J. Gladigau, C. Haubelt, J. Keinert, T. Schlichter, M. Streubühr and J. Teich.
Substantiating Early Design Decisions by Automatic Design Space Exploration.
Talk at 16. European SystemC Users Group Meeting, September 18, Barcelona, Spain, 2007. ©1
258 J. Teich.
Reconfigurable Computing Systems.
it - Information Technology, http://it-information-technology.de, Oldenbourg Wissenschaftsverlag, vol. 49(3):139-142, 2007. ©1
257 B. Niemann, C. Haubelt, M. Uribe and J. Teich.
Formalizing TLM with Communicating State Machines.
In Advances in Design and Specification Languages for Embedded Systems, pp. 225-242, Springer, 2007. ©1
256 J. Keinert, C. Haubelt and J. Teich.
Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow.
In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, Acoustics, Speech, and Signal Processing (IC-SAMOS VII), Samos (Greece) July 16-19, 2007. ©1
255 H. Dutta, F. Hannig, A. Kupriyanov, D. Kissler, J. Teich, R. Schaffer, S. Siegel, R. Merker and B. Pottier.
Massively Parallel Processor Architectures: A Co-design Approach.
Proceedings of the 3rd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC), pp. 61-68, Montpellier, France, June 18-20, 2007. ©1
254 J. Teich, F. Hannig, H. Ruckdeschel, H. Dutta, D. Kissler and A. Stravet.
A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation.
In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Invited paper, pp. 14-24, Las Vegas, NV, USA, June 25-28, 2007. ©1
253 W. Stechele, O. Bringmann, R. Ernst, A. Herkersdorf, K. Hojenski, P. Janacik, F. Rammig, J. Teich, N. Wehn, J. Zeppenfeld and D. Ziener.
Concepts for Autonomic Integrated Systems.
In Proceedings of edaWorkshop07, Hannover, Germany, June 19-20, 2007. ©1
252 H. Dutta, F. Hannig, H. Ruckdeschel and J. Teich.
Efficient Control Generation for Mapping Nested Loop Programs onto Processor Arrays.
In Journal of Systems Architecture, 53(5-6):300-309, 2007. ©1
251 M. Lukasiewycz, M. Glaß, C. Haubelt and J. Teich.
Solving Multiobjective Pseudo-Boolean Problems.
In Proceedings of Tenth International Conference on Theory and Applications of Satisfiability Testing (SAT 2007), Lisbon, Portugal, pp. 56-69, May 28-31, 2007. ©1
250 D. Koch, C. Haubelt, T. Streichert and J. Teich.
Modeling and Synthesis of Hardware-Software Morphing.
In Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), pp. 2746-2749, New Orleans, LA, U.S.A., May 2007. ©1
249 D. Kissler, F. Hannig and J. Teich.
Schwach-programmiert macht stark.
Design&Elektronik, April 2007, pp. 34-39, WEKA Fachzeitschriften-Verlag GmbH. ©1
248 A. Kupriyanov, D. Kissler, F. Hannig and J. Teich.
Efficient Event-driven Simulation of Parallel Processor Architectures.
In Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems (SCOPES), Nice, France, pp. 71-80, April 20, 2007. ©1
247 M. Glaß, M. Lukasiewycz, T. Streichert, C. Haubelt and J. Teich.
Reliability-Aware System Synthesis.
In Proceedings of Design, Automation and Test in Europe (DATE 2007), IEEE Computer Society, Nice, France, pp. 409-414, April 16-20, 2007. ©1
246 T. Streichert, C. Strengert, D. Koch, C. Haubelt and J. Teich.
Communication Aware Optimization of the Task Binding in Hardware/Software Reconfigurable Networks.
Journal on Integrated Circuits and Systems, Volume 2, Number 1, pp. 29-36, March 2007. ©1
245 M. Glaß, M. Lukasiewycz, T. Streichert, C. Haubelt and J. Teich.
Synthese zuverlässiger und flexibler Systeme.
In Proceedings of Zuverlässigkeit und Entwurf (ZuD 2007), Munich, Germany, pp. 141-148, March 26-28, 2007. ©1
244 W. Stechele, O. Bringmann, R. Ernst, A. Herkersdorf, K. Hojenski, P. Janacik, F. Rammig, J. Teich, N. Wehn, J. Zeppenfeld and D. Ziener.
Autonomic MPSoCs for Reliable Systems.
In Proceedings of Zuverlässigkeit und Entwurf (ZuD 2007), pp. 137-138, Munich, Germany, March 26-28, 2007. ©1
243 S. Fekete, J. van der Veen, J. Angermeier, D. Göhringer, M. Majer and J. Teich.
Scheduling and communication-aware mapping of HW-SW modules for dynamically and partially reconfigurable SoC architectures.
In Proceedings of the Dynamically Reconfigurable Systems Workshop (DRS 2007), Zürich, Switzerland, pages 151-160, March 15, 2007. ©1
242 A. Kupriyanov, F. Hannig, D. Kissler, J. Teich, J. Lallet, O. Sentieys and S. Pillement.
Modeling of Interconnection Networks in Massively Parallel Processor Architectures.
In Proceedings of the 20th International Conference on Architecture of Computing Systems (ARCS 2007), Springer LNCS series, Swiss Federal Institute of Technology (ETH), Zurich, Switzerland, pp. 268-282, March 12-15, 2007. ©1
241 J. Angermeier, D. Göhringer, M. Majer and J. Teich.
The Erlangen Slot Machine: A flexible FPGA-platform for partially reconfigurable applications at run-time.
Tutorial, 20th International Conference on Architecture of Computing Systems (ARCS 2007), Springer LNCS series, Swiss Federal Institute of Technology (ETH) Zurich, Switzerland, March 12-15, 2007. ©1
240 M. Lukasiewycz, M. Glaß, C. Haubelt and J. Teich.
Symbolic Archive Representation for a Fast Nondominance Test.
In Proceedings of the Fourth International Conference on Evolutionary Multi-Criterion Optimization (EMO 2007), Sendai, Japan, pp. 111-125, March 5-8, 2007. ©1
239 M. Streubühr, C. Riedel, C. Haubelt and J. Teich.
System Level Modeling and Performance Simulation for Dynamic Reconfigurable Computing Systems in SystemC.
10. Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen", Erlangen, Germany, pp. 59-68, March 05-07, 2007. ©1
238 J. Teich and C. Haubelt.
Digitale Hardware/Software-Systeme: Synthese und Optimierung.
2. Auflage, Springer-Verlag, Berlin Heidelberg, 2007. ©1
237 M. Majer, J. Teich, A. Ahmadinia and C. Bobda.
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-Based Computer.
Journal of VLSI Signal Processing Systems, Springer, vol. 47(1), pages 15-31, March 2007. ©1
236 C. Haubelt, J. Falk, J. Keinert, T. Schlichter, M. Streubühr, A. Deyhle, A. Hadert and J. Teich.
A SystemC-based Design Methodology for Digital Signal Processing Systems.
In EURASIP Journal on Embedded Systems, Special Issue on Embedded Digital Signal Processing Systems, Volume 2007 (2007), Article ID 47580, 22 pages, March 2007. ©1
235 C. Haubelt and J. Teich.
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen.
Shaker Verlag, Aachen, Germany, 2007. ©1
234 D. Koch, C. Haubelt and J. Teich.
Efficient Hardware Checkpointing -- Concepts, Overhead Analysis, and Implementation.
In Proceedings of the 15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2007), Monterey, CA, pp. 188-196, February 18-20, 2007.
Download demo video. ©1
233 N. Bergmann, M. Platzner and J. Teich.
Dynamically Reconfigurable Architectures.
EURASIP Journal of Embedded Systems, Volume 2007 (2007), Article ID 28405, 2 pages, February 2007. ©1
232 J. Teich.
Evaluation and Optimization of Reliability of Embedded Systems during Design Space Exploration.
Dagstuhl Seminar No. 07101, Quantitative Aspects of Embedded Systems, IBFI, March 5-9, 2007. ©1
231 J. Angermeier, D. Göhringer, M. Majer, J. Teich, S. Fekete and J. van der Veen.
The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Reconfigurable Computing.
it - Information Technology, http://it-information-technology.de, Oldenbourg Wissenschaftsverlag, vol. 49(3):143-148, 2007. ©1
230 A. Ahmadinia, C. Bobda, S. Fekete, J. Teich and J. van der Veen.
Optimal free-space management and routing-conscious dynamic placement for reconfigurable computing.
IEEE Transactions on Computers, volume 56, number 3, pages 673-680, 2007. ©1
2006
229 D. Ziener and J. Teich.
FPGA Core Watermarking Based on Power Signature Analysis.
In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2006), pp. 205-212, Bangkok, Thailand, December 13-15, 2006. ©1
228 D. Kissler, F. Hannig, A. Kupriyanov and J. Teich.
A Highly Parameterizable Parallel Processor Array Architecture.
In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT 2006), pp. 105-112, Bangkok, Thailand, December 13-15, 2006. ©1
227 J. Falk, J. Gladigau, C. Haubelt and J. Teich.
SysteMoC - Verification and Refinement of Actor-Based Models of Computation.
Talk, ARTIST2 Workshop on MoCC - Models of Computation and Communication, November 16-17, Zurich, Switzerland, 2006. ©1
226 D. Kissler, F. Hannig, A. Kupriyanov and J. Teich.
Hardware Cost Analysis for Weakly Programmable Processor Arrays.
In Proceedings of the International Symposium on System-on-Chip (SoC), pp. 179-182, Tampere, Finland, November 14-16, 2006. ©1
225 S. Siegel, R. Merker, F. Hannig and J. Teich.
Communication-conscious Mapping of Regular Nested Loop Programs onto Massively Parallel Processor Arrays.
In Proceedings of the 18th International Conference on Parallel and Distributed Computing and Systems (PDCS), pp. 71-76, Dallas, TX, USA, November 13-15, 2006. ©1
224 J. Teich.
Are Current ESL Tools Meeting the Requirements of Advanced Embedded Systems?.
In Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), p. 166, Seoul, Korea, October 22-25, 2006. ©1
223 T. Streichert, D. Koch, C. Haubelt and J. Teich.
Modeling and Design of Fault-Tolerant and Self-Adaptive Reconfigurable Networked Embedded Systems.
EURASIP Journal on Embedded Systems, Volume 2006 (2006), Article ID 42168, 15 pages, Hindawi Publishing Corporation. ©1
222 J. Falk, C. Haubelt and J. Teich.
Efficient Representation and Simulation of Model-Based Designs in SystemC.
In Proceedings FDL'06, Forum on Design Languages 2006, Darmstadt, Germany, September 19-22, pp. 129 - 134, 2006. ©1
221 H. Dutta, F. Hannig and J. Teich.
Hierarchical Partitioning for Piecewise Linear Algorithms.
In Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering (PARELEC), pp. 153-159, Bialystok, Poland, September 13-17, 2006. ©1
220 H. Dutta, F. Hannig, J. Teich, B. Heigl and H. Hornegger.
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing.
In Proceedings of IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 331-337, Steamboat Springs, CO, USA, September 11-13, 2006. ©1
219 D. Ziener, S. Aßmus and J. Teich.
Identifying FPGA IP-Cores based on Lookup Table Content Analysis.
In Proceedings of 16th International Conference on Field Programmable Logic and Applications, Madrid, Spain, pp. 481-486, August 28-30, 2006. ©1
218 T. Streichert, C. Strengert, C. Haubelt and J. Teich.
Dynamic Task Binding for Hardware/Software Reconfigurable Networks .
In Proceedings of SBCCI 2006, pages 38-43, Ouro Preto, Brasil, August 28th - September 1st, 2006. ©1
217 J. Teich, S. Kaxiras, T. Plaks and K. Flautner.
Topic 18: Embedded Parallel Systems.
In Proceedings of12th International Euro-Par Conference, p. 1179, Dresden, Germany, August 28-September 1, 2006. ©1
216 S. Fekete, J. van der Veen, M. Majer and J. Teich.
Minimizing communication cost for reconfigurable slot modules.
In Proceedings 16th International Conference on Field-Programmable Logic and Applications (FPL 2006), pp. 535-540, Madrid, Spain, August 28-30, 2006. ©1
215 A. Kupriyanov, F. Hannig, D. Kissler, J. Teich, J. Lallet, O. Sentieys and S. Pillement.
Modeling of Interconnection Networks in Massively Parallel Processor Architectures.
Technical Report 05-2006, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, August 2006. ©1
214 S. Fekete, E. Köhler and J. Teich.
Higher-dimensional packing with order constraints.
SIAM Journal on Discrete Mathematics,Vol. 20, No. 4, pp. 1056-1078, 2006. ©1
213 T. Streichert, C. Haubelt and J. Teich.
Multi-Objective Topology Optimization for Networked Embedded Systems.
In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2006), pp. 93--98, Samos (Greece), July 17-20, 2006.. ©1
212 D. Kissler, F. Hannig, A. Kupriyanov and J. Teich.
A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template.
In Proceedings of the 2nd International Workshop on Reconfigurable Communication-Centric System-on-Chips (ReCoSoC), pp. 31-37, France, July 3-5, 2006. ©1
211 D. Göhringer, M. Majer and J. Teich.
Bridging the Gap between Relocation and Available Technology: The Erlangen Slot Machine.
In Proceedings of the Dagstuhl Seminar Nº 06141 on Dynamically Reconfigurable Architectures, P. M. Athanas, J. Becker, G. Brebner, J. Teich (Eds.), ISSN 1862 - 4405, Dagstuhl, Germany, April 02-07, 2006. ©1
210 D. Kissler, A. Kupriyanov, F. Hannig, D. Koch and J. Teich.
A Generic Framework for Rapid Prototyping of System-on-Chip Designs.
In Proceedings of the International Conference on Computer Design (CDES), pp. 189-195, Las Vegas, NV, USA, June 2006. ©1
209 D. Koch, M. Körber and J. Teich.
Searching RC5-Keys with Distributed Reconfigurable Computing.
In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA 2006), Las Vegas, USA, June 26-29, 2006. ©1
208 F. Hannig, H. Dutta and J. Teich.
Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays: Architectural Parameters and Methodology.
In International Journal of Embedded Systems, Vol. 2, Nos. 1/2, pp. 114-127, 2006. ©1
207 J. Teich and S. Bhattacharyya.
Analysis of Dataflow Programs with Interval-limited Data-rates.
In Journal of VLSI Signal Processing, Vol. 43, Nos. 2-3, pp. 247-258, 2006. ©1
206 C. Haubelt, T. Schlichter and J. Teich.
Improving Automatic Design Space Exploration by Integrating Symbolic Techniques into Multi-Objective Evolutionary Algorithms.
In International Journal of Computational Intelligence Research (IJCIR), Special Issue on Multiobjective Optimization and Applications, Volume 2, Issue 3. pp. 239-254, 2006. ©1
205 A. Ahmadinia, C. Bobda and J. Teich.
Online Placement for Dynamically Reconfigurable Devices.
Int. J. Embedded Systems, Vol. 1, Nos. 3/4, pp.165-178, 2006. ©1
204 J. Keinert, C. Haubelt and J. Teich.
Modeling and Analysis of Windowed Synchronous Algorithms.
In Proceedings of the 31st International Conference on Acoustics, Speech, and Signal Processing (ICASSP2006), Toulouse (France) May 14-19, 2006. ©1
203 H. Dutta, F. Hannig and J. Teich.
A Formal Methodology for Hierarchical Partitioning of Piecewise Linear Algorithms.
Technical Report 04-2006, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, April 2006. ©1
202 J. Becker, J. Teich, P. Athanas and G. Brebner.
Dynamically Reconfigurable Architectures.
Proceedings of the Dagstuhl Seminar Nº 06141, ISSN 1862 - 4405, Dagstuhl, Germany, April 02-07, 2006. ©1
201 M. Majer, A. Ahmadinia, C. Bobda and J. Teich.
A Flexible Reconfiguration Manager for the Erlangen Slot Machine.
In Proceedings of the Dynamically Reconfigurable Systems Workshop (DRS'2006), Frankfurt/Main, Germany, pp.183-194, March 16, 2006. ©1
200 A. Kupriyanov, F. Hannig, D. Kissler, R. Schaffer and J. Teich.
MAML - An Architecture Description Language for Modeling and Simulation of Processor Array Architectures, Part I.
Technical Report 03-2006, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, March 2006. ©1
199 D. Koch, T. Streichert, S. Dittrich, C. Strengert, C. Haubelt and J. Teich.
An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks.
In Proceedings of the 19th International Conference on Architecture of Computing Systems (ARCS 2006), Frankfurt/Main, Germany, pp. 202-216, March 13-16, 2006. ©1
198 H. Dutta, F. Hannig and J. Teich.
Controller Synthesis for Mapping Partitioned Programs on Array Architectures.
In Proceedings of the 19th International Conference on Architecture of Computing Systems (ARCS), Frankfurt/Main, Germany, pp. 176-191, March 13-16, 2006. ©1
197 J. Teich, C. Haubelt, D. Koch and T. Streichert.
Concepts for Self-Adaptive Automotive Control Architectures.
DATE'06 Friday Workshop Future Trends in Automotive Electronics and Tool Integration, Conference Design Automation and Test in Europe, March 10, 2006, Munich, Germany. ©1
196 C. Bobda, M. Platzner and J. Teich.
The Renaissance of FPGA-Based High-Performance Computing.
DATE'06 Friday Workshop, Conference Design Automation and Test in Europe, March 10, 2006, Munich, Germany. ©1
195 M. Streubühr, J. Falk, C. Haubelt, J. Teich, R. Dorsch and T. Schlipf.
Task-Accurate Performance Modeling in SystemC for Real-Time Multi-Processor Architectures.
In Proceedings of Design, Automation and Test in Europe (DATE 2006), IEEE Computer Society, Munich, Germany, pp. 480-481, March 6-10, 2006. ©1
194 T. Schlichter, M. Lukasiewycz, C. Haubelt and J. Teich.
Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms.
In Proceedings of IEEE Computer Society Annual Symposium on VLSI. Karlsruhe, Germany, pp. 309-314, March 2-3, 2006. ©1
193 A. Kupriyanov, F. Hannig, D. Kissler, J. Teich, R. Schaffer and R. Merker.
An Architecture Description Language for Massively Parallel Processor Architectures.
In Proceedings of the 9th ITG/GMM/GI Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Dresden, Germany, pp. 11-20, February 20-22, 2006. ©1
192 H. Dutta, F. Hannig and J. Teich.
Mapping of Nested Loop Programs onto Massively Parallel Processor Arrays with Memory and I/O Constraints.
In Friedhelm Meyer auf der Heide and Burkhard Monien, editors, Proceedings of the 6th International Heinz Nixdorf Symposium, New Trends in Parallel & Distributed Computing, volume 181 of HNI-Verlagsschriftenreihe, pp. 97-119, Paderborn, Germany, January 17-18, 2006. ©1
191 J. Teich.
Timing Analysis of Systems of Communicating Tasks with Internal State.
Technical Report 01-2006, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, January 2006. ©1
190 J. Teich.
Stochastic Timing Analysis of Communicating Tasks with Internal State.
Technical Report 02-2006, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, January 2006. ©1
2005
189 J. Falk, C. Haubelt and J. Teich.
Syntax and execution behavior of SysteMoC.
Technical Report 04-2005, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, December 2005. ©1
188 A. Ahmadinia, C. Bobda, T. Haller, A. Linarth, M. Majer and J. Teich.
Increasing the Flexibility in FPGA-Based Reconfigurable Platforms: The Erlangen Slot Machine.
In Proc. IEEE 2005 Conference on Field-Programmable Technology (FPT), Singapore, Singapore, pages 37-42, December 11-14, 2005. ©1
187 H. Dutta, F. Hannig and J. Teich.
Control Path Generation for Mapping Partitioned Dataflow-dominant Algorithms onto Array Architectures.
Technical Report 03-2005, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, November 2005. ©1
186 J. Keinert, C. Haubelt and J. Teich.
Windowed Synchronous Data Flow.
Department of Computer Science 12, Hardware-Software-Co-Design, University of Erlangen-Nuremberg, Am Weichselgarten 3, D-91058 Erlangen, Germany Co-Design-Report 02-2005. ©1
185 A. Ahmadinia, C. Bobda, J. Ding, M. Majer and J. Teich.
Modular Video Streaming on a Reconfigurable Platform.
In Proc. IFIP VLSI SOC 2005, pages 103-108, Perth, Australia, pp. 103-108, October 17-19, 2005. ©1
184 C. Haubelt, M. Jersak, K. Richter, K. Strehl, D. Ziegenbein, R. Ernst, J. Teich and L. Thiele.
SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme.
In Proceedings of INFORMATIK 2005 - Informatik LIVE. by Armin B. Cremers, Rainer Manthey, Peter Martini, and Volker Steinhage (Eds.). In Lecture Notes in Informatics. VOL. P-68, No. 2, Bonn, Germany, pp. 693-697, September 19-22, 2005. © Gesellschaft für Informatik, Bonn, Germany, 2005. ©1
183 S. Helwig, C. Haubelt and J. Teich.
Modeling and Analysis of Indirect Communication in Particle Swarm Optimization.
In Proceedings of the 2005 IEEE Congress on Evolutionary Computation, volume 2, pages 1246-1253, Edinburgh, UK, September 2nd-5th, 2005. ©1
182 A. Ahmadinia, C. Bobda, S. Fekete, M. Majer, J. Teich and J. van der Veen.
DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices.
In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL),Tampere, Finland, pp. 153-158, August 24-26, 2005. ©1
181 T. Schlichter, C. Haubelt, F. Hannig and J. Teich.
Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems.
In Proceedings of Application-specific Systems, Architectures and Processors (ASAP). Samos, Greece, pp. 9-14, July 23-25, 2005. ©1
180 H. Ruckdeschel, H. Dutta, F. Hannig and J. Teich.
Automatic FIR Filter Generation for FPGAs.
In Proceedings of the International Workshop on Embedded Computer Systems, Architectures, Modeling, and Simulation (SAMOS), Samos, Greece, pp. 51-61, July 18-20, 2005. ©1
179 F. Hannig and J. Teich.
Output Serialization for FPGA-based and Coarse-grained Processor Arrays.
In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, USA, pp. 78-84, June 27-30, 2005. ©1
178 F. Hannig, H. Dutta, A. Kupriyanov, J. Teich, R. Schaffer, S. Siegel, R. Merker, R. Keryell, B. Pottier and D. Chillet, D. Ménard, O. Sentieys.
Co-Design of Massively Parallel Embedded Processor Architectures.
In Proceedings of the first ReCoSoC Workshop. Montpellier, France, June 27-29, 2005. ©1
177 A. Ahmadinia, C. Bobda, S. Fekete, F. Hannig, M. Majer, J. Teich and J. van der Veen.
Defragmenting the Module Layout of a Partially Reconfigurable Device.
In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, USA, pp. 92-101, June 27-30, 2005. ©1
176 T. Schlichter, C. Haubelt and J. Teich.
Improving EA-based Design Space Exploration by Utilizing Symbolic Feasibility Tests.
In Proceedings of Genetic and Evolutionary Computation Conference (GECCO). Washington, DC, pp. 1945-1952, June 25-29, 2005. ©1
175 A. Ahmadinia, C. Bobda, J. Ding, S. Fekete, M. Majer, J. Teich and J. van der Veen.
A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices.
In Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping, Montreal, Canada, pp. 84-90, June 8-10, 2005. ©1
174 S. Mostaghim and J. Teich.
Quad-trees: A Data structure for storing Pareto-sets in Multi-objective Evolutionary Algorithms with Elitism.
In Ajith Abraham and Lakhmi Jain and Robert Goldberg (eds.), Evolutionary Multiobjective Optimization, Theoretical Advances and Applications. Springer Advanced Information and Knowledge Processing Series, London, pp. 81-104, 2005. ©1
173 A. Ahmadinia, C. Bobda, S. Fekete, T. Haller, A. Linarth, M. Majer, J. Teich and J. van der Veen.
The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform.
In Proceedings of the 2005 IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, USA, pp. 319-320, April 17-20, 2005. ©1
172 T. Dinkel, C. Haubelt, U. Heinkel, J. Knäblein, T. Schlichter, S. Schock and J. Teich.
Comparison of Techniques for the Automatic Verification of ADeVA Specifications.
In Dresdener Arbeitstagung Schaltungs- und Systementwurf (DASS 2005). Dresden, Germany, April 13-14, 2005. ©1
171 T. Dinkel, C. Haubelt, U. Heinkel, T. Schlichter and J. Teich.
Automatische Verification von ADeVA-Spezifikationen.
In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen. GI/ITG/GMM-Workshop 2005, Munich, Germany, April 06-07, 2005. ©1
170 J. Falk, C. Haubelt and J. Teich.
Representing Models of Computation in SystemC.
GI/ITG/GMM-Workshop 2005, Munich, Germany, April 06-07, 2005. ©1
169 A. Ahmadinia, C. Bobda, M. Majer and J. Teich.
Packet Routing in Dynamically Changing Networks on Chip.
In Proceedings of the 12th Reconfigurable Architectures Workshop (RAW 2005), Denver, USA, p. 154b, IEEE Computer Society, April 4-5, 2005. ©1
168 J. Teich.
Model-Based System-Level Design Using SystemC.
Invited talk, Akademische Tage'05, IBM Forschungslaboratorium, March 18, 2005, Böblingen, Germany. ©1
167 J. Teich.
The Future of Reconfigurable Computing.
DATE'05 Friday Workshop, Conference Design Automation and Test in Europe, March 11, 2005, Munich, Germany. ©1
166 A. Ahmadinia, C. Bobda, T. Haller, A. Linarth, M. Majer and J. Teich.
The Erlangen Slot Machine (ESM): A Flexible Platform for Dynamic Reconfigurable Computing.
Board Demo at the University Booth at Design, Automation and Test in Europe (DATE 2005), Munich, Germany, March 7-11, 2005. ©1
165 C. Haubelt, J. Gamenik and J. Teich.
Initial Population Construction for Convergence Improvement of MOEAs.
In Evolutionary Multi-Criterion Optimization, Carlos A. Coello Coello, Arturo Hernández Aguirre, and Eckart Zitzler (eds.), Lecture Notes in Computer Science, Vol. 3410, pp. 191-205, Springer, Berlin, Heidelberg, New York, 2005. ©1
164 T. Streichert, C. Haubelt and J. Teich.
Distributed HW/SW-Partitioning for Embedded Reconfigurable Systems.
In Proceedings of DATE 2005, Munich, Germany, pp. 894-895, March 7-11, 2005. ©1
163 D. Ziener and J. Teich.
Evaluation of Watermarking methods for FPGA-based IP-cores.
Technical Report 01-2005, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, March 2005. ©1
162 T. Streichert, C. Haubelt and J. Teich.
Verteilte HW/SW-Partitionierung für fehlertolerante rekonfigurierbare Netzwerke.
In Proceedings of 17. ITG/GI/GMM Workshop für Testmethoden und Zuverlässigkeit und Fehlertoleranz von Schaltungen und Systemen. Innsbruck, Austria, pp. 50-54, February 27 - March 1, 2005. ©1
161 C. Haubelt, S. Otto, C. Grabbe and J. Teich.
A System-Level Approach to Hardware Reconfigurable Systems.
In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC'05). Shanghai, China, pp. 298-301, January 18-21, 2005. ©1
160 T. Streichert, C. Haubelt and J. Teich.
Online Hardware/Software Partitioning in Networked Embedded Systems.
In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC'05). Shanghai, China, pp. 982-985, January 18-21, 2005. ©1
2004
159 A. Ahmadinia, C. Bobda, H. Kalte, D. Koch and J. Teich.
FPGA Architecture Extensions for Preemptive Multitasking and Hardware Defragmentation.
In Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology (FPT), Brisbane, Australia, pp. 433-436, December 6-8, 2004. ©1
158 A. Ahmadinia, C. Bobda, J. Ding and J. Teich.
Design and Implementation of Reconfigurable Multiple Bus on Chip (RMBoC).
Technical Report 02-2004, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, November 2004. ©1
157 S. Mostaghim and J. Teich.
Multi-Objective Particle Swarm Optimization.
Dagstuhl Seminar No. 04461, Practical Approaches to Multi-Objective Optimization, IBFI, November 7 - 12, 2004. ©1
156 F. Hannig and J. Teich.
Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals.
In Proceedings of the 15th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2004), pp. 17-27, Galveston, TX, USA, September 27-29, 2004. ©1
155 A. Kupriyanov, F. Hannig and J. Teich.
Automatic and Optimized Generation of Compiled High-Speed RTL Simulators.
In Proceedings of the Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES 2004). Washington, DC, U.S.A., September 22, 2004. ©1
154 F. Hannig and J. Teich.
Dynamic Piecewise Linear/Regular Algorithms.
In Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), pp. 79-84, Dresden, Germany, September 7-10, 2004. ©1
153 A. Ahmadinia, C. Bobda, D. Koch, M. Majer and J. Teich.
Task Scheduling for Heterogeneous Reconfigurable Computers.
In Proceedings of the 17th Symposium on Integrated Circuits and Systems Design (SBCCI), Pernambuco, Brazil, pp. 22-27, ACM Press, September 7-11, 2004. ©1
152 A. Ahmadinia, C. Bobda, D. Koch, M. Majer and J. Teich.
A Dynamic NoC Approach for Communication in Reconfigurable Devices.
In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL), Antwerp, Belgium, LNCS 3203, pp. 1032-1036, Springer, August 30 - September 1, 2004. ©1
151 A. Ahmadinia, C. Bobda, S. Fekete, J. Teich and J. van der Veen.
Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices.
In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL), Antwerp, Belgium, LNCS 3203, pp. 847-851, Springer, August 30 - September 01, 2004. ©1
150 C. Haubelt, D. Koch and J. Teich.
Basic OS Support for Distributed Reconfigurable Hardware.
In Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04), Samos, Greece, July 19-21, published as Springer Lecture Notes in Computer Science (LNCS), volume 3133, pages 30-38, 2004. ©1
149 N. Bambha, S. Bhattacharyya, J. Teich and E. Zitzler.
Systematic Integration of Parameterized Local Search Into Evolutionary Algorithms.
IEEE Transactions on Evolutionary Computation, vol. 8, no. 2, pages 137-155, April 2004. ©1
148 A. Kupriyanov, F. Hannig and J. Teich.
High-Speed Event-Driven RTL Compiled Simulation.
In Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04), Samos, Greece, July 19-21, published as Springer Lecture Notes in Computer Science (LNCS), volume 3133, pages 519-529, 2004. ©1
147 S. Bhattacharyya and J. Teich.
Analysis of Dataflow Programs with Interval-Limited Data-Rates.
In Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04), Samos, Greece, July 19-21, published as Springer Lecture Notes in Computer Science (LNCS), volume 3133, pages 507-518, 2004. ©1
146 N. Bambha, S. Bhattacharyya, J. Teich and E. Zitzler.
Systematic Integration of Parameterized Local Search Techniques in Evolutionary Algorithms.
In Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '04), Part II, pp. 383-384, Seattle, U.S.A., June 26-30, 2004. ©1
145 S. Mostaghim and J. Teich.
Covering Pareto-optimal Fronts by Subswarms in Multi-objective Particle Swarm Optimization.
In Proceedings of the Congress on Evolutionary Computation (CEC '04), pp. 1404-1411, Portland, U.S.A., June 20-23, 2004. ©1
144 T. Frauenheim, M. Hoffman, P. Koenig, S. Mostaghim and J. Teich.
Molecular Force Field Parameterization using Multi-Objective Evolutionary Algorithms.
In Proceedings of the Congress on Evolutionary Computation (CEC '04), pp. 212-219, Portland, U.S.A., June 20-23, 2004. ©1
143 F. Hannig and J. Teich.
Resource Constrained and Speculative Scheduling of Dynamic Piecewise Regular Algorithms.
Technical Report 01-2004, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, June 2004. ©1
142 F. Hannig, H. Dutta and J. Teich.
Regular Mapping for Coarse-grained Reconfigurable Architectures.
In Proceedings of the 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2004), Vol. V, pp. 57-60, Montréal, Quebec, Canada, May 17-21, 2004. ©1
141 F. Hannig, H. Dutta and J. Teich.
Mapping of Regular Nested Loop Programs to Coarse-grained Reconfigurable Arrays -- Constraints and Methodology.
In Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), Santa Fe, NM, USA, April 26-30, 2004. ©1
140 A. Ahmadinia, M. Bednara, C. Bobda and J. Teich.
A New Approach for On-line Placement on Reconfigurable Devices.
In Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), Santa Fe, NM, U.S.A., April 26-30, 2004. ©1
139 C. Haubelt and J. Teich.
Modeling and Analysis of Distributed Reconfigurable Hardware.
In Dresdener Arbeitstagung Schaltungs- und Systementwurf (DASS 2004), pp. 106-111, Dresden, Germany, April 19-20, 2004. ©1
138 D. Koch and J. Teich.
Platform-Independent Methodology for Partial Reconfiguration.
Proceedings of the 2004 ACM conference Computing Frontiers (CF 04), pp. 398-403, April 14-16, 2004, Ischia, Italy. ©1
137 A. Ahmadinia, C. Bobda, K. Danne and J. Teich.
Generation of Distributed Arithmetic Designs for Reconfigurable Applications.
In Proc. GI/ITG Dynamically Reconfigurable Systems Workshop at ARCS - Organic and Pervasive Computing, Augsburg, Germany, pp. 205-214, March 26, 2004. ©1
136 A. Ahmadinia, C. Bobda and J. Teich.
A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware.
In Proc. 17th International Conference on Architecture of Computing Systems (ARCS 2004), Augsburg, Germany, LNCS 2981, pp. 125-139, Springer, March 23-26, 2004. ©1
135 A. Kupriyanov, F. Hannig, J. Teich, D. Fischer, M. Thies and R. Weper.
ArchitectureComposer.
CAD Software Demo at the University Booth at Design, Automation and Test in Europe (DATE 2004), Paris, France, February 16-20, 2004. ©1
134 F. Hannig and J. Teich.
Energy Estimation and Optimization for Piecewise Regular Processor Arrays.
In Shuvra S. Bhattacharyya, Ed F. Deprettere and Jürgen Teich (eds.). Chapter 6 in Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation, pages 107-126. Number 20 in Signal Processing and Communication Series, Marcel Dekker, New York, U.S.A., 2004. ©1
2003
133 A. Ahmadinia, C. Bobda, K. Danne and J. Teich.
A New Approach for Reconfigurable Massively Parallel Computers.
In Proceedings of the IEEE International Conference on Field-Programmable Technology, Tokyo, Japan, pp. 391-394, December 15-17, 2003. ©1
132 A. Ahmadinia, C. Bobda and J. Teich.
Temporal Task Clustering for Online Placement on Reconfigurable Hardware.
In Proceedings of the IEEE International Conference on Field-Programmable Technology, Tokyo, Japan, pp. 359-362, December 15-17, 2003. ©1
131 A. Ahmadinia and J. Teich.
Speeding up Online Placement for XILINX FPGAs by Reducing Configuration Overhead .
In Proceedings of the IFIP International Conference on VLSI-SOC, Darmstadt, Germany, pp. 118-122, December 1-3, 2003. ©1
130 C. Haubelt and J. Teich.
Accelerating Design Space Exploration.
In Proceedings of 5th International Conference on ASIC (ASICON 2003), pp. 79-84, Beijing, China, October 21-24, 2003. ©1
129 P. Kralicek, C. Reinhold and J. Teich.
Synthesizing Passive Networks by applying Genetic Programming and Evolution Strategies.
In Proceedings of the Congress on Evolutionary Computation (CEC'03), pp. 1740-1747, Canberra, Australia, December 8-12, 2003. ©1
128 S. Mostaghim and J. Teich.
The role of e-dominance in Multi-Objective Particle Swarm Optimization Methods.
In Proceedings of the Congress on Evolutionary Computation (CEC'03), pp.1764-1771, Canberra, Australia, December 8-12, 2003 . ©1
127 C. Haubelt, D. Koch and J. Teich.
ReCoNets: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware.
In Proceedings of the 16th Symposium on Integrated Circuits and Systems Design (SBCCI2003), pp. 343-348, São Paulo, Brazil, September 8-11, 2003. ©1
126 R. Feldmann, C. Haubelt, B. Monien and J. Teich.
Fault Tolerance Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques.
In Proceedings of 13th International Conference on Field Programmable Logic and Applications, pp. 478-487, Lisbon, Portugal, September 1-3, 2003. ©1
125 C. Haubelt, D. Koch and J. Teich.
Basic OS Support for Distributed Reconfigurable Hardware.
In Proceedings of the Third International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'03), pp. 18-22, Samos, Greece, July 21-23, 2003, ISBN 90-807957-1-2. ©1
124 J. Teich.
ReCoNets - Networks of Reconfigurable Nodes and Interconnect.
Dagstuhl Seminar No. 03301, Dynamically Reconfigurable Architectures, IBFI, Germany, July 2003. ©1
123 M. Bednara, C. Grabbe, J. Shokrollahi, J. Teich and J. von zur Gathen.
FPGA Designs of Parallel High Performance GF(2^233) Multipliers.
In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS-2003), pp. 268-271, Bangkok, Thailand, May 25-28, 2003. ©1
122 S. Mostaghim and J. Teich.
Strategies for finding good local guides in multi-objective particle swarm optimization.
In Proceedings of the Swarm Intelligence Symposium, pp. 26-33, Indianapolis, USA, April 24-26, 2003. ©1
121 M. Bednara, C. Grabbe, J. Shokrollahi, J. Teich and J. von zur Gathen.
A High Performance VLIW Processor for Finite Field Arithmetic.
In Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS-2003),p. 189, Nice, France, April 22-26, 2003. ©1
120 M. Bednara and J. Teich.
Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms.
Journal of Supercomputing, Vol. 26, No., 2, pp. 149-165, September 2003. ©1
119 D. Fischer, J. Teich, M. Thies and R. Weper.
Buildabong: A Framework for Architecture/Compiler Co-Exploration .
Journal of Circuits, Systems, and Computers, Vol. 12, No. 3, pp. 353-375, World Scientific Publishing Company, June 2003. ©1
118 M. Bednara, K. Danne, M. Deppe, F. Oberschelp, F. Slomka and J. Teich.
Design and Implementation of Digital Linear Control Systems on Reconfigurable Hardware.
EURASIP Journal of Applied Signal Processing, Vol. 2003, Number 6, pp. 1-9, Hindawi Publishing Corporation, 2003. ©1
117 M. Dellnitz, S. Mostaghim, O. Schütze and J. Teich.
Covering Pareto Sets by Multilevel Evolutionary Subdivision Techniques.
In Proceedings of the Second International Conference on Evolutionary Multi-Criterion Optimization (EMO), pp. 118-132, Faro, Portugal, April 8-11, 2003. ©1
116 J. Teich.
Challenges and Potentials of Reconfigurable Computing.
6th German-American Frontiers of Engineering Symposium, Alexander von Humboldt-Foundation, U.S. National Academy of Engineering, Ludwigsburg, Germany, April 2003. ©1
115 C. Haubelt, S. Mostaghim, J. Teich and A. Tyagi.
Solving Hierarchical Optimization Problems Using MOEAs.
In Evolutionary Multi-Criterion Optimization, Carlos M. Fonseca, Peter J. Fleming, Eckart Zitzler, Kalyanmoy Deb, and Lothar Thiele (eds.), Lecture Notes in Computer Science, Vol. 2632, pp. 162-176, Springer, Berlin, Heidelberg, New York, 2003. ©1
114 C. Haubelt, S. Mostaghim, F. Slomka, J. Teich and A. Tyagi.
Hierachical Synthesis of Embedded Systems Using Evolutionary Algorithms.
In Evolutionary Algorithms in System Design by Drechsler, R. and Drechsler, N., in Genetic Algorithms and Evolutionary Computation (GENA), pp. 63-104, Kluwer Academic Publishers, Boston, Dordrecht, London, 2003. ©1
113 J. Gerling, G. Mrozynski, J. Schrage, O. Stuebbe and J. Teich.
Improved time domain simulation of optical multimode intrasystem interconnects.
In Proceedings of Design, Automation and Test in Europe (DATE 2003), Messe Munich, Germany, pp. 1110-1111, March 3-7, 2003. ©1
112 C. Haubelt, J. Teich, R. Feldmann and B. Monien.
SAT-Based Techniques in System Synthesis.
In Proceedings of Design, Automation and Test in Europe (DATE 2003), Norbert Wehn and Diederik Verkest, IEEE Computer Society, Munich, Germany, pp. 1168-1169, March 3-7, 2003. ©1
111 F. Slomka and J. Teich.
A Model for Buffer Exploration in EDF Scheduled Embedded Systems.
11. EIS-Workshop, Entwurf Integrierter Schaltungen und Systeme, Erlangen, Germany. VDE/VDI-Gesellschaft Mikroelektronik, Mikro- und Feinwerktechnik (GMM), GMM-Fachbericht, pp. 91-96, VDE-Verlag, Berlin, März 2003. ©1
110 J. Teich.
Entwurfsautomatisierung elektronischer Systeme auf Systemebene.
11. EIS-Workshop, Entwurf Integrierter Schaltungen und Systeme, VDE/VDI-Gesellschaft Mikroelektronik, Mikro- und Feinwerktechnik (GMM), GMM-Fachbericht, VDE-Verlag, Berlin, März 2003. ©1
109 S. Bhattacharyya, E. Deprettere and J. Teich.
Domain-Specific Processors: Systems, Architectures, Modeling and Simulation.
Marcel Dekker, Signal Processing and Communication Series, New York, USA, 2004. ©1
108 C. Haubelt and J. Teich.
Accelerating Design Space Exploration Using Pareto-Front Arithmetics.
In Proceedings ASP-DAC 2003, Asia and South Pacific Design Automation Conference, pp. 525-531, Kitakyushu, Japan, January 21-24, 2003. ©1
2002
107 D. Fischer, J. Teich, M. Thies and R. Weper.
Efficient Architecture/Compiler Co-Exploration for ASIPs.
In ACM SIG Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES2002), pp. 27-34, October 8-11, Grenoble, France. ©1
106 F. Hannig and J. Teich.
Energy Estimation of Nested Loop Programs.
Proceedings 14th Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA 2002), Winnipeg, Manitoba, Canada, August 10-13, 2002. ©1
105 F. Hannig and J. Teich.
Energy Estimation for Piecewise Regular Processor Arrays.
In Proceedings of the Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2002). Island of Samos, Greece, July 22-25, 2002. ©1
104 M. Bednara and J. Teich.
Interface Synthesis for FPGA Based VLSI Processor Arrays.
In Proc. of The International Conference on Engineering of Reconfigurable Sytsems and Algorithms (ERSA02), Las Vegas, Nevada, U.S.A., June 24-27, 2002 . ©1
103 M. Bednara, M. Daldrup, J. Shokrollahi, J. Teich and J. von zur Gathen.
Tradeoff Analysis of FPGA Based Elliptic Curve Cryptography.
In Proc. of IEEE International Symposium on Circuits and Systems (ISCAS-02). Scottsdale, Arizona, U.S.A., May 26-29 2002.. ©1
102 S. Mostaghim, J. Teich and A. Tyagi.
Comparison of Data Structures for Storing Pareto-sets in MOEAs.
In 2002 World Congress on Computational Intelligence (CEC02), pp. 843-849, May 2002. ©1
101 M. Bednara, M. Daldrup, J. Shokrollahi, J. Teich and J. von zur Gathen.
Reconfigurable Implementation of Elliptic Curve Crypto Algorithms.
In RAW2002- Proc. The 9th Reconfigurable Architectures Workshop, Fort Lauderdale, Florida, U.S.A., April 2002. ©1
100 C. Haubelt, J. Teich, K. Richter and R. Ernst.
System Design for Flexibility.
In Proc. DATE 2002, Design, Automation and Test in Europe, IEEE Computer Society Press, pp. 854-861, Paris, France, March 4-8, 2002. ©1
99 J. Teich and L. Thiele.
Exact Partitioning of Affine Dependence Algorithms.
In Embedded Processor Design Challenges, E. Deprettere, J. Teich, and S. Vassiliadis, editors, Lecture Notes in Computer Science (LNCS), Vol. 2268, pp. 135-151, Springer, Berlin, Germany, March 2002. ©1
98 M. Köster and J. Teich.
(Self-) reconfigurable Finite State Machines.
In Proc. DATE 2002, Design, Automation and Test in Europe, IEEE Computer Society Press, Paris, France, March 4 -8, 2002. ©1
97 M. Jersak, K. Richter, D. Ziegenbein, R. Ernst, C. Haubelt, F. Slomka and J. Teich.
SPI-Workbench für die Analyse eingebetteter Systeme.
Workshop: Modelle, Werkzeuge und Infrastrukturen zur Unterstützung von Entwicklungsprozessen, talk, Aachen, Germany, March 20-22, 2002. ©1
96 C. Haubelt, J. Teich, K. Richter and R. Ernst.
Flexibility / Cost-Tradeoffs of Platform-Based Systems.
In Embedded Processor Design Challenges, E. Deprettere, J. Teich, and S. Vassiliadis, editors, Lecture Notes in Computer Science (LNCS), Vol. 2268, pp. 38-56, Springer, Berlin, Germany, March 2002. ©1
95 M. Bednara, F. Hannig and J. Teich.
Generation of Distributed Loop Control.
In Embedded Processor Design Challenges, E. F. Deprettere, J. Teich, and S. Vassiliadis, editors, Lecture Notes in Computer Science (LNCS), Vol. 2268, pp. 154-170, Springer, Berlin, Germany, March 2002. ©1
94 E. Deprettere, J. Teich and S. Vassiliadis.
Embedded Processor Design Challenges, E. F. Deprettere, J. Teich, and S. Vassiliadis, editors.
Lecture Notes in Computer Science (LNCS), Vol. 2268, Springer, Berlin, Germany, March 2002. ©1
93 C. Haubelt, J. Teich, K. Richter and R. Ernst.
Modellierung Rekonfigurierbarer Systemarchitekturen.
GI / ITG / GMM Workshop - Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Tuebingen, Germany, Shaker Verlag, pp. 163-171, February 25-27, 2002. ©1
92 R. Ernst, K. Richter, J. Teich, L. Thiele and D. Ziegenbein.
SPI - A System Model for Heterogeneously Specified Embedded Systems.
J. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 4, pp. 379-389, August 2002. ©1
2001
91 D. Fischer, U. Kastens, J. Teich, M. Thies and R. Weper.
Design Space Characterization for Architecture/Compiler Co-Exploration.
In ACM SIG Proceedings International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES 2001), pp. 108-115, Atlanta, Georgia, USA, November 2001. ©1
90 M. Bednara, F. Hannig and J. Teich.
Boundary Control: A new Distributed Control Architecture for Space-Time Transformed (VLSI) Processor Arrays.
Proc. 35th IEEE Asilomar Conf. on Signals, Systems and Computers, Pacific Grove,California, USA, November 2001. ©1
89 F. Hannig and J. Teich.
Design Space Exploration for Massively Parallel Processor Arrays.
In Proc. of the Sixth International Conference on Parallel Computing Technologies (PaCT-2001), Novosibirsk, Russia, September 3-7, 2001. ©1
88 R. Ernst, M. Gries, K. Strehl, J. Teich, L. Thiele and D. Ziegenbein.
FunState - An Internal Design Representation for Codesign.
J. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 4, pp. 524-544, August 2001. ©1
87 S. Fekete, E. Köhler and J. Teich.
Higher-Dimensional Packing with Order Constraints.
Proc. 7th Workshop on Algorithms and Data Structures, Lecture Notes in Computer Science (LNCS), Vol. 2125, pp. 300-312, Springer, August 2001. ©1
86 J. Teich.
Symbiose von Hardware und Software.
Hardware/Software Codesign, K. J. Buchenrieder, editor, IT Press, Bruchsal, pp. 79-107, July 2001. In Schriftenreihe Informationsverarbeitung und Technische Informatik. ©1
85 J. Teich.
Exact Partitioning of Affine Dependence Algorithms.
Proc. SAMOS - Systems, Architectures, Modeling and Simulation Workshop, Island of Samos, Greece, July 13-16, 2001. ©1
84 M. Bednara and J. Teich.
Synthesis of FPGA Implementations from Loop Algorithms.
In Proc. of the First International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA?01), pp. 1-7, Las Vegas, Nevada, U.S.A., June 25-28, 2001. ©1
83 S. Fekete, J. Schepers and J. Teich.
Optimization of Dynamic Hardware Reconfigurations.
The J. of Supercomputing, Kluwer Academic Publishers, Vol. 19, No. 1, pp. 57-75, May 2001. ©1
82 S. Bhattacharyya, J. Teich, E. Zitzler and N. Bambha.
Hybrid Global/Local Search Strategies for Dynamic Voltage Scaling in Embedded Multiprocessors.
Proc. 9th Int. Workshop on Hardware/Software Co-Design, Copenhagen, Denmark, pp. 243-248, April 25-27, 2001. ©1
81 D. Fischer, J. Teich and R. Weper.
Hierarchical Modeling and Simulation of Embedded Processors Using ASMs.
International Workshop on Software and Compilers for Embedded Systems, (SCOPES 2001), St.Goar, Germany, March 20-22, 2001. ©1
80 J. Teich.
Pareto-Front Exploration with Uncertain Objectives.
Proc. First International Conference on Evolutionary Multi-Criterion Optimization, Zurich, Switzerland, March 7-9, 2001. In Lecture Notes in Computer Science (LNCS), Vol. 1993, pp. 314-328, Springer, 2001. ©1
79 S. Fekete, E. Köhler and J. Teich.
Optimal FPGA Module Placement with Temporal Precedence Constraints.
In Proc. DATE 2001, Design, Automation and Test in Europe, Computer Society Press, Munich, Germany, pp. 658-665, March 13-16, 2001. ©1
78 M. Anlauff, D. Fischer, P. Kutter, J. Teich and R. Weper.
Hierarchical Microprocessor Design Using XASM.
In Proc. EUROCAST 2001, Las Palmas de Gran Canaria, Spain, pp. 271-274, February 19-23, 2001. ©1
77 M. Bednara, O. Beyer, J. Teich and R. Wanka.
Hardware Supported Sorting: Design and Tradeoff Analysis.
In System Design Automation, R. Merker and W. Schwarz, editors, Kluwer Academic Publishers, pp. 97-107, 2001. ©1
76 S. Fekete, E. Köhler and J. Teich.
Extending Partial Suborders.
Electronic Notes in Discrete Mathematics, Hajo Broersma, Ulrich Faigle, Johann Hurink and Stefan Pickl, editors, Elsevier Science Publishers, Vol. 8, 2001. ©1
75 J. Teich.
Synthesis and Optimization of Digital Hardware/Software Systems.
In System Design Automation, R. Merker and W. Schwarz, editors, Kluwer Academic Publishers, pp. 3-26, 2001. ©1
2000
74 K. Strehl, J. Teich and L. Thiele.
Regular State Machines.
J. Parallel Algorithms and Applications, Vol. 15, pp. 265-300, December 2000. ©1
73 D. Fischer, J. Teich, S. Trinkert and R. Weper.
A Joined Architecture/Compiler Environment for ASIPs.
ACM SIG Proc. International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES 2000). San Jose, CA, U.S.A., pp. 26 - 33, November 2000 . ©1
72 F. Cieslok, H. Esau and J. Teich.
EXPLORA - Generic Design Space Exploration During Embedded System Synthesis.
Proc. DIPES 2000, Int. IFIP Workshop on Distributed and Parallel Embedded Systems. Schloss Eringerfeld, Germany, October 2000. In Architecture and Design of Distributed Embedded Systems, B. Kleinjohann, editor, Kluwer Academic Publishers, pp. 215-225, June 2001. ©1
71 D. Fischer, J. Teich, S. Trinkert and R. Weper.
BUILDABONG: A Rapid Prototyping Environment for ASIPs.
Proc. DSP-Deutschland 2000, pp. 153-162, Munich, Germany. WEKA Fachzeitschriften Verlag, October 2000. ©1
70 P. Kutter, J. Teich and R. Weper.
Description and Simulation of Microprocessor Instruction Sets Using ASMs.
International Workshop on Abstract State Machines. Lecture Notes in Computer Science (LNCS) 1912, pp. 266-286, Springer-Verlag, October 2000. ©1
69 F. Cieslok, R. Ernst, M. Jersak, K. Richter, K. Strehl, J. Teich, L. Thiele, F. Wolf and D. Ziegenbein.
Embedded System Design using the SPI Workbench.
Proc. FDL'00, Forum on Design Languages 2000, Tübingen, Germany, September 2000. ©1
68 S. Bhattacharyya, J. Teich and E. Zitzler.
Evolutionary Algorithms for the Synthesis of Embedded Software.
J. IEEE Trans. on VLSI Systems, Vol. 8, No. 4, pp. 452-456, August 2000 . ©1
67 M. Bednara, O. Beyer, J. Teich and R. Wanka.
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter.
Proc. ASAP'00, the Int. Conf. on Application Specific Systems, Architectures, and Processors, pp. 299-308, Boston, MA, U.S.A. IEEE Computer Society Press, July 2000. ©1
66 S. Bhattacharyya, J. Teich and E. Zitzler.
Optimizing the Efficiency of Parameterized Local Search within Global Search:.
Proc. of CEC'2000, the Int. Conf. on Evolutionary Computation, La Jolla, CA, U.S.A., pp. 365-372, July 2000. ©1
65 J. Teich.
Embedded System Synthesis and Optimization.
Invited paper, Proc. Workshop on System Design Automation - SDA 2000, pp. 9-22, Rathen, Germany. VDE-Verlag, March 2000. ©1
64 C. Böke, C. Ditze, W. Hardt, B. Kleinjohann, F. Rammig, A. Rettberg, J. Stroop and J. Teich.
IP-based System Design with the PARADISE Design Environment.
Accepted, J. Euromicro, March 2000. ©1
63 M. Bednara, W. Hardt, A. Rettberg and J. Teich.
Automated Design Space Exploration on System Level for Embedded Systems.
Proc. Ninth Annual International HDL Conference and Exhibition (HDL Conf. 2000), San Jose, CA, U.S.A., March 2000. ©1
62 M. Bednara, O. Beyer, J. Teich and R. Wanka.
Hardware-Supported Sorting: Design and Tradeoff Analysis.
Workshop on System Design Automation - SDA 2000, pp.37-44, Rathen, Germany. VDE-Verlag, March 2000. ©1
61 R. Ernst, K. Richter, J. Teich and D. Ziegenbein.
SPI Workbench - Entwurf gemischt reaktiv/transformativer Systeme.
AES 2000, Workshop Architekturentwurf für eingebettete Systeme, pp. 184-191, Karlsruhe, Germany, January 2000. ©1
60 P. Kutter, J. Teich and R. Weper.
Description and Simulation of Microprocessor Instruction Sets Using ASMs.
Proc. ASM 2000 Workshop, pp. 376-397, Monte Verita, Ascona, Switzerland, 2000. ©1
59 J. Teich.
Symbiose von Hardware und Software.
ForschungsForum 2000, No.2, pp. 82-87, Universität Paderborn, Germany, 2000. ©1
58 S. Bhattacharyya, J. Teich and E. Zitzler.
Multidimensional Exploration of Software Implementations for DSP Algorithms.
J. of VLSI Signal Processing Systems, Vol. 24, pp. 83-98, Kluwer Academic Publishers, 2000. ©1
1999
57 R. Ernst, K. Strehl, J. Teich, L. Thiele and D. Ziegenbein.
FunState - An Internal Design Representation for Codesign.
Proc. ICCAD'99, the IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 558-565, San Jose, CA, U.S.A., November 1999. ©1
56 S. Bhattacharyya, J. Teich and E. Zitzler.
Optimized Software Synthesis for DSP Using Randomization Techniques.
Technical Report No. 75, Computer Engineering and Communication Networks Lab (TIK), Swiss Federal Institute of Technology (ETH) Zurich, Gloriastrasse 35, CH-8092 Zurich, July 1999. ©1
55 S. Bhattacharyya, J. Teich and E. Zitzler.
Evolutionary Algorithm Based Exploration of Software Schedules for Digital Signal Processors.
Proc. GECCO'99, the Genetic and Evolutionary Computation Conference, pp. 1762-1769, Orlando, Florida, U.S.A., July 1999. ©1
54 S. Fekete, J. Schepers and J. Teich.
Compile-Time Optimization of Dynamic Hardware Reconfigurations.
Proc. Int. Conf. on Parallel and Distributed Processing Techniques and Applications (PDPTA'99), pp. 1097-1103, Las Vegas, Nevada, U.S.A., June 1999. ©1
53 R. Ernst, K. Richter, J. Teich, L. Thiele and D. Ziegenbein.
Representation of Function Variants for Embedded System Optimization and Synthesis.
Proc. 36th Design Automation Conference (DAC), pp. 517-522, New Orleans, U.S.A., June 1999. ©1
52 R. Ernst, K. Strehl, J. Teich, L. Thiele and D. Ziegenbein.
Scheduling Hardware/Software Systems Using Symbolic Techniques.
Proc. CODES'99, the 7th Int. Workshop on Hardware/Software Co-Design, pp. 173-177, Rome, Italy, May 1999. ©1
51 S. Bhattacharyya, J. Teich and E. Zitzler.
3D Exploration of Software Schedules for DSP Algorithms.
Proc. CODES'99, the 7th Int. Workshop on Hardware/Software Co-Design, pp. 168-172, Rome, Italy, May 1999. ©1
50 S. Bhattacharyya, J. Teich and E. Zitzler.
3D Exploration of Uniprocessor Schedules for DSP ALgorithms.
Technical Report No. 56, Computer Engineering and Communication Networks Lab (TIK), Swiss Federal Institute of Technology (ETH) Zurich, Gloriastrasse 35, CH-8092 Zurich, April 1999. ©1
49 R. Ernst, K. Richter, J. Teich, L. Thiele and D. Ziegenbein.
SPI - An Internal Representation for Heterogeneously Specified Embedded Systems.
Proc. GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, pp. 160-169, Braunschweig, Germany, February 1999. ©1
48 R. Ernst, K. Richter, J. Teich, L. Thiele and D. Ziegenbein.
Hardware/Software Codesign of Embedded Systems - The SPI Workbench.
Proc. Int. Workshop on VLSI, pp. 9-17, Orlando, Florida, U.S.A., 1999. ©1
1998
47 R. Ernst, K. Richter, J. Teich, L. Thiele and D. Ziegenbein.
Representation of Process Mode Correlation for Scheduling.
Proc. of ICCAD - the ACM/IEEE Int. Conf. on CAD, pp. 54-61, San Jose, CA, U.S.A., November 1998. ©1
46 S. Fekete, J. Schepers and J. Teich.
Optimizing Dynamic Hardware Reconfigurations.
Technical Report, Zentrum für Paralleles Rechnen, Universität zu Köln, Oktober 1998. ©1
45 S. Bhattacharyya, J. Teich and E. Zitzler.
Optimized Software Synthesis for Digital Signal Processing Algorithms: An Evolutionary Approach.
Proc. of the 1998 Workshop on Signal Processing Systems (SiPS), Boston, U.S.A., pp. 589-598, October 1998. ©1
44 S. Bhattacharyya, J. Teich and E. Zitzler.
Optimized Software Synthesis for Digital Signal Processing Algorithms: An Evolutionary Approach.
Proc. of the 1998 Workshop on Signal Processing Systems (SiPS), Boston, U.S.A., pp. 589-598, October 1998. ©1
43 S. Bhattacharyya, J. Teich and E. Zitzler.
Buffer Memory Optimization in DSP Applications - An Evolutionary Approach.
Parallel Problem Solving from Nature (PPSN'98), Amsterdam, The Netherlands, Springer Lecture Notes in Computer Science (LNCS) 1498, pp. 292-301, Springer-Verlag, September 1998. ©1
42 M. Eisenring and J. Teich.
Interfacing Hardware and Software.
Proc. of FPL'98, the Conf. on Field-Programmable Logic and Applications, Tallin, Estonia, Springer Lecture Notes in Computer Science (LNCS) 1482, pp. 520-524, Springer-Verlag, September 1998. ©1
41 J. Teich and L. Thiele.
Regular State Machines.
Presented at Workshop Seminar No. 98341, Tiling for Optimal Resource Utilization, Schloss Dagstuhl, Germany, August 1998. ©1
40 J. Teich and E. Zitzler.
3D Exploration of Uniprocessor Schedules for DSP Algorithms.
Technical Report, Computer Engineering and Communication Networks Lab (TIK), Swiss Federal Institute of Technology (ETH) Zurich, Gloriastrasse 35, CH-8092 Zurich, August 1998. ©1
39 R. Esser, J. Teich and L. Thiele.
CodeSign: An Embedded System Design Environment.
IEE Proc. - Computers and Digital Techniques, 145(3):171-180, May 1998. ©1
38 M. Eisenring and J. Teich.
Domain-Specific Interface Generation From Dataflow Specifications.
Proc. of Codes/CASHE'98, the 6th Int. Workshop on Hardware/Software Co-design, Seattle, Washington, U.S.A., pp. 43-47, March 1998. ©1
37 R. Ernst, K. Richter, J. Teich, L. Thiele and D. Ziegenbein.
Combining Multiple Models of Computation for Scheduling and Allocation.
Proc. of Codes/CASHE\'98, the 6th Int. Workshop on Hardware/Software Codesign, Seattle, Washington, U.S.A., pp. 9-13, March 1998. ©1
36 M. Naedele, K. Strehl, J. Teich, L. Thiele and D. Ziegenbein.
SCF - State Machine Controlled Flow Diagrams.
Technical Report No. 33, Computer Engineering and Communication Networks Lab (TIK), Swiss Federal Institute of Technology (ETH) Zurich, Gloriastrasse 35, CH-8092 Zurich, January 1998. ©1
35 S. Bhattacharyya, J. Teich and E. Zitzler.
Optimized Software Synthesis for Digital Processing Algorithms - An Evolutionary Approach.
Technical Report No. 32, Computer Engineering and Communication Networks Lab (TIK), Swiss Federal Institute of Technology (ETH) Zurich, Gloriastrasse 35, CH-8092 Zurich, January 1998. ©1
34 M. Eisenring, J. Teich and L. Thiele.
Rapid Prototyping of Dataflow Programs on Hardware/Software Architectures.
In Proc. of HICSS'98, the Hawai'i Int. Conf. on Syst. Sci., Kona, Hawaii, U.S.A., pp. 187-196, January 1998. ©1
33 T. Blickle, J. Teich and L. Thiele.
System-Level Synthesis Using Evolutionary Algorithms.
J. Design Automation for Embedded Systems, Vol. 3, No. 1, pp. 23-58 , Kluwer Academic Publishers, January 1998. ©1
1997
32 J. Teich, L. Thiele and L. Zhang.
Partitioning Processor Arrays under Resource Constraints.
Int. Journal on VLSI and Signal Processing, Vol. 17, No. 1, pp. 5-20, September 1997. ©1
31 J. Fortes, T. Noll, V. Taylor, J. Teich, L. Thiele and K. Vissers.
Proc. IEEE Int. Conference on Application Specific Systems, Architectures, and Processors (ASAP´97).
IEEE Computer Society Press, Los Alamitos, July 1997. ©1
30 M. Martin, S. Sriram, J. Teich and L. Thiele.
Performance Analysis of Mixed Asynchronous-Synchronous Systems.
J. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 16, No. 5, pp. 473-484, May 1997. ©1
29 J. Teich.
Hardware/Software-Codesign: Massgeschneiderte elektronische Systeme. Teil II: HW/SW-Synthese.
J. SEV/VSE Bulletin, Vol. 3/97, pp. 17-22, March 1997. ©1
28 T. Blickle, J. Teich and L. Thiele.
An Evolutionary Approach to System-Level Synthesis.
Proc. of Codes/CASHE'97, the 5th Int. Workshop on Hardware/Software Co-design, Braunschweig, Germany, pp. 167-171, March 1997. ©1
27 J. Teich.
Digitale Hardware/Software-Systeme: Synthese und Optimierung.
Springer-Lehrbuch, Springer-Verlag, Berlin, 1997. ©1
1996
26 J. Teich.
Hardware/Software-Codesign: Massgeschneiderte elektronische Systeme.Teil I: HW/SW-Architekturen und Spezifikation.
J. SEV/VSE Bulletin, Vol. 25/96, pp. 17-23, December 1996. ©1
25 T. Blickle, J. Teich and L. Thiele.
An evolutionary approach to system-level synthesis.
Proc. of WSC1, the 1st Online Workshop on Soft Computing, pp. 251-256, Nagoya, Japan, August 1996. ©1
24 J. Teich, L. Thiele and L. Zhang.
Scheduling of partitioned regular algorithms on processor arrays with constrained resources.
In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP´96), pp. 131-144, Chicago, U.S.A., August 1996. ©1
23 J. Teich.
Synthesis and Optimization of Digital Hardware/Software Systems.
Habilitationsschrift, Computer Engineering and Communication Networks Lab (TIK), ETH Zurich, Switzerland, April 1996. ©1
22 J. Teich and L. Thiele.
A new approach to solving resource-constrained scheduling problems based on a flow-model.
Technical Report No. 17, Computer Engineering and Communication Networks Lab (TIK), Swiss Federal Institute of Technology (ETH) Zurich, Gloriastrasse 35, CH-8092 Zurich, March 1996. Presented at Workshop Dagstuhl Seminar No. 9617, Design Automation for Embedded Systems, Schloss Dagstuhl, Germany, April 1996 . ©1
21 T. Blickle, J. Teich and L. Thiele.
System-level synthesis using evolutionary algorithms.
Technical Report No. 16, Computer Engineering and Communication Networks Lab (TIK), Swiss Federal Institute of Technology (ETH) Zurich, Gloriastrasse 35, CH-8092 Zurich, March 1996. Presented at Workshop Dagstuhl Seminar No. 9613, Evolutionary Algorithms and their Application, Schloss Dagstuhl, Germany, March 1996. ©1
1995
20 E. Lee, J. Teich and L. Thiele.
Simulation and modeling of heterogeneous systems modeled by deterministic discrete event systems.
In 8th Int. Symposium on System Level Synthesis (ISSS´95), Cannes, France, pp. 156-161, October 1995. ©1
19 B. Evans, C. Schwarz, J. Teich and E. Welzl.
On finding a minimal enclosing parallelogram.
In Proc. 11th ACM Symposium on Computational Geometry, Vancouver, British Columbia, Canada, June 1995. ©1
1994
18 B. Evans, T. Kalker and J. Teich.
Families of Smith Form Decompositions to simplify Multidimensional Filter Design.
In Proc. IEEE Asilomar Conf. on Signals, Systems and Computers, pp. 498-501, Pacific Grove, CA, U.S.A., November 1994. ©1
17 M. Martin, S. Sriram, J. Teich and L. Thiele.
Performance analysis and optimization of mixed asynchronous synchronous systems.
Technical report, ERL Technical Report UCB/ERL No. 94/95, University of California, Berkeley, CA 94720, U.S.A., November 1994. ©1
16 B. Evans, C. Schwarz and J. Teich.
Automateddesign of two-dimensional rational decimation systems.
In Proc. IEEE Asilomar Conf. on Signals, Systems and Computers, pp. 363-367, Pacific Grove, CA, U.S.A., November 1994. ©1
15 M. Martin, S. Sriram, J. Teich and L. Thiele.
Performance Analysis of Mixed Asynchronous-Synchronous Systems.
In Proc. of the IEEE Int. Workshop on VLSI Signal Processing 94,pp. 103-112, Proceedings published as IEEE VLSI Signal Processing VII, October 1994. ©1
14 B. Evans, C. Schwarz, J. Teich and E. Welzl.
On finding a minimal enclosing parallelogram.
4th MSI Workshop on Computational Geometry, Cornell University, Ithaca, NY, U.S.A., October 1994. ©1
13 B. Evans, C. Schwarz, J. Teich and E. Welzl.
On finding a minimal enclosing parallelogram.
Technical Report TR-94-036, ICSI - International Computer Science Institute, Berkeley, CA, U.S.A., 1994. ©1
1993
12 J. Teich.
A Compiler for Application-Specific Processor Arrays.
Doctoral thesis, Institut für Mikroelektronik, Universität des Saarlandes, Saarbrücken, Germany, September 1993. ©1
11 J. Teich, L. Thiele and L. Zhang.
Minimal communication in massively parallel architectures.
In Proc. of PARS Workshop 93, pp. 154-161, Dresden, Germany, April 1993. ©1
10 J. Teich.
A Compiler for Application-Specific Processor Arrays.
Shaker (Reihe Elektrotechnik), ISBN 3-86111-701-0, Aachen, Germany, 1993. ©1
9 J. Teich and L. Thiele.
Partitioning of processor arrays: A piecewise regular approach.
INTEGRATION: The VLSI Journal, 14(3):297-332, 1993. ©1
1992
8 J. Teich and L. Thiele.
A transformative approach to the partitioning of processor arrays.
In Proc. Int. Conf. on Application Specific Array Processors (ASAP´92), Berkeley, CA, U.S.A., pp. 4-20, IEEE Computer Society, August 1992. ©1
7 U. Arzt, J. Teich and L. Thiele.
The concepts of COMPAR: A compiler for massive parallel architectures.
In Proc. International Symposium on Circuits and Systems (ISCAS´92), pp. 681-684, San Diego, CA, U.S.A., May 1992. ©1
6 U. Arzt, J. Teich and L. Thiele.
Hierarchical concepts in the design of processor arrays.
In Proc. CompEuro 1992, pp. 232-238, The Hague, The Netherlands, May 1992. ©1
5 J. Teich and L. Thiele.
Control generation in the design of processor array.
In J.A Nossek, editor, Parallel Processing on VLSI Arrays, Kluwer Academic Publishers, 1992. ©1
1991
4 J. Teich and L. Thiele.
Control generation in the design of processor arrays.
Int. Journal on VLSI and Signal Processing, 3(2):77-92, 1991. ©1
3 J. Teich and L. Thiele.
Uniform design of parallel programs for DSP.
In Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), pages 344a-347a, Singapore, June 1991.. ©1
1990
2 J. Teich and L. Thiele.
Systematic design concepts for signal processing arrays (invited paper).
Frequenz /Journal of telecommunications, Vol. 44, pp. 122-132, May 1990. ©1
1 M. Huber, J. Teich and L. Thiele.
Design of configurable processor arrays (invited paper).
In Proc. IEEE Int. Symp. Circuits and Systems (ISCAS). ©1

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