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Codesign
Department of Computer Science 12
Moritz Schmid
Dept. of Computer Science  >  CS 12  >  Staff  >  Moritz Schmid
Department of Computer Science 12
(Hardware-Software-Co-Design)
University of Erlangen-Nuremberg
Cauerstr. 11
D-91058 Erlangen
Germany
Phone: +49 9131 85-67306
Mail: moritz.schmid[at]informatik.uni-erlangen.de
Research Interests
Massively Parallel VLSI Architectures, Project PARO
Image processing for Time-of-Flight, Project MMSys - Motion Management System
High-speed interconnect architectures for embedded systems
Digital signal processing on FPGAs
Education
Sommersemester 2013
Hauptseminar Electronic System Level Design
Wintersemester 2013/14
Grundlagen der Technischen Informatik
Übung zu Grundlagen der Technischen Informatik
Praktikum zu Grundlagen der Technischen Informatik
Sommersemester 2013
Hauptseminar Electronic System Level Design
Übung zu Grundlagen der Technischen Informatik
Praktikum zu Grundlagen der Technischen Informatik
Wintersemester 2012/13
Grundlagen der Technischen Informatik
Übung zu Grundlagen der Technischen Informatik
Praktikum zu Grundlagen der Technischen Informatik
Sommersemester 2012
Hauptseminar Electronic System Level Design
Übung zu Grundlagen der Technischen Informatik
Praktikum zu Grundlagen der Technischen Informatik
Wintersemester 2011/12
Grundlagen der Technischen Informatik
Übung zu Grundlagen der Technischen Informatik
Praktikum zu Grundlagen der Technischen Informatik
Sommersemester 2011
Hauptseminar Electronic System Level Design
Übung zu Grundlagen der Technischen Informatik
Praktikum zu Grundlagen der Technischen Informatik
Wintersemester 2010/11
Grundlagen der Technischen Informatik
Übung zu Grundlagen der Technischen Informatik
Praktikum zu Grundlagen der Technischen Informatik
Sommersemester 2010
Hauptseminar Electronic System Level Design
Übung zu Grundlagen der Technischen Informatik
Praktikum zu Grundlagen der Technischen Informatik
Wintersemester 2009/10
Grundlagen der Technischen Informatik
Publications
2017
24 C. Schmitt, M. Schmid, S. Kuckuk, H. Köstler, J. Teich and F. Hannig.
Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution.
To appear in Parallel Processing Letters. ©1
23 O. Reiche, M. Özkan, F. Hannig, J. Teich and M. Schmid.
Loop Parallelization Techniques for FPGA Accelerator Synthesis.
In Journal of Signal Processing Systems (JSPS), 2017. ©1
[doi>10.1007/s11265-017-1229-7]
2016
22 V. Bhadouria, A. Tanase, M. Schmid, F. Hannig, J. Teich and D. Ghoshal.
A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators.
Journal of Signal Processing Systems, pp. 1-18, 2016. ©1
[doi>10.1007/s11265-016-1187-5]
21 M. Schmid, C. Schmitt, F. Hannig, G. Malazgirt, N. Sönmez, A. Yurdakul and A. Cristal.
Big Data and HPC Acceleration with Vivado HLS.
In Dirk Koch, Frank Hannig, and Daniel Ziener, editors, FPGAs for Software Programmers, chapter 7, pp. 115-136. Springer, 2016. ©1
[doi>10.1007/978-3-319-26408-0_7]
20 M. Schmid, O. Reiche, F. Hannig and J. Teich.
HIPAcc.
In Dirk Koch, Frank Hannig, and Daniel Ziener, editors, FPGAs for Software Programmers, chapter 12, pp. 205-223. Springer, 2016. ©1
[doi>10.1007/978-3-319-26408-0_12]
2015
19 O. Reiche, K. Häublein, M. Reichenbach, M. Schmid, F. Hannig, J. Teich and D. Fey.
Synthesis and Optimization of Image Processing Accelerators using Domain Knowledge.
In Journal of Systems Architecture (JSA), 61(10), pp. 646-658, 2015. ©1
[doi>10.1016/j.sysarc.2015.09.004]
18 M. Schmid, O. Reiche, F. Hannig and J. Teich.
Loop Coarsening in C-based High-Level Synthesis.
In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 166-173, Toronto, Canada, Jul. 27-29, 2015. ©1
[doi>10.1109/ASAP.2015.7245730]
17 M. Schmid.
Rapid Prototyping for Hardware Accelerators in the Medical Imaging Domain.
Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, July 24, 2015. ©1
16 C. Schmitt, M. Schmid, F. Hannig, J. Teich, S. Kuckuk and H. Köstler.
Generation of Multigrid-based Numerical Solvers for FPGA Accelerators.
In Proceedings of the 2nd International Workshop on High-Performance Stencil Computations (HiStencils), pp. 9-15, Amsterdam, The Netherlands, January 20, 2015. ©1
2014
15 O. Reiche, M. Schmid, F. Hannig, R. Membarth and J. Teich.
Code Generation from a Domain-specific Language for C-based HLS of Hardware Accelerators.
In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New Dehli, India, October 12-17, 2014. ©1
[doi>10.1145/2656075.2656081]
14 M. Schmid, N. Apelt, F. Hannig and J. Teich.
An Image Processing Library for C-based High-Level Synthesis.
In Proceedings of the 24th International Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, September 2-4, 2014. ©3
[doi>10.1109/FPL.2014.6927424]
13 M. Schmid, O. Reiche, C. Schmitt, F. Hannig and J. Teich.
Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs.
In Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP), pp. 21-26, Munich, Germany, September 1, 2014. arXiv: 1408.4721 [cs.CV]. ©1
12 M. Schmid, A. Tanase, V. Badhouria, F. Hannig, J. Teich and D. Ghoshal.
Domain-Specific Augmentations for High-Level Synthesis.
In Proceedings of the 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 173-177, IEEE, Zurich, Switzerland, Jun. 18-20, 2014. ©1
[doi>10.1109/ASAP.2014.6868653]
11 M. Schmid, F. Hannig, A. Tanase and J. Teich.
High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model.
In Parallel Computing: Accelerating Computational Science and Engineering (CSE), volume 25 of Advances in Parallel Computing, pp. 497-506, IOS Press, 2014. ©1
[doi>10.3233/978-1-61499-381-0-497]
2013
10 M. Schmid, M. Blocherer, F. Hannig and J. Teich.
Real-Time Range Image Preprocessing on FPGAs.
In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), pp.1-8, Cancun, Mexico, Dec. 09 - 11, 2013. ©1
9 F. Hannig, M. Schmid, V. Lari, S. Boppu and J. Teich.
System Integration of Tightly-Coupled Processor Arrays using Reconfigurable Buffer Structures.
Proceedings of the ACM International Conference on Computing Frontiers (CF), Ischia, Italy, May 14-16, 2013. ©1
8 V. Lari, S. Muddasani, S. Boppu, F. Hannig, M. Schmid and J. Teich.
Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays.
ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 18, No. 1, Article 2, Pages 2:1–2:25, January 2013. ©1
[doi>http://dx.doi.org/10.1145/2390191.2390193]
2012
7 M. Schmid, F. Hannig and J. Teich.
Power Management Strategies for Serial RapidIO Endpoints in FPGAs.
Proceedings of the IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM'12), pp. 101-108, Toronto, Canada, April 29th - May 1st, 2012. ©3
2011
6 J. Wasza, S. Bauer, S. Haase, M. Schmid, S. Reichert and J. Hornegger.
RITK: The Range Imaging Toolkit – A Framework for 3-D Range Image Stream Processing.
In Proceeding of International Workshop on Vision, Modeling and Visualization (VMV), pp. 57-64, Berlin, Oct. 2011. ©1
2010
5 F. Hannig, M. Schmid, J. Teich and H. Hornegger.
A Deeply Pipelined and Parallel Architecture for Denoising Medical Images.
In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT), pp. 485-490, Beijing, China, December 8-10, 2010. ©3
4 D. Ziener, M. Schmid and J. Teich.
Robustness Analysis of Watermark Verification Techniques for FPGA Netlist Cores.
In Design Methodologies for Secure Embedded Systems, A. Biedermann and H. Gregor Molter (Eds.), Lecture Notes in Electrical Engineering, volume 78, pp. 105-127, Springer-Verlag, Berlin Heidelberg, 2010. ©1
3 H. Dutta, F. Hannig, M. Schmid and J. Keinert.
Modeling and Synthesis of Communication Subsystems for Loop Accelerator Pipelines.
In Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), pp. 125-132, Rennes, France, July 7-9, pages 125-132, 2010. ©2
2 M. Schmid, F. Hannig, J. Teich, R. Diefenbach, H. Pettendorf and H. Hornegger.
Discourse on Extending Embedded Medical Image Processing Systems Using the High Speed Serial RapidIO Interconnect.
Proceedings of the Embedded World Conference, Nuremberg, Germany, March 03-05, 2010. ©1
2008
1 M. Schmid, D. Ziener and J. Teich.
Netlist-Level IP Protection by Watermarking for LUT-Based FPGAs.
In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2008), pp. 209-216, Taipei, Taiwan, December 08-10, 2008. ©1

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