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Codesign
Lehrstuhl für Informatik 12
Oliver Reiche
Curriculum Vitæ
Research
Interests
Teaching
Open Theses
Supervised Theses
Publications
Misc

Department Informatik  >  Informatik 12  >  Personal  >  Oliver Reiche

Oliver Reiche
M. Sc.

Oliver Reiche
Address:
Department of Computer Science 12
(Hardware-Software-Co-Design)
Friedrich-Alexander University Erlangen-Nürnberg
Cauerstraße 11
D-91058 Erlangen
Germany
Office: 02.121-128
Phone: +49 9131 85-67270
Fax: +49 9131 85-25149
Email: oliver.reiche(at)cs.fau.de
PGP Key: C0FA9963

Curriculum Vitæ

since 2012 Researcher at the Department of Computer Science 12 (Hardware/Software Co-Design), Friedrich-Alexander University Erlangen-Nürnberg, Erlangen, Germany
2010 - 2012 Master in Computer Science, Georg-Simon-Ohm Hochschule, Nuremberg, Germany
2006 - 2010 Bachelor in Computer Science, Georg-Simon-Ohm Hochschule, Nuremberg, Germany
June, 1986 Born in Leipzig, Germany

Research Interests

  • Multi-Core Architectures and Programming
  • Parallel Architectures (GPGPUs)
  • Parallel Programming Models for Many-core Systems: CUDA, OpenCL, Renderscript
  • Domain-Specific Languages
  • Image Processing

Other Interests

Teaching

SS 2017 Multi-Core Architectures and Programming
WS 2016/2017 Embedded Systems
Extended Exercise Embedded Systems
Domain-Specific and Resource-Aware Computing on Multicore Architectures
SS 2016 Multi-Core Architectures and Programming
Extended Exercise Hardware/Software Co-Design
WS 2015/2016 Embedded Systems
Extended Exercise Embedded Systems
Domain-Specific and Resource-Aware Computing on Multicore Architectures
SS 2015 Multi-Core Architectures and Programming
WS 2014/2015 Embedded Systems
Extended Exercise Embedded Systems
Domain-Specific and Resource-Aware Computing on Multicore Architectures
SS 2014 Multi-Core Architectures and Programming
WS 2013/2014 Embedded Systems
Extended Exercise Embedded Systems
Domain-Specific and Resource-Aware Computing on Multicore Architectures
SS 2013 Multi-Core Architectures and Programming
WS 2012/2013 Extended Exercise Embedded Systems

Open Theses

Analyzing Optical Flow Algorithms

Supervised Theses

  • Kolonnenspurerkennung im Automobil
  • Selective Embedded Just-in-Time Specialization for FPGAs
  • Parallelisierung einer Interval-Karte mit einer GPU
  • Domain-Specific Computation with Lisp
  • Hardware-Software-Kommunikation unter Android auf dem Zynq SoC
  • High-Level Synthese von Bildverarbeitungsalgorithmen mit OpenCL
  • Beschleuniger für adaptive Bildverarbeitung auf FPGAs
  • Domänenspezifische GPU-Berechnungen in Python
  • Whole-Function Vectorization based on a Domain-Specific Approach for General-Purpose Processors with SIMD Extensions

Publications

2017
15 O. Reiche, M. Özkan, F. Hannig, J. Teich and M. Schmid.
Loop Parallelization Techniques for FPGA Accelerator Synthesis.
In Journal of Signal Processing Systems (JSPS), 2017. ©1
[doi>10.1007/s11265-017-1229-7]
2016
14 J. Fickenscher, O. Reiche, J. Schlumberger, F. Hannig and J. Teich.
Modeling, Programming and Performance Analysis of Automotive Environment Map Representations on Embedded GPUs.
In Proceedings of the 18th IEEE International High-Level Design Validation and Test Workshop (HLDVT), pp. 70-77, Santa Cruz, CA, USA, October 7-8, 2016. ©1
[doi>10.1109/HLDVT.2016.7748257]
13 M. Özkan, O. Reiche, F. Hannig and J. Teich.
FPGA-Based Accelerator Design from a Domain-Specific Language.
In Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL), pp. 1-9, Lausanne, Switzerland, August 29-September 2, 2016. ©1
[doi>10.1109/FPL.2016.7577357]
12 K. Häublein, M. Reichenbach, O. Reiche, M. Özkan, D. Fey, F. Hannig and J. Teich.
Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures.
In Proceedings of the 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), pp. 211-218, Island of Samos, Greece, July 18-21, 2016. ©1
[doi>10.1109/SAMOS.2016.7818350]
11 M. Schmid, O. Reiche, F. Hannig and J. Teich.
HIPAcc.
In Dirk Koch, Frank Hannig, and Daniel Ziener, editors, FPGAs for Software Programmers, chapter 12, pp. 205-223. Springer, 2016. ©1
[doi>10.1007/978-3-319-26408-0_12]
10 K. Selgrad, A. Lier, J. Dörntlein, O. Reiche and M. Stamminger.
A High-Performance Image Processing DSL for Heterogeneous Architectures.
In Proceedings of the 9th European Lisp Symposium (ELS), pp. 39-46, Kraków, Poland, May 9-10, 2016. ©1
9 R. Membarth, O. Reiche, F. Hannig, J. Teich, M. Körner and W. Eckert.
HIPAcc: A Domain-Specific Language and Compiler for Image Processing.
IEEE Transactions on Parallel and Distributed Systems, 27(1), pp. 210-224, 2016. ©3
[doi>10.1109/TPDS.2015.2394802]
2015
8 O. Reiche, K. Häublein, M. Reichenbach, M. Schmid, F. Hannig, J. Teich and D. Fey.
Synthesis and Optimization of Image Processing Accelerators using Domain Knowledge.
In Journal of Systems Architecture (JSA), 61(10), pp. 646-658, 2015. ©1
[doi>10.1016/j.sysarc.2015.09.004]
7 M. Schmid, O. Reiche, F. Hannig and J. Teich.
Loop Coarsening in C-based High-Level Synthesis.
In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 166-173, Toronto, Canada, Jul. 27-29, 2015. ©1
[doi>10.1109/ASAP.2015.7245730]
6 O. Reiche, K. Häublein, M. Reichenbach, F. Hannig, J. Teich and D. Fey.
Automatic Optimization of Hardware Accelerators for Image Processing.
In Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS), pp. 10-15, Grenoble, France, March 13, 2015. arXiv: 1502.07448 [cs.PL]. ©1
2014
5 R. Membarth, O. Reiche, C. Schmitt, F. Hannig, J. Teich, M. Stürmer and H. Köstler.
Towards a Performance-portable Description of Geometric Multigrid Algorithms using a Domain-specific Language.
In Journal of Parallel and Distributed Computing (JPDC). 74(12), pp. 3191-3201, 2014. ©1
[doi>10.1016/j.jpdc.2014.08.008]
4 O. Reiche, M. Schmid, F. Hannig, R. Membarth and J. Teich.
Code Generation from a Domain-specific Language for C-based HLS of Hardware Accelerators.
In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New Dehli, India, October 12-17, 2014. ©1
[doi>10.1145/2656075.2656081]
3 M. Schmid, O. Reiche, C. Schmitt, F. Hannig and J. Teich.
Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs.
In Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP), pp. 21-26, Munich, Germany, September 1, 2014. arXiv: 1408.4721 [cs.CV]. ©1
2 F. Hannig, V. Lari, S. Boppu, A. Tanase and O. Reiche.
Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach.
ACM Transactions on Embedded Computing Systems (TECS), 2014. ©1
[doi>10.1145/2584660]
1 R. Membarth, O. Reiche, F. Hannig and J. Teich.
Code Generation for Embedded Heterogeneous Architectures on Android.
In Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pp. 86:1-86:6, Dresden, Germany, March 24-28, 2014. ©3
[doi>10.7873/DATE.2014.099]

Misc.

2016
8 M. Özkan, O. Reiche, F. Hannig and J. Teich.
FPGA-Based Accelerator Design from a Domain-Specific Language.
Talk, International Conference on Field-Programmable Logic and Applications (FPL), Lausanne, Switzerland, August 29-September 2, 2016. ©1
2015
7 O. Reiche.
Automatic Optimization of Hardware Accelerators for Image Processing.
Talk, DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS), Grenoble, France, March 13, 2015. ©1
2014
6 O. Reiche.
Code Generation from a Domain-specific Language for C-based HLS of Hardware Accelerators.
Poster Presentation at the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New Dehli, India, October 12-17, 2014. ©1
5 O. Reiche.
Code Generation from a Domain-specific Language for C-based HLS of Hardware Accelerators.
Talk, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New Dehli, India, October 12-17, 2014. ©1
4 O. Reiche.
Code Generation for Embedded Heterogeneous Architectures on Android.
Talk, Conference on Design, Automation and Test in Europe (DATE), Dresden, Germany, March 24-28, 2014. ©1
3 O. Reiche, R. Membarth, F. Hannig and J. Teich.
Automatic GPU Code Generation for Android.
Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March 24-28, 2014. ©1
2 R. Membarth and O. Reiche.
HIPAcc: A Domain-Specific Language and Compiler for Image Processing.
Poster Presentation at the GPU Technology Conference (GTC), San Jose, CA, USA, March 24-27, 2014. ©1
2013
1 O. Reiche.
Code Generation for GPU Accelerators in the Domain of Image Preprocessing.
Talk, Dagstuhl Seminar 13142, Correct and Efficient Accelerator Programming, Wadern, Germany, April 1-4, 2013. ©1

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