Friedrich-Alexander-Universität DruckenUnivisEnglish FAU-Logo
Techn. Fakultšt Willkommen am Department Informatik FAU-Logo
Codesign
Lehrstuhl fŁr Informatik 12
M. Akif Özkan
Department Informatik  >  Informatik 12  >  Personal  >  M. Akif Özkan

M. Akif Özkan
M. Sc.

Address: Akif Oezkan
Department of Computer Science 12
(Hardware-Software-Co-Design)
University of Erlangen-Nuremberg
Cauerstraße 11
D-91058 Erlangen
Germany
Room: 02.121
Phone: +49 9131 85-67306
Fax: +49 9131 85-25149
Email: akif.oezkan(at)fau.de

Curriculum Vitae

Since 2015 Researcher at the Department of Computer Science 12 (Hardware/Software Co-Design),
University of Erlangen-Nuremberg, Germany
2014 - 2015 Researcher, Department of EE, Özyegin University, Turkey
2012 - 2013 Exchange Student, KU Leuven, Belgium
2011 - 2014 M. Sc. in Electronics Engineering, Istanbul Technical University, Turkey
2007 - 2011 B. Sc. in Electronics Engineering, Istanbul Technical University, Turkey
July, 1989 Born in Ankara, Turkey

Research Interests

Embedded System Design, System-on-Chip (SoC) ASIC and FPGA Design
Heterogeneous Architectures for Image Systems

Teaching

WS 2016/2017 Praktikum: Entwicklung interaktiver eingebetteter Systeme (EES)

Open Theses

Analyzing Optical Flow Algorithms
DSL-Based Optimization of FPGA Implementations

Publications

2017
3 O. Reiche, M. ÷zkan, F. Hannig, J. Teich and M. Schmid.
Loop Parallelization Techniques for FPGA Accelerator Synthesis.
In Journal of Signal Processing Systems (JSPS), 2017. ©1
[doi>10.1007/s11265-017-1229-7]
2016
2 M. ÷zkan, O. Reiche, F. Hannig and J. Teich.
FPGA-Based Accelerator Design from a Domain-Specific Language.
In Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL), pp. 1-9, Lausanne, Switzerland, August 29-September 2, 2016. ©1
[doi>10.1109/FPL.2016.7577357]
1 K. Hšublein, M. Reichenbach, O. Reiche, M. ÷zkan, D. Fey, F. Hannig and J. Teich.
Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures.
In Proceedings of the 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), pp. 211-218, Island of Samos, Greece, July 18-21, 2016. ©1
[doi>10.1109/SAMOS.2016.7818350]

Misc.

2016
1 M. ÷zkan, O. Reiche, F. Hannig and J. Teich.
FPGA-Based Accelerator Design from a Domain-Specific Language.
Talk, International Conference on Field-Programmable Logic and Applications (FPL), Lausanne, Switzerland, August 29-September 2, 2016. ©1

Copyrights:
©1The documents distributed by this server have been provided by the contributing authors as a means to ensure timely dissemination of scholarly and technical work on a noncommercial basis. Copyright and all rights therein are maintained by the authors or by other copyright holders, notwithstanding that they have offered their works here electronically. It is understood that all persons copying this information will adhere to the terms and constraints invoked by each author's copyright. These works may not be reposted without the explicit permission of the copyright holder.
©2©2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
©3©2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
  Impressum Stand: 21 September 2016.   A.O.