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Lehrstuhl für Informatik 12
Richard Membarth
Curriculum Vitæ
Awards
Research
Open Source
Projects
Education
Tutorials
Publications
Misc.
Thesis
Department Informatik  >  Informatik 12  >  Personal  >  Richard Membarth

Richard Membarth
Dr.-Ing.

Richard Membarth
Mt. Ngauruhoe (New Zealand)
Address:
I'm now at Saarland University:

https://graphics.cg.uni-saarland.de/people/membarth

Email: richard.membarth@informatik.uni-erlangen.de
PGP/GPG-Key: FD108540

Curriculum Vitæ

07/2013 Postdoctoral Researcher at the Intel Visual Computing Institute (Computer Graphics Lab), Saarland University, Germany
05/2013 Doctorate degree (Dr.-Ing.) in Computer Science, University of Erlangen-Nuremberg, Germany
10/2008 Researcher at the Department of Computer Science (Hardware/Software Co-Design), University of Erlangen-Nuremberg, Germany
09/2008 Diploma degree in Computer Science, University of Erlangen-Nuremberg, Germany
10/2007 Postgraduate Diploma in Computer and Information Sciences, Auckland University of Technology, New Zealand
March 03, 1983 born in Gunzenhausen, Germany

Awards and Distinctions

2010: HiPEAC Fellowship for Internship at ARM Cambridge, UK
2008: NVIDIA CUDA Challenge: 1st Prize

Research Projects

Multi-core Architectures and Programming
InvasIC: Invasive Algorithms, Architectures, and Programming
ExaStencils: Advanced Stencil-Code Engineering
Heterogeneous Image Systems

Research Interests

Parallel Architectures: Kepler, Fermi, Tesla, Tile Processor (Tilera), Cell B.E., Intel MIC, ARM Mali, ImgTec PowerVR
Parallel Programming Models for Multi-core Systems: OpenMP, Cilk++, Threading Building Blocks, RapidMind, OpenCL, Cell SDK, Tilera MDE, MPI
Parallel Programming Models for Many-core Systems: CUDA, OpenCL, Renderscript, RapidMind, PGI Accelerator, HMPP Workbench
Source-to-Source Compilation for Automatic Parallelization
Domain Specific Languages
Medical Imaging
GNU/Linux

Projects

HIPAcc — The Heterogeneous Image Processing Acceleration Framework
HIPAcc Framework
Website: HIPAcc website Sources: HIPAcc hosted by SourceForge.net


Detector Defect Correction on Graphics Processors 2D/3D Image Registration on Multi-core and Many-core Architectures
Image Conditioning 2D/3D Image Registration

Open Source Projects

HIPAcc - The Heterogeneous Image Processing Acceleration Framework
CUDA Challenge - Gimp Plugin using CUDA: Multiresolution Gradient Adaptive Filter

Education

Multi-core Architectures and Programming
Parallel Systems

Tutorials

2011: One day Seminar on CUDA as part of the summer academy on "Parallel Systems" (Georg Simon Ohm University of Applied Sciences, Germany)
2009: Two day Seminar on CUDA (University of Patras, Greece)

Publications  Google scholar

2016
22 R. Membarth, O. Reiche, F. Hannig, J. Teich, M. Körner and W. Eckert.
HIPAcc: A Domain-Specific Language and Compiler for Image Processing.
IEEE Transactions on Parallel and Distributed Systems, 27(1), pp. 210-224, 2016. ©3
[doi>10.1109/TPDS.2015.2394802]
2014
21 R. Membarth, O. Reiche, C. Schmitt, F. Hannig, J. Teich, M. Stürmer and H. Köstler.
Towards a Performance-portable Description of Geometric Multigrid Algorithms using a Domain-specific Language.
In Journal of Parallel and Distributed Computing (JPDC). 74(12), pp. 3191-3201, 2014. ©1
[doi>10.1016/j.jpdc.2014.08.008]
20 O. Reiche, M. Schmid, F. Hannig, R. Membarth and J. Teich.
Code Generation from a Domain-specific Language for C-based HLS of Hardware Accelerators.
In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New Dehli, India, October 12-17, 2014. ©1
[doi>10.1145/2656075.2656081]
19 R. Membarth, O. Reiche, F. Hannig and J. Teich.
Code Generation for Embedded Heterogeneous Architectures on Android.
In Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pp. 86:1-86:6, Dresden, Germany, March 24-28, 2014. ©3
[doi>10.7873/DATE.2014.099]
2013
18 R. Membarth.
Code Generation for GPU Accelerators from a Domain-Specific Language for Medical Imaging.
Dissertation, University of Erlangen-Nuremberg, ISBN 978-3-8439-1074-3, Verlag Dr. Hut, Munich, Germany, May 2, 2013. ©1
2012
17 R. Membarth, F. Hannig, J. Teich and H. Köstler.
Towards Domain-specific Computing for Stencil Codes in HPC.
In Proceedings of the 2nd International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC), pp. 1133-1138, Salt Lake City, UT, USA, November 16, 2012. ©3
[doi>10.1109/SC.Companion.2012.136]
16 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Mastering Software Variant Explosion for GPU Accelerators.
In Proceedings of the 10th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar), pp. 123-132, Rhodes Island, Greece, August 27, 2012. ©1
[doi>10.1007/978-3-642-36949-0_15]
15 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators based on a Domain-Specific Language for Medical Imaging.
In Proceedings of the 11th International Symposium on Parallel and Distributed Computing (ISPDC), pp. 211-218, Munich, Germany, June 25-29, 2012. ©3
[doi>10.1109/ISPDC.2012.36]
14 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Generating Device-specific GPU Code for Local Operators in Medical Imaging.
In Proceedings of the 26th IEEE International Parallel & Distributed Processing Symposium (IPDPS), pp. 569-581, Shanghai, China, May 21-25, 2012. ©3
[doi>10.1109/IPDPS.2012.59]
13 R. Membarth, J. Lupp, F. Hannig, J. Teich, M. Körner and W. Eckert.
Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging.
In Proceedings of the 25th International Conference on Architecture of Computing Systems (ARCS), pp. 147-159, Munich, Germany, February 28 - March 02, 2012. ©1
[doi>10.1007/978-3-642-28293-5_13]
2011
12 R. Membarth, A. Lokhmotov and J. Teich.
Generating GPU Code from a High-level Representation for Image Processing Kernels.
In Proceedings of the 5th Workshop on Highly Parallel Processing on a Chip (HPPC), pp. 270-280, Bordeaux, France, August 30, 2011. ©1
[doi>10.1007/978-3-642-29737-3_31]
11 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Frameworks for GPU Accelerators: A Comprehensive Evaluation using 2D/3D Image Registration.
In Proceedings of the 9th IEEE Symposium on Application Specific Processors (SASP), pp. 78-81, San Diego, CA, USA, June 5-6, 2011. ©3
[doi>10.1109/SASP.2011.5941083]
10 R. Membarth, H. Dutta, F. Hannig and J. Teich.
Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards.
In Transactions on High-Performance Embedded Architectures and Compilers (Transactions on HiPEAC), 5(3), 2011. ©3
9 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Frameworks for Multi-core Architectures: A Comprehensive Evaluation using 2D/3D Image Registration.
In Proceedings of the 24th International Conference on Architecture of Computing Systems (ARCS), pp. 62-73, Lake Como, Italy, February 22-25, 2011. ©1
[doi>10.1007/978-3-642-19137-4_6]
8 R. Membarth, F. Hannig, J. Teich, G. Litz and H. Hornegger.
Detector Defect Correction of Medical Images on Graphics Processors.
In Proceedings of the SPIE: Medical Imaging 2011: Image Processing, pp. 79624M 1-12, Lake Buena Vista, Orlando, FL, USA, February 12-17, 2011. ©1
[doi>10.1117/12.877656]
2010
7 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Comparison of Parallelization Frameworks for Shared Memory Multi-Core Architectures.
In Proceedings of the Embedded World Conference, Nuremberg, Germany, March 03-05, 2010. ©1
2009
6 N. Sarkar and R. Membarth.
Modeling and Simulation of IEEE 802.11g using OMNeT++.
In Handbook of Research on Discrete Event Simulation Environments: Technologies and Applications, pp. 379-397, Information Science Reference, Hershey, PA, October, 2009. ©1
[doi>10.4018/978-1-60566-774-4.ch017]
5 F. Arifin, R. Membarth, A. Amouri, F. Hannig and J. Teich.
FSM-Controlled Architectures for Linear Invasion.
In Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 59-64, Florianópolis, Brazil, October 12-14, 2009. ©2
[doi>10.1109/VLSISOC.2009.6041331]
4 R. Membarth, F. Hannig, H. Dutta and J. Teich.
Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors.
In Proceedings of the 9th International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS Workshop), pp. 277-288, July 20-23, 2009. ©1
[doi>10.1007/978-3-642-03138-0_31]
3 R. Membarth, F. Hannig, H. Dutta and J. Teich.
Optimization Flow for Algorithm Mapping on Graphics Cards.
In Proceedings of ACACES 2009 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems, pp. 229-232, Barcelona, Spain, July 12-18, 2009. ©1
2 R. Membarth, P. Kutzer, H. Dutta, F. Hannig and J. Teich.
Acceleration of Multiresolution Imaging Algorithms: A Comparative Study.
In Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 211-214, Boston, MA, USA, July 7-9, 2009. ©2
[doi>10.1109/ASAP.2009.8]
2006
1 K. Köker, R. Membarth and R. German.
Performance Analyses of Embedded Real-Time Operating Systems Using High-Precision Counters.
In Proceedings of the 3rd International Conference on Autonomous Robots and Agents (ICARA), pp 485-490, Palmerston North, New Zealand, December 12-14, 2006. ©2

Misc.

2014
8 R. Membarth and O. Reiche.
HIPAcc: A Domain-Specific Language and Compiler for Image Processing.
Poster Presentation at the GPU Technology Conference (GTC), San Jose, CA, USA, March 24-27, 2014. ©1
7 O. Reiche, R. Membarth, F. Hannig and J. Teich.
Automatic GPU Code Generation for Android.
Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March 24-28, 2014. ©1
2013
6 R. Membarth.
Code Generation for GPU Accelerators in the Domain of Image Preprocessing.
Talk at the 2nd German Heterogeneous Computing Group (GHCG) Meeting, Aachen, Germany, May 24, 2013. ©1
2012
5 R. Membarth.
Code Generation for GPU Accelerators in Medical Imaging.
Invited Talk at the Symposium on Personal High-Performance Computing (PHPC), Brussels, Belgium, December 13, 2012. ©1
4 R. Membarth.
Automatic Code Generation for Image Processing Algorithms on Accelerators in Heterogeneous Architectures.
Talk, Intel GmbH, Braunschweig, Germany, September 20, 2012. ©1
3 M. Körner, W. Eckert, R. Membarth, F. Hannig and J. Teich.
Entwicklungsframeworks für Mehrkernarchitekturen und Grafikprozessoren: Evaluierung anhand eines Algorithmus zur Registrierung von 3D- mit 2D-Bilddaten.
Talk at the Conference for Parallel Programming, Concurrency, and Multi-core Systems (parallel), Karlsruhe, Germany, May 23-25, 2012. ©1
2011
2 W. Eckert and R. Membarth.
Frameworks for Multicore Architectures and GPU Accelerators: A Comprehensive Evaluation using 2D/3D Image Registration.
Talk at the Conference Multicore@Siemens, Erlangen, Germany, November 15-16, 2011. ©1
1 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Domain-specific Computing and Code Generation for Medical Imaging.
Poster Presentation at the 2nd Programming and Tuning Massively Parallel Systems Summer School (PUMPS), Barcelona, Spain, July 18-22, 2011. ©1

Thesis

2008
2 R. Membarth.
Efficient Mapping Methodology for Medical Image Processing on GPUs.
Diploma thesis (Diplomarbeit), Department of Computer Science, University of Erlangen-Nuremberg, Germany, September 2008 . ©1
2006
1 R. Membarth.
Messung der Quality of Service (QoS)-Parameter eines embedded-Linux-Systems mit Echtzeit Erweiterung (RTAI).
Pre-Master's thesis (Studienarbeit), Department of Computer Science, University of Erlangen-Nuremberg, Germany, January 2006. ©1

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  Impressum Stand: 13 May 2014.   R.M.