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Frank Hannig
Department Informatik  >  Informatik 12  >  Personal  >  Frank Hannig

Frank Hannig

Dr.-Ing.

Address:
Department of Computer Science 12
Hardware-Software-Co-Design
Friedrich-Alexander University Erlangen-Nürnberg (FAU)
Cauerstr. 11
91058 Erlangen
Germany
Phone: +49 9131 85-25153
Fax: +49 9131 85-25149
Email: hannig [at] cs [.] fau [.] de">hannig [at] cs [.] fau [.] de
Frank Hannig
Curriculum Vitæ
CV
March, 1974 born in Verl, Germany
2000 Diploma degree in EE/CS (interdisciplinary course of study), University of Paderborn, Germany
11/2000 - 12/2002 Researcher at the Computer Engineering Laboratory (Institute DATE), University of Paderborn
since 01/2003 Researcher at the Department of Computer Science 12 (Hardware-Software-Co-Design), University of Erlangen-Nuremberg, Germany
since 2004 Head of the Architecture and Compiler Design Group at the Department of Computer Science 12 (Hardware-Software-Co-Design), University of Erlangen-Nuremberg, Erlangen, Germany
08/2009 Dr.-Ing. degree in CS, University of Erlangen-Nuremberg, Erlangen, Germany
Experience
C-LAB,
Paderborn, Germany
01/1997 - 04/1999
Working student at C-LAB (Cooperative Computing & Communication Laboratory) in the research of analysing crosstalk noise problems during the design of digital high-speed integrated circuits
Electrolux,
Fredericia, Denmark
04/1999 - 09/1999
Practical training at Electrolux GPDH Tech-Centre, primary development, hardware/software co-design of electrical hobs
C-LAB,
Paderborn, Germany
10/1999 - 04/2000
Working student at C-LAB in the research group OIT (Optical Interconnection Technology)
Professional Scientific Activities
Recent and Upcoming Events
DATE 2017 – Topic Chair E2: Compilers and Software Synthesis for Embedded Systems
Conference on Design, Automation and Test in Europe (DATE), Lausanne, Switzerland, March 27-31, 2017
ARCS 2016 – Program Chair
29th GI/ITG International Conference on Architecture of Computing Systems (ARCS), Nuremberg, Germany, April 4-7, 2016
DATE 2016 – Topic Co-Chair E2: Compilers and Software Synthesis for Embedded Systems
Conference on Design, Automation and Test in Europe (DATE), Dresden, Germany, March 14-18, 2016
Guest Editor: Special Issue on Heterogeneous Real-Time Image Processing
Journal of Real-Time Image Processing – Springer
Conference and Workshop Organization
General Co-Chair, FSP 2015 – Second International Workshop on FPGAs for Software Programmers, co-located with International Conference on Field Programmable Logic and Applications (FPL)
Initiator and General Co-Chair, HIS 2015 – DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems, co-located with Conference on Design, Automation and Test in Europe (DATE)
Initiator and General Co-Chair, FSP 2014 – First International Workshop on FPGAs for Software Programmers, co-located with International Conference on Field Programmable Logic and Applications (FPL)
Co-Organizer and Program Chair, Racing 2014 – Workshop on Resource-Awareness and Adaptivity in Multi-Core Computing, co-located with IEEE European Test Symposium (ETS)
Publication Chair, ASAP 2011 – 21th IEEE International Conference on Application-specific Systems, Architectures and Processors
Publication Chair, ASAP 2010 – 21th IEEE International Conference on Application-specific Systems, Architectures and Processors
Organization Assistance, CODES+ISSS 2007 – International Conference on Hardware-Software Codesign and System Synthesis
Organization Assistance, Euro-Par 2006 – European Conference on Parallel Computing
Organization Assistance, ARCS 2006 – 19th International Conference on Architecture of Computing Systems
Program Committee Member
2017
ARC 2017 – International Symposium on Applied Reconfigurable Computing
DATE 2017 – Conference on Design, Automation and Test in Europe
SAC 2017 – 32nd ACM/SIGAPP Symposium On Applied Computing, Embedded Systems Track
2016
ARC 2016 – International Symposium on Applied Reconfigurable Computing
ASAP 2016 – 27th IEEE International Conference on Application-specific Systems, Architectures and Processors
ASR-MOV 2016 – International Workshop on Architectures and Systems for Real-time Mobile Vision applications
CODES+ISSS 2016 – International Conference on Hardware/Software Codesign and System Synthesis
DASIP 2016 – Conference on Design and Architectures for Signal and Image Processing
DATE 2016 – Conference on Design, Automation and Test in Europe
FSP 2016 – Third International Workshop on FPGAs for Software Programmers
DLMCS 2016 – Workshop on Data Locality in Modern Computing Systems
ISC 2016 – International Supercomputing Conference
SAC 2016 – 31st ACM/SIGAPP Symposium On Applied Computing, Embedded Systems Track
SAMOS 2016 – International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
SCOPES 2016 – 19th International Workshop on Software and Compilers for Embedded Systems
UCHPC 2016 – 9th Workshop on UnConventional High Performance Computing in conjunction with Euro-Par 2016
VLSID 2016 – 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, Track D1: System-level Design
2015
ARC 2015 – International Symposium on Applied Reconfigurable Computing
ASAP 2015 – 26th IEEE International Conference on Application-specific Systems, Architectures and Processors
CODES+ISSS 2015 – International Conference on Hardware/Software Codesign and System Synthesis
DASIP 2015 – Conference on Design and Architectures for Signal and Image Processing
DATE 2015 – Conference on Design, Automation and Test in Europe
HiStencils 2015 – 2nd International Workshop on High-Performance Stencil Computations
ISC 2015 – International Supercomputing Conference
SAC 2015 – 30th ACM/SIGAPP Symposium On Applied Computing, Embedded Systems Track
SAMOS 2015 – International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
SCOPES 2015 – 18th International Workshop on Software and Compilers for Embedded Systems
UCHPC 2015 – 8th Workshop on UnConventional High Performance Computing in conjunction with Euro-Par 2015
2014
ARC 2014 – International Symposium on Applied Reconfigurable Computing
ASAP 2014 – 25th IEEE International Conference on Application-specific Systems, Architectures and Processors
CODES+ISSS 2014 – International Conference on Hardware/Software Codesign and System Synthesis
DASIP 2014 – Conference on Design and Architectures for Signal and Image Processing
DATE 2014 – Conference on Design, Automation and Test in Europe
EUC 2014 – The 12th IEEE International Conference on Embedded and Ubiquitous Computing
HiStencils 2014 – 1st International Workshop on High-Performance Stencil Computations
ISC 2014 – International Supercomputing Conference
ODES 2014 – 11th Workshop on Optimizations for DSP and Embedded Systems
SAC 2014 – 29th ACM Symposium on Applied Computing, Embedded Systems Track
UCHPC 2014 – 7th Workshop on UnConventional High Performance Computing in conjunction with Euro-Par 2014
2013
ARC 2013 – International Symposium on Applied Reconfigurable Computing
ASAP 2013 – 24th IEEE International Conference on Application-specific Systems, Architectures and Processors
CODES+ISSS 2013 – International Conference on Hardware/Software Codesign and System Synthesis
DASIP 2013 – Conference on Design and Architectures for Signal and Image Processing
DATE 2013 – Conference on Design, Automation and Test in Europe
ISC 2013 – International Supercomputing Conference
SAC 2013 – 28th ACM Symposium on Applied Computing, Embedded Systems Track
UCHPC 2013 – 6th Workshop on UnConventional High Performance Computing in conjunction with Euro-Par 2013
2012
ASAP 2012 – 23rd IEEE International Conference on Application-specific Systems, Architectures and Processors
CODES+ISSS 2012 – International Conference on Hardware/Software Codesign and System Synthesis
DASIP 2012 – Conference on Design and Architectures for Signal and Image Processing
DATE 2012 – Conference on Design, Automation and Test in Europe
ERSA 2012 – International Conference on Engineering of Reconfigurable Systems and Algorithms
SAC 2012 – 27th ACM Symposium on Applied Computing, Embedded Systems Track
SIES 2012 – 7th IEEE International Symposium on Industrial Embedded Systems, Work-in-Progress Session
2011
ASAP 2011 – 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors
CODES+ISSS 2011 – International Conference on Hardware/Software Codesign and System Synthesis
DASIP 2011 – Conference on Design and Architectures for Signal and Image Processing
DATE 2011 – Conference on Design, Automation and Test in Europe
ERSA 2011 – International Conference on Engineering of Reconfigurable Systems and Algorithms
2010
ASAP 2010 – 21st IEEE International Conference on Application-specific Systems, Architectures and Processors
DASIP 2010 – Conference on Design and Architectures for Signal and Image Processing
ERSA 2010 – International Conference on Engineering of Reconfigurable Systems and Algorithms
2009
DASIP 2009 – Conference on Design and Architectures for Signal and Image Processing
ERSA 2009 – International Conference on Engineering of Reconfigurable Systems and Algorithms
2008
DASIP 2008 – Conference on Design and Architectures for Signal and Image Processing
ERSA 2008 – International Conference on Engineering of Reconfigurable Systems and Algorithms
2007
DASIP 2007 – Workshop on Design and Architectures for Signal and Image Processing
ERSA 2007 – International Conference on Engineering of Reconfigurable Systems and Algorithms
Reviewing — Journals
ACM TECS – ACM Transactions on Embedded Computing Systems
ACM TODAES – ACM Transactions on Design Automation of Electronic Systems
IEEE SPM – IEEE Signal Processing Magazine
IEEE TVLSI – IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE TSP – IEEE Transactions on Signal Processing
IEEE TCAD – IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Design & Test – IEEE Design & Test of Computers
EURASIP Journal on Embedded Systems
Microprocessors and Microsystems
Reviewing — Conferences, Symposia, and Workshops (selection, in addition to TPC memberships)
DAC (expert reviewer), ICCAD, CASES, SAMOS, ARCS, FPT, FPL, RAW, PARELEC, SiPS
Memberships
Member of the IEEE since 2001 and Senior Member since 2012
Affiliate member of the European Network of Excellence (NoE) on High Performance and Embedded Architecture and Compilation (HiPEAC)
Member of the HiPEAC Reconfigurable Computing Cluster
Research Projects
Ongoing
InvasIC: DFG Transregional Collaborative Research Centre 89 — Invasive Computing
ExaStencils: Advanced Stencil-Code Engineering within the DFG Priority Programme 1648 (Software for Exascale Computing)
HBS: DFG Research Training Group (Graduiertenkolleg) 1773 Heterogeneous Image Systems, Project B3
INI.FAU: Parallelization and Resource Estimation of Algorithms for Heterogeneous DAS Architectures
PARO: Architecture/Compiler Co-Design of Massively Parallel Processor Architectures
MAP: Multi-core Architectures and Programming
Open Source Projects
HIPAcc: A Domain-Specific Language and Compiler for Image Processing Applications
Completed
MMSys: Motion Management System
CoMap: Co-Design of Massively Parallel Embedded Processor Architectures
DFG SFB 376Massively Parallel Computation
BUILDABONG: Architecture and Compiler Design for ASIPs
Education
Lectures
Domain-Specific and Resource-Aware Computing on Multicore Architectures
Parallel Systems
Embedded Systems
Exercises
Domain-Specific and Resource-Aware Computing on Multicore Architectures
Parallel Systems
Embedded Systems
Hardware-Software-Co-Design
Architecture and Design of Embedded Systems (University of Paderborn)
Seminars
Multi-Core Architectures and Programming
Oberseminar: Hardware-Software-Co-Design
Energy Efficient Systems
Bluetooth (University of Paderborn)
Labs
Unix Basics (University of Paderborn)
Architecture Synthesis (University of Paderborn)
Publications
Statistics
h-index (Web of Science): 5
h-index (Scopus): 9
h-index (Google Scholar): 17
Erdös Number: 3 (via this path: Frank Hannig → Sándor P. Fekete → Aviezri S. Fraenkel → Paul Erdös)

All Publications

202

article

Vivek Singh Bhadouria, Alexandru Tanase, Moritz Schmid, Frank Hannig, Jürgen Teich, and Dibyendu Ghoshal.

A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators.

To appear in Journal of Signal Processing Systems,

2016.

201

inproceedings

Jörg Fickenscher, Oliver Reiche, Jens Schlumberger, Frank Hannig, and Jürgen Teich.

Modeling, Programming and Performance Analysis of Automotive Environment Map Representations on Embedded GPUs.

To appear in Proceedings of the 18th IEEE International High-Level Design Validation and Test Workshop (HLDVT),

IEEE, Santa Cruz, CA, USA, October 7-8, 2016.

200

article

Christian Schmitt, Moritz Schmid, Sebastian Kuckuk, Harald Köstler, Jürgen Teich, and Frank Hannig.

Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution.

To appear in Parallel Processing Letters,

2016.

199

article

Santiago Pagani, Lars Bauer, Qingqing Chen, Elisabeth Glocker, Frank Hannig, Andreas Herkersdorf, Heba Khdr, Anuj Pathania, Ulf Schlichtmann, Doris Schmitt-Landsiedel, Mark Sagi, Éricles R. Sousa, Philipp Wagner, Volker Wenzel, Thomas Wild, and Jörg Henkel.

Dark Silicon Management: An Integrated and Coordinated Cross-Layer Approach.

it - Information Technology,

2016.

198

inproceedings

M. Akif Özkan, Oliver Reiche, Frank Hannig, and Jürgen Teich.

FPGA-based Accelerator Design from a Domain-Specific Language.

To appear in Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL),

Lausanne, Switzerland, August 29-September 2, 2016.

197

article

Heba Khdr, Santiago Pagani, Éricles R. Sousa, Vahid Lari, Anuj Pathania, Frank Hannig, Muhammad Shafique, Jürgen Teich, and Jörg Henkel.

Power Density-Aware Resource Management for Heterogeneous Tiled Multicores.

To appear in IEEE Transactions on Computers (TC),

PP(99), 14 pages, 2016.

196

inproceedings

Konrad Häublein, Marc Reichenbach, Oliver Reiche, M. Akif Özkan, Dietmar Fey, Frank Hannig, and Jürgen Teich.

Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures.

In Proceedings of the 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS),

Island of Samos, Greece, July 18-21, 2016.

195

inproceedings

Michael Witterauf, Alexandru Tanase, Frank Hannig, and Jürgen Teich.

Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays.

In Proceedings of the 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP),

IEEE, London, United Kingdom, July 6-8, 2016.

194

inproceedings

Sascha Roloff, Alexander Pöppl, Tobias Schwarzer, Stefan Wildermann, Michael Bader, Michael Glaß, Frank Hannig, and Jürgen Teich.

ActorX10: An Actor Library for X10.

In Proceedings of the Sixth ACM SIGPLAN X10 Workshop (X10),

pp. 24-29, ACM, Santa Barbara, CA, USA, June 14, 2016.

193

book

Dirk Koch, Frank Hannig, and Daniel Ziener.

FPGAs for Software Programmers.

327 pages, Springer, 2016, ISBN 978-3-319-26406-6.

192

inbook

Frank Hannig.

A Quick Tour of High-Level Synthesis Solutions for FPGAs.

In Dirk Koch, Frank Hannig, and Daniel Ziener, editors, FPGAs for Software Programmers,

chapter 3, pp. 49-59. Springer, 2016.

191

inbook

Dirk Koch, Daniel Ziener, and Frank Hannig.

FPGA versus Software Programming: Why, When, and How?.

In Dirk Koch, Frank Hannig, and Daniel Ziener, editors, FPGAs for Software Programmers,

chapter 1, pp. 1-21. Springer, 2016.

190

inbook

Moritz Schmid, Oliver Reiche, Frank Hannig, and Jürgen Teich.

HIPAcc.

In Dirk Koch, Frank Hannig, and Daniel Ziener, editors, FPGAs for Software Programmers,

chapter 12, pp. 205-223. Springer, 2016.

189

inbook

Moritz Schmid, Christian Schmitt, Frank Hannig, Gorker Alp Malazgirt, Nehir Sönmez, Arda Yurdakul, and Adrián Cristal.

Big Data and HPC Acceleration with Vivado HLS.

In Dirk Koch, Frank Hannig, and Daniel Ziener, editors, FPGAs for Software Programmers,

chapter 7, pp. 115-136. Springer, 2016.

188

proceedings

Frank Hannig, João M. P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, and Jürgen Teich.

Proceedings of the 29th International Conference on Architecture of Computing Systems (ARCS).

volume 9637 of Lecture Notes in Computer Science (LNCS), 402 pages, Springer, 2016, ISBN 978-3-319-30694-0.

187

unpublished

Sascha Roloff, Frank Hannig, and Jürgen Teich.

InvadeSIM: A Simulator for Heterogeneous Multi-Processor Systems-on-Chip.

Tool Presentation at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March 14-18, 2016.

186

unpublished

Alexandru Tanase, Michael Witterauf, Éricles R. Sousa, Vahid Lari, Frank Hannig, and Jürgen Teich.

LoopInvader: A Compiler for Tightly Coupled Processor Arrays.

Tool Presentation at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March 14-18, 2016.

185

incollection

Christian Schmitt, Sebastian Kuckuk, Frank Hannig, Jürgen Teich, Harald Köstler, Ulrich Rüde, and Christian Lengauer.

Systems of Partial Differential Equations in ExaSlang.

To appear in Software for Exascale Computing - SPPEXA 2013-2015,

Volume 113 of Lecture Notes in Computational Science and Engineering, Springer, 2016.

184

article

Richard Membarth, Oliver Reiche, Frank Hannig, Jürgen Teich, Mario Körner, and Wieland Eckert.

HIPAcc: A Domain-Specific Language and Compiler for Image Processing.

IEEE Transactions on Parallel and Distributed Systems,

27(1), pp. 210-224, 2016.

183

article

Frank Hannig and Andreas Herkersdorf.

Introduction to the Special Issue on Testing, Prototyping, and Debugging of Multi-Core Architectures.

Journal of Systems Architecture,

61(10), p. 600, 2015.

182

article

Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles R. Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, and Jörg Henkel.

Resource-Awareness on Heterogeneous MPSoCs for Image Processing.

Journal of Systems Architecture,

61(10), pp. 668-680, 2015.

181

inproceedings

Éricles R. Sousa, Frank Hannig, and Jürgen Teich.

Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays.

In Proceedings of the 5th IFIP International Embedded Systems Symposium (IESS),

Foz do Iguaçu, Brazil, November 3-6, 2015,
In Lecture Notes in Computer Science (LNCS), Springer, 2015.

180

article

Oliver Reiche, Konrad Häublein, Marc Reichenbach, Moritz Schmid, Frank Hannig, Jürgen Teich, and Dietmar Fey.

Synthesis and Optimization of Image Processing Accelerators using Domain Knowledge.

Journal of Systems Architecture,

61(10), pp. 646-658, 2015.

179

inproceedings

Sascha Roloff, Stefan Wildermann, Frank Hannig, and Jürgen Teich.

Invasive Computing for Predictable Stream Processing: A Simulation-based Case Study.

In Proceedings of the 13th IEEE Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia),

2 pages, IEEE, Amsterdam, The Netherlands, October 8-9, 2015.

178

inproceedings

Alexandru Tanase, Michael Witterauf, Jürgen Teich, and Frank Hannig.

Symbolic Loop Parallelization for Balancing I/O and Memory Accesses on Processor Arrays.

In Proceedings of the 13th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE),

pp. 188-197, IEEE, Austin, TX, USA, September 21-23, 2015.

177

proceedings

Frank Hannig, Dirk Koch, and Daniel Ziener.

Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015).

104 pages, London, United Kingdom, 2015. arXiv: 1508.06320 [cs.AR].

176

inproceedings

Moritz Schmid, Oliver Reiche, Frank Hannig, and Jürgen Teich.

Loop Coarsening in C-based High-Level Synthesis.

In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP),

pp. 166-173, IEEE, Toronto, Canada, July 27-29, 2015.

175

inproceedings

Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig, and Vahid Lari.

On-Demand Fault-Tolerant Loop Processing on Massively Parallel Processor Arrays.

In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP),

pp. 194-201, IEEE, Toronto, Canada, July 27-29, 2015.

174

inproceedings

Michael Witterauf, Alexandru Tanase, Frank Hannig, and Jürgen Teich.

Adaptive Fault Tolerance in Tightly Coupled Processor Arrays with Invasive Computing.

In Proceedings of ACACES 2015 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems,

pp. 205-208, HiPEAC, Fiuggi, Italy, July 12-18, 2015.

173

inproceedings

Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, and Brett H. Meyer.

A Co-Design Approach for Fault-Tolerant Loop Execution on Coarse-Grained Reconfigurable Arrays.

In Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS),

8 pages, IEEE, Montréal, Quebec, Canada, June 15-18, 2015.

172

inproceedings

Sascha Roloff, David Schafhauser, Frank Hannig, and Jürgen Teich.

Execution-driven Parallel Simulation of PGAS Applications on Heterogeneous Tiled Architectures.

In Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), HiPEAC Paper Award,

pp. 44:1-44:6, ACM, San Francisco, CA, USA, June 7-11, 2015.

171

article

Harald Köstler, Christian Schmitt, Sebastian Kuckuk, Stefan Kronawitter, Frank Hannig, Jürgen Teich, Ulrich Rüde, and Christian Lengauer.

A Scala Prototype to Generate Multigrid Solver Implementations for Different Problems and Target Multi-Core Platforms.

To appear in International Journal of Computational Science and Engineering,

2015.

170

inproceedings

Éricles R. Sousa, Frank Hannig, Jürgen Teich, Qingqing Chen, and Ulf Schlichtmann.

Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays.

In Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES),

pp. 121-124, ACM, St. Goar, Germany, June 1-3, 2015.

169

incollection

Jürgen Teich, Srinivas Boppu, Frank Hannig, and Vahid Lari.

Compact Code Generation and Throughput Optimization for Coarse-Grained Reconfigurable Arrays.

In Wayne Luk and George A. Constantinides, editors, Transforming Reconfigurable Systems: A Festschrift Celebrating the 60th Birthday of Professor Peter Cheung,

chapter 10, pp. 167-206. Imperial College Press, London, UK, 2015.

168

inproceedings

Oliver Reiche, Konrad Häublein, Marc Reichenbach, Frank Hannig, Jürgen Teich, and Dietmar Fey.

Automatic Optimization of Hardware Accelerators for Image Processing.

In Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS),

pp. 10-15, Grenoble, France, March 13, 2015. arXiv: 1502.07448 [cs.PL].

167

proceedings

Frank Hannig, Dietmar Fey, and Anton Lokhmotov.

Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015).

35 pages, Grenoble, France, 2015. arXiv: 1502.07241 [cs.AR].

166

inproceedings

Christian Schmitt, Moritz Schmid, Frank Hannig, Jürgen Teich, Sebastian Kuckuk, and Harald Köstler.

Generation of Multigrid-based Numerical Solvers for FPGA Accelerators.

In Armin Größlinger and Harald Köstler, editors, Proceedings of the 2nd International Workshop on High-Performance Stencil Computations (HiStencils),

pp. 9-15, Amsterdam, The Netherlands, January 20, 2015.

165

article

Sven Apel, Matthias Bolten, Armin Größlinger, Frank Hannig, Harald Köstler, Christian Lengauer, Ulrich Rüde, and Jürgen Teich.

ExaStencils: Advanced Stencil-Code Engineering.

inSiDE,

12(2), pp. 60-63, 2014.

164

inproceedings

Christian Schmitt, Sebastian Kuckuk, Frank Hannig, Harald Köstler, and Jürgen Teich.

ExaSlang: A Domain-Specific Language for Highly Scalable Multigrid Solvers.

In Proceedings of the 4th International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC),

pp. 42-51, IEEE Computer Society, New Orleans, LA, USA, November 17, 2014.

163

techreport

Adrian Tate, Amir Kamil, Anshu Dubey, Armin Größlinger, Brad Chamberlain, Brice Goglin, H. Carter Edwards, Chris J. Newburn, David Padua, Didem Unat, Emmanuel Jeannot, Frank Hannig, Tobias Gysi, Hatem Ltaief, James Sexton, Jesus Labarta, John Shalf, Karl Fürlinger, Kathryn O'Brien, Leonidas Linardakis, Maciej Besta, Marie-Christine Sawley, Mark Abraham, Mauro Bianco, Miquel Pericàs, Naoya Maruyama, Paul H. J. Kelly, Peter Messmer, Robert B. Ross, Romain Cledat, Satoshi Matsuoka, Thomas Schulthess, Torsten Hoefler, and Vitus J. Leung.

Programming Abstractions for Data Locality.

White Paper, PADAL Workshop 2014, April 28-29, Swiss National Supercomputing Center (CSCS), Lugano, Switzerland, November 2014.

162

inproceedings

Deepak Gangadharan, Éricles R. Sousa, Vahid Lari, Frank Hannig, and Jürgen Teich.

Application-driven Reconfiguration of Shared Resources for Timing Predictability of MPSoC Platforms.

In Proceedings of Asilomar Conference on Signals, Systems, and Computers (ACSSC),

pp. 398-403, IEEE, Pacific Grove, CA, USA, November 2-5, 2014.

161

article

Richard Membarth, Oliver Reiche, Christian Schmitt, Frank Hannig, Jürgen Teich, Markus Stürmer, and Harald Köstler.

Towards a Performance-portable Description of Geometric Multigrid Algorithms using a Domain-specific Language.

Journal of Parallel and Distributed Computing,

74(12), pp. 3191-3201, 2014.

160

inproceedings

Alexandru Tanase, Michael Witterauf, Jürgen Teich, and Frank Hannig.

Symbolic Inner Loop Parallelisation for Massively Parallel Processor Arrays.

In Proceedings of the 12th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE),

pp. 219-228, IEEE, Lausanne, Switzerland, October 19-21, 2014.

159

inproceedings

Oliver Reiche, Moritz Schmid, Frank Hannig, Richard Membarth, and Jürgen Teich.

Code Generation from a Domain-specific Language for C-based HLS of Hardware Accelerators.

In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS),

pp. 17:1-17:10, ACM, New Dehli, India, October 12-17, 2014.

158

inproceedings

Johny Paul, Walter Stechele, Éricles R. Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Manfred Kröhnert, and Tamim Asfour.

Self-Adaptive Harris Corner Detector on Heterogeneous Many-Core Processor.

In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP),

8 pages, IEEE, Madrid, Spain, October 8-10, 2014.

157

article

Alexander Grebhahn, Sebastian Kuckuk, Christian Schmitt, Harald Köstler, Norbert Siegmund, Sven Apel, Frank Hannig, and Jürgen Teich.

Experiments on Optimizing the Performance of Stencil Codes with SPL Conqueror.

Parallel Processing Letters,

24(3), 19 pages, 2014.

156

inproceedings

Moritz Schmid, Nicolas Apelt, Frank Hannig, and Jürgen Teich.

An Image Processing Library for C-based High-Level Synthesis.

In Proceedings of the 24th International Conference on Field Programmable Logic and Applications (FPL),

4 pages, IEEE, Munich, Germany, September 2-4, 2014.

155

inproceedings

Moritz Schmid, Oliver Reiche, Christian Schmitt, Frank Hannig, and Jürgen Teich.

Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs.

In Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP),

pp. 21-26, Munich, Germany, September 1, 2014. arXiv: 1408.4721 [cs.CV].

154

proceedings

Frank Hannig, Dirk Koch, and Daniel Ziener.

Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014).

82 pages, Munich, Germany, 2014. arXiv: 1408.4423 [cs.AR].

153

inproceedings

Éricles R. Sousa, Deepak Gangadharan, Frank Hannig, and Jürgen Teich.

Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures.

In Proceedings of the 17th Euromicro Conference on Digital Systems Design (DSD),

pp. 74-81, IEEE, Verona, Italy, August 27-29, 2014.

152

inproceedings

Christian Lengauer, Sven Apel, Matthias Bolten, Armin Größlinger, Frank Hannig, Harald Köstler, Ulrich Rüde, Jürgen Teich, Alexander Grebhahn, Stefan Kronawitter, Sebastian Kuckuk, Hannah Rittich, and Christian Schmitt.

ExaStencils: Advanced Stencil-Code Engineering.

In Proceedings of Euro-Par 2014: Parallel Processing Workshops,

Porto, Portugal, August 25-29, 2014,
volume 8806 of Lecture Notes in Computer Science (LNCS), pp. 553-564, Springer, 2014.

151

unpublished

Frank Hannig.

Loop Compilation Techniques for Coarse-Grained Reconfigurable Architectures.

Invited Talk, RWTH Aachen University, Germany, July 28, 2014.

150

article

Jürgen Teich, Alexandru Tanase, and Frank Hannig.

Symbolic Mapping of Loop Programs onto Processor Arrays.

Journal of Signal Processing Systems,

77(1-2), pp. 31-59, 2014.

149

inproceedings

Christian Schmitt, Sebastian Kuckuk, Harald Köstler, Frank Hannig, and Jürgen Teich.

An Evaluation of Domain-Specific Language Technologies for Code Generation.

In Proceedings of the 14th International Conference on Computational Science and its Applications (ICCSA),

pp. 18-26, IEEE Computer Society, Guimaraes, Portugal, June 30-July 3, 2014.

148

unpublished

Frank Hannig.

Mehr Produktivität und Portabilität durch domänenspezifische Programmiersprachen.

Invited Talk, University of Passau, Germany, June 24, 2014.

147

article

Harald Köstler, Christian Schmitt, Sebastian Kuckuk, Frank Hannig, Jürgen Teich, and Ulrich Rüde.

A Scala Prototype to Generate Multigrid Solver Implementations for Different Problems and Target Multi-Core Platforms.

The Computing Research Repository (CoRR),

18 pages, 2014. arXiv: 1406.5369 [cs.MS].

146

inproceedings

Moritz Schmid, Alexandru Tanase, Frank Hannig, Jürgen Teich, Vivek Singh Bhadouria, and Dibyendu Ghoshal.

Domain-Specific Augmentations for High-Level Synthesis.

In Proceedings of the 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP),

pp. 173-177, IEEE, Zurich, Switzerland, June 18-20, 2014.

145

techreport

Christian Lengauer, Sven Apel, Matthias Bolten, Armin Größlinger, Frank Hannig, Harald Köstler, Ulrich Rüde, Jürgen Teich, Alexander Grebhahn, Stefan Kronawitter, Sebastian Kuckuk, Hannah Rittich, and Christian Schmitt.

ExaStencils: Advanced Stencil-Code Engineering - First Project Report.

Department of Computer Science and Mathematics, University of Passau, June 2014.

144

article

Srinivas Boppu, Frank Hannig, and Jürgen Teich.

Compact Code Generation for Tightly-Coupled Processor Arrays.

Journal of Signal Processing Systems,

77(1-2), pp. 5-29, 2014.

143

proceedings

Frank Hannig and Jürgen Teich.

Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014).

62 pages, Paderborn, Germany, 2014. arXiv: 1405.2281 [cs.DC].

142

inproceedings

Vahid Lari, Alexandru Tanase, Frank Hannig, and Jürgen Teich.

Massively Parallel Processor Architectures for Resource-aware Computing.

In Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014),

pp. 1-7, Paderborn, Germany, May 29-30, 2014. arXiv: 1405.2907 [cs.AR].

141

unpublished

Frank Hannig.

Increasing Productivity and Performance Portability through Domain-Specific Languages.

Invited Talk at Workshop on Programming Abstractions for Data Locality (PADAL), Lugano, Switzerland, April 28-29, 2014.

140

article

Frank Hannig, Vahid Lari, Srinivas Boppu, Alexandru Tanase, and Oliver Reiche.

Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach.

ACM Transactions on Embedded Computing Systems (TECS),

13(4s), pp. 133:1-133:29, 2014.

139

incollection

Moritz Schmid, Frank Hannig, Alexandru Tanase, and Jürgen Teich.

High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model.

In Parallel Computing: Accelerating Computational Science and Engineering (CSE),

pp. 497-506. Volume 25 of Advances in Parallel Computing, IOS Press, Amsterdam, The Netherlands, 2014.

138

unpublished

Christian Schmitt, Frank Hannig, and Jürgen Teich.

A Multi-layered Domain-Specific Language for Stencil Computations.

Talk, Workshop ExaStencils 2014, Dresden, Germany, March 31, 2014.

137

inproceedings

Deepak Gangadharan, Alexandru Tanase, Frank Hannig, and Jürgen Teich.

Timing Analysis of a Heterogeneous Architecture with Massively Parallel Processor Arrays.

In Proceedings of the DATE Friday Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES),

ECSI, Dresden, Germany, March 28, 2014.

136

inproceedings

Richard Membarth, Oliver Reiche, Frank Hannig, and Jürgen Teich.

Code Generation for Embedded Heterogeneous Architectures on Android.

In Proceedings of the Conference on Design, Automation and Test in Europe (DATE),

pp. 86:1-86:6, European Design and Automation Association (EDAA), Dresden, Germany, March 24-28, 2014.

135

unpublished

Éricles R. Sousa, Vahid Lari, Johny Paul, Frank Hannig, Jürgen Teich, and Walter Stechele.

Resource-Aware Computer Vision Application on Heterogeneous Multi-Tile Architecture.

Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March 24-28, 2014.

134

unpublished

Oliver Reiche, Richard Membarth, Frank Hannig, and Jürgen Teich.

Automatic GPU Code Generation for Android.

Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March 24-28, 2014.

133

inproceedings

Sascha Roloff, Frank Hannig, and Jürgen Teich.

Towards Actor-oriented Programming on PGAS-based Multicore Architectures.

In Workshop Proceedings of the 27th International Conference on Architecture of Computing Systems (ARCS),

VDE Verlag, Lübeck, Germany, February 25-28, 2014.

132

inproceedings

Moritz Schmid, Markus Blocherer, Frank Hannig, and Jürgen Teich.

Real-Time Range Image Preprocessing on FPGAs.

In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig),

Cancun, Mexico, December 9-11, 2013.

131

unpublished

Markus Blocherer, Srinivas Boppu, Vahid Lari, Frank Hannig, and Jürgen Teich.

Transactor-based Debugging of Massively Parallel Processor Array Architectures.

Talk at 1st International Workshop on Multicore Application Debugging (MAD), Garching, Germany, November 14-15, 2013.

130

inproceedings

Éricles R. Sousa, Alexandru Tanase, Frank Hannig, and Jürgen Teich.

Accuracy and Performance Analysis of Harris Corner Computation on Tightly-Coupled Processor Arrays.

In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP),

pp. 88-95, IEEE, Cagliari, Italy, October 8-10, 2013.

129

inproceedings

Éricles R. Sousa, Alexandru Tanase, Frank Hannig, and Jürgen Teich.

A Prototype of an Adaptive Computer Vision Algorithm on an MPSoC Architecture.

In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP),

pp. 353-354, IEEE, Cagliari, Italy, October 8-10, 2013.

128

inproceedings

Alexandru Tanase, Vahid Lari, Frank Hannig, and Jürgen Teich.

Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing.

In Proceedings of the International Conference on Parallel Computing (ParCo),

Munich, Germany, September 10-13, 2013.

127

unpublished

Frank Hannig.

High-Level Synthesis Revised: Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model.

Keynote at Mini-Symposium on Parallel Computing with FPGAs (ParaFPGA) in conjunction with International Conference on Parallel Computing (ParCo), Munich, Germany, September 10, 2013.

126

unpublished

Frank Hannig.

A Domain-Specific Approach for 2-D Stencil Computations.

Invited talk, Regional Computing Center in Erlangen (RRZE), Germany, July 16, 2013.

125

inproceedings

Sascha Roloff, Andreas Weichslgartner, Jan Heißwolf, Frank Hannig, and Jürgen Teich.

NoC Simulation in Heterogeneous Architectures for PGAS Programming Model.

In Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems (M-SCOPES),

pp. 77-85, ACM, St. Goar, Germany, June 19-21, 2013.

124

inproceedings

Jürgen Teich, Alexandru Tanase, and Frank Hannig.

Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays.

In Proceedings of the 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Best Paper Award,

pp. 1-9, IEEE, Washington, DC, USA, June 5-7, 2013.

123

inproceedings

Srinivas Boppu, Frank Hannig, and Jürgen Teich.

Loop Program Mapping and Compact Code Generation for Programmable Hardware Accelerators.

In Proceedings of the 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP),

pp. 10-17, IEEE, Washington, DC, USA, June 5-7, 2013.

122

unpublished

Vahid Lari, Srinivas Boppu, Frank Hannig, Jürgen Teich, and Troy Scott.

Hybrid Prototyping of Tightly-Coupled Processor Arrays for MPSoC Designs.

Designer Track Poster Presentation at the 50th Design Automation Conference (DAC), Austin, TX, USA, June 2-6, 2013.

121

inproceedings

Srinivas Boppu, Vahid Lari, Frank Hannig, and Jürgen Teich.

Transactor-based Prototyping of Heterogeneous Multiprocessor System-On-Chip Architectures.

In Proceedings of the Synopsys Users Group Conference (SNUG),

Munich, Germany, May 14, 2013.

120

inproceedings

Frank Hannig, Moritz Schmid, Vahid Lari, Srinivas Boppu, and Jürgen Teich.

System Integration of Tightly-Coupled Processor Arrays using Reconfigurable Buffer Structures.

In Proceedings of the ACM International Conference on Computing Frontiers (CF),

pp. 2:1-2:4, ACM, Ischia, Italy, May 14-16, 2013.

119

inproceedings

Éricles R. Sousa, Alexandru Tanase, Vahid Lari, Frank Hannig, Jürgen Teich, Johny Paul, Walter Stechele, Manfred Kröhnert, and Tamim Asfour.

Acceleration of Optical Flow Computations on Tightly-Coupled Processor Arrays.

In Proceedings of the 25th Workshop on Parallel Systems and Algorithms (PARS),

Erlangen, Germany, April 11-12, 2013,
volume 30 of Mitteilungen - Gesellschaft für Informatik e. V., Parallel-Algorithmen und Rechnerstrukturen, pp. 80-89, Gesellschaft für Informatik e. V., 2013.

118

unpublished

Vahid Lari, Srinivas Boppu, Frank Hannig, Shravan Muddasani, Boris Kuzmin, and Jürgen Teich.

Resource-Aware Video Processing on Tightly-Coupled Processor Arrays.

Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), Grenoble, France, March 18-22, 2013.

117

inproceedings

Frank Hannig.

Resource-Aware Computing on Domain-Specific Accelerators.

In Proceedings of the 10st Workshop on Optimizations for DSP and Embedded Systems (ODES), Keynote,

p. 35, ACM, Shenzhen, China, February 24, 2013.

116

article

Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Moritz Schmid, and Jürgen Teich.

Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays.

ACM Transactions on Design Automation of Electronic Systems (TODAES),

18(1), pp. 2:1-2:25, 2013.

115

inproceedings

Richard Membarth, Frank Hannig, Jürgen Teich, and Harald Köstler.

Towards Domain-specific Computing for Stencil Codes in HPC.

In Proceedings of the 2nd International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC),

pp. 1133-1138, Salt Lake City, UT, USA, November 16, 2012.

114

unpublished

Frank Hannig.

Why do we see more and more domain-specific accelerators in multi-processor systems?.

Guest Lecture at University of California, Riverside in CS 287 Colloquium in Computer Science, Riverside, CA, USA, November 9, 2012.

113

unpublished

Frank Hannig.

Invasive Tightly-Coupled Processor Arrays.

Talk, 1st International Workshop on Domain-Specific Multicore Computing (DSMC) at International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, November 8, 2012.

112

inproceedings

Shravan Muddasani, Srinivas Boppu, Frank Hannig, Boris Kuzmin, Vahid Lari, and Jürgen Teich.

A Prototype of an Invasive Tightly-Coupled Processor Array.

In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP),

pp. 393-394, IEEE, Karlsruhe, Germany, October 23-25, 2012.

111

inproceedings

Michael Gerndt, Frank Hannig, Andreas Herkersdorf, Andreas Hollmann, Marcel Meyer, Sascha Roloff, Josef Weidendorfer, Thomas Wild, and Aurang Zaib.

An Integrated Simulation Framework for Invasive Computing.

In Proceedings of the Forum on Specification and Design Languages (FDL),

pp. 209-216, IEEE, Vienna, Austria, September 18-20, 2012.

110

inproceedings

Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, and Wieland Eckert.

Mastering Software Variant Explosion for GPU Accelerators.

In Ioannis Caragiannis, Michael Alexander, Rosa Maria Badia, Mario Cannataro, Alexandru Costan, Marco Danelutto, Frédéric Desprez, Bettina Krammer, Julio Sahuquillo, Stephen L. Scott, and Josef Weidendorfer, editors, Proceedings of the International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar) in Euro-Par 2012: Parallel Processing Workshops,

Rhodes Island, Greece, August 27-27, 2012,
volume 7640 of Lecture Notes in Computer Science (LNCS), pp. 123-132, Springer, 2012.

109

inproceedings

Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, and Jürgen Teich.

Design of Low Power On-Chip Processor Arrays.

In Proceedings of the 23rd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP),

pp. 165-168, IEEE Computer Society, Delft, The Netherlands, July 9-11, 2012.

108

inproceedings

Sascha Roloff, Frank Hannig, and Jürgen Teich.

Simulation of Resource-Aware Applications on Heterogeneous Architectures.

In Proceedings of ACACES 2012 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems,

pp. 127-130, Academia Press, Ghent, Fiuggi, Italy, July 8-14, 2012.

107

inproceedings

Alexandru Tanase, Frank Hannig, and Jürgen Teich.

Symbolic Loop Parallelization of Static Control Programs.

In Proceedings of ACACES 2012 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems,

pp. 33-36, Academia Press, Ghent, Fiuggi, Italy, July 8-14, 2012.

106

inproceedings

Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, and Wieland Eckert.

Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators based on a Domain-Specific Language for Medical Imaging.

In Proceedings of the 11th International Symposium on Parallel and Distributed Computing (ISPDC),

pp. 211-218, IEEE, Munich, Germany, June 25-29, 2012.

105

unpublished

Alexandru Tanase, Frank Hannig, and Jürgen Teich.

Towards Symbolic Loop Parallelization for Tightly-Coupled Processor Arrays.

Work-In-Progress Presentation at the 49th Design Automation Conference (DAC), San Francisco, CA, USA, June 3-7, 2012.

104

unpublished

Mario Körner, Wieland Eckert, Richard Membarth, Frank Hannig, and Jürgen Teich.

Entwicklungsframeworks für Mehrkernarchitekturen und Grafikprozessoren: Evaluierung anhand eines Algorithmus zur Registrierung von 3D- mit 2D-Bilddaten.

Talk, Conference for Parallel Programming, Concurrency, and Multi-core Systems (parallel), Karlsruhe, Germany, May 23-25, 2012.

103

inproceedings

Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, and Wieland Eckert.

Generating Device-specific GPU Code for Local Operators in Medical Imaging.

In Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS),

pp. 569-581, IEEE, Shanghai, China, May 21-25, 2012.

102

inproceedings

Sascha Roloff, Frank Hannig, and Jürgen Teich.

Fast Architecture Evaluation of Heterogeneous MPSoCs by Host-Compiled Simulation.

In Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems (SCOPES),

pp. 52-61, ACM Press, St. Goar, Germany, May 15-16, 2012.

101

inproceedings

Moritz Schmid, Frank Hannig, and Jürgen Teich.

Power Management Strategies for Serial RapidIO Endpoints in FPGAs.

In Proceedings of the 20th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), HiPEAC Paper Award,

pp. 101-108, IEEE, Toronto, Canada, April 29-May 1, 2012.

100

inproceedings

Richard Membarth, Jan-Hugo Lupp, Frank Hannig, Jürgen Teich, Mario Körner, and Wieland Eckert.

Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging.

In Andreas Herkersdorf, Kay Römer, and Uwe Brinkschulte, editors, Proceedings of the 25th International Conference on Architecture of Computing Systems (ARCS),

Munich, Germany, February 28-March 2, 2012,
volume 7179 of Lecture Notes in Computer Science (LNCS), pp. 147-159, Springer, 2012.

99

inproceedings

Sascha Roloff, Frank Hannig, and Jürgen Teich.

Approximate Time Functional Simulation of Resource-Aware Programming Concepts for Heterogeneous MPSoCs.

In Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC),

pp. 187-192, Sydney, Australia, January 30-February 2, 2012.

98

inproceedings

Srinivas Boppu, Frank Hannig, Jürgen Teich, and Roberto Perez-Andrade.

Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays.

In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig),

pp. 392-397, IEEE Computer Society, Cancun, Mexico, November 30-December 2, 2011.

97

unpublished

Vahid Lari, Srinivas Boppu, Shravan Muddasani, Frank Hannig, and Jürgen Teich.

Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays.

Talk, International Workshop on Adaptive Power Management with Machine Intelligence at International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, November 10, 2011.

96

inproceedings

Vahid Lari, Andriy Narovlyanskyy, Frank Hannig, and Jürgen Teich.

Decentralized Dynamic Resource Management Support for Massively Parallel Processor Arrays.

In Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP),

pp. 87-94, IEEE Computer Society, Santa Monica, CA, USA, September 11-14, 2011.

95

proceedings

Joseph R. Cavallaro, Milos D. Ercegovac, Frank Hannig, Paolo Ienne, Earl E. Swartzlander, Jr., and Alexandre F. Tenca.

Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP).

IEEE Computer Society, 2011, ISBN 978-1-4577-1292-0.

94

unpublished

Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, and Wieland Eckert.

Domain-specific Computing and Code Generation for Medical Imaging.

Poster Presentation at the 2nd Programming and Tuning Massively Parallel Systems Summer School (PUMPS), Barcelona, Spain, July 18-22, 2011.

93

inproceedings

Georgia Kouveli, Frank Hannig, Jan-Hugo Lupp, and Jürgen Teich.

Towards Resource-Aware Programming on Intel's Single-Chip Cloud Computer Processor.

In 3rd Many-core Applications Research Community (MARC) Symposium,

Ettlingen, Germany, July 5-6, 2011,
volume 7598 of KIT Scientific Reports, pp. 111-114, KIT Scientific Publishing, 2011.

92

article

Dmitrij Kissler, Daniel Gran, Zoran A. Salcic, Frank Hannig, and Jürgen Teich.

Scalable Many-Domain Power Gating in Coarse-grained Reconfigurable Processor Arrays.

IEEE Embedded Systems Letters,

3(2), pp. 58-61, 2011.

91

inproceedings

Frank Hannig, Sascha Roloff, Gregor Snelting, Jürgen Teich, and Andreas Zwinkau.

Resource-Aware Programming and Simulation of MPSoC Architectures through Extension of X10.

In Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems (SCOPES),

pp. 48-55, ACM Press, St. Goar, Germany, June 27-28, 2011.

90

inproceedings

Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, and Wieland Eckert.

Frameworks for GPU Accelerators: A Comprehensive Evaluation using 2D/3D Image Registration.

In Proceedings of the 9th IEEE Symposium on Application Specific Processors (SASP),

pp. 78-81, San Diego, CA, USA, June 5-6, 2011.

89

article

Richard Membarth, Hritam Dutta, Frank Hannig, and Jürgen Teich.

Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards.

Transactions on High-Performance Embedded Architectures and Compilers (Transactions on HiPEAC),

5(3)2011.

88

inproceedings

Vahid Lari, Frank Hannig, and Jürgen Teich.

Distributed Resource Reservation in Massively Parallel Processor Arrays.

In Proceedings of the International Parallel and Distributed Processing Symposium Workshops (IPDPSW),

pp. 318-321, IEEE Computer Society, Anchorage, AK, USA, May 16-17, 2011.

87

inproceedings

Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, and Wieland Eckert.

Frameworks for Multi-core Architectures: A Comprehensive Evaluation using 2D/3D Image Registration.

In Proceedings of the 24th International Conference on Architecture of Computing Systems (ARCS),

Lake Como, Italy, February 22-25, 2011,
volume 6566 of Lecture Notes in Computer Science (LNCS), pp. 62-73, Springer, 2011.

86

inproceedings

Richard Membarth, Frank Hannig, Jürgen Teich, Gerhard Litz, and Heinz Hornegger.

Detector Defect Correction of Medical Images on Graphics Processors.

In Proceedings of SPIE Medical Imaging,

volume 7962, pp. 79624M 1-12, Lake Buena Vista, FL, USA, February 12-17, 2011.

85

article

Dmitrij Kissler, Frank Hannig, and Jürgen Teich.

Efficient Evaluation of Power/Area/Latency Design Trade-offs for Coarse-Grained Reconfigurable Processor Arrays.

Journal of Low Power Electronics,

7(1), pp. 29-40, 2011.

84

inproceedings

Frank Hannig, Moritz Schmid, Jürgen Teich, and Heinz Hornegger.

A Deeply Pipelined and Parallel Architecture for Denoising Medical Images.

In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT),

pp. 485-490, IEEE, Beijing, China, December 8-10, 2010.

83

unpublished

Frank Hannig.

Communication Synthesis of Loop Accelerator Pipelines.

Talk, Workshop on Compiler-Assisted System-On-Chip Assembly (CASA), Embedded Systems Week (ESWEEK), Scottsdale, AZ, USA, October 28, 2010.

82

unpublished

Frank Hannig.

Retargetable Mapping of Loop Programs on Coarse-grained Reconfigurable Arrays.

Talk, International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), Scottsdale, AZ, USA, October 26, 2010.

81

inproceedings

Tom Vander Aa, Praveen Raghavan, Scott Mahlke, Bjorn De Sutter, Aviral Shrivastava, and Frank Hannig.

Compilation Techniques for CGRAs: Exploring All Parallelization Approaches.

In Proceedings of the International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS),

pp. 185-186, ACM, Scottsdale, AZ, USA, October 24-29, 2010.

80

inproceedings

Hritam Dutta, Frank Hannig, Moritz Schmid, and Joachim Keinert.

Modeling and Synthesis of Communication Subsystems for Loop Accelerator Pipelines.

In Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP),

pp. 125-132, IEEE Computer Society, Rennes, France, July 7-9, 2010.

79

proceedings

François Charot, Frank Hannig, Jürgen Teich, and Christophe Wolinski.

Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP).

IEEE Computer Society, 2010, ISBN 978-1-4244-6967-3.

78

unpublished

Hritam Dutta, Frank Hannig, and Jürgen Teich.

PARO - A Design Tool for Synthesis of Hardware Accelerators for SoCs.

Tool Presentation at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March 8-12, 2010.

77

inproceedings

Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, and Wieland Eckert.

Comparison of Parallelization Frameworks for Shared Memory Multi-Core Architectures.

In Proceedings of the Embedded World Conference,

Nuremberg, Germany, March 3-5, 2010.

76

inproceedings

Moritz Schmid, Frank Hannig, Jürgen Teich, Ralf Diefenbach, Hartmut Pettendorf, and Heinz Hornegger.

Discourse on Extending Embedded Medical Image Processing Systems Using the High Speed Serial RapidIO Interconnect.

In Proceedings of the Embedded World Conference,

Nuremberg, Germany, March 3-5, 2010.

75

inproceedings

Amouri Abdulazim, Farhadur Arifin, Frank Hannig, and Jürgen Teich.

FPGA Implementation of an Invasive Computing Architecture.

In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT),

pp. 135-142, IEEE, Sydney, Australia, December 9-11, 2009.

74

inproceedings

Farhadur Arifin, Richard Membarth, Amouri Abdulazim, Frank Hannig, and Jürgen Teich.

FSM-Controlled Architectures for Linear Invasion.

In Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC),

pp. 59-64, IEEE, Florianópolis, Brazil, October 12-14, 2009.

73

inproceedings

Vahid Lari, Frank Hannig, and Jürgen Teich.

System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance.

In Proceedings of the 4th International Symposium on Embedded Multicore Systems-on-Chip (MCSoC),

pp. 528-534, IEEE Computer Society, Vienna, Austria, September 22-25, 2009.

72

phdthesis

Frank Hannig.

Scheduling Techniques for High-Throughput Loop Accelerators.

Dissertation, 307 pages, University of Erlangen-Nuremberg, Germany, August 11, 2009, ISBN 978-3-86853-220-3, Verlag Dr. Hut, Munich, Germany.

71

inproceedings

Richard Membarth, Frank Hannig, Hritam Dutta, and Jürgen Teich.

Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors.

In Koen Bertels, Nikitas Dimopoulos, Christina Silvano, and Stephan Wong, editors, Proceedings of the 9th International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS),

Island of Samos, Greece, July 20-23, 2009,
volume 5657 of Lecture Notes in Computer Science (LNCS), pp. 277-288, Springer, 2009.

70

inproceedings

Richard Membarth, Frank Hannig, Hritam Dutta, and Jürgen Teich.

Optimization Flow for Algorithm Mapping on Graphics Cards.

In Proceedings of ACACES 2009 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems,

pp. 229-232, Academia Press, Ghent, Terrassa, Spain, July 12-18, 2009.

69

inproceedings

Hritam Dutta, Jiali Zhai, Frank Hannig, and Jürgen Teich.

Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines.

In Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP),

pp. 161-168, IEEE Computer Society, Boston, MA, USA, July 7-9, 2009.

68

inproceedings

Richard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig, and Jürgen Teich.

Acceleration of Multiresolution Imaging Algorithms: A Comparative Study.

In Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP),

pp. 211-214, IEEE Computer Society, Boston, MA, USA, July 7-9, 2009.

67

unpublished

Frank Hannig, Hritam Dutta, and Jürgen Teich.

PARO - A Design Tool for the Automatic Generation of Hardware Accelerators.

Tool Presentation at the Demo Night of the 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Boston, MA, USA, July 7-9, 2009.

66

inproceedings

Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, and Jürgen Teich.

Model-Based Synthesis and Optimization of Static Multi-Rate Image Processing Algorithms.

In Proceedings of the Conference on Design, Automation and Test in Europe (DATE),

pp. 135-140, IEEE Computer Society, Nice, France, April 20-24, 2009.

65

article

Dmitrij Kissler, Andreas Strawetz, Frank Hannig, and Jürgen Teich.

Power-efficient Reconfiguration Control in Coarse-grained Dynamically Reconfigurable Architectures.

Journal of Low Power Electronics,

5(1), pp. 96-105, 2009.

64

inproceedings

Frank Hannig, Hritam Dutta, and Jürgen Teich.

Parallelization Approaches for Hardware Accelerators - Loop Unrolling versus Loop Partitioning.

In Proceedings of the 22nd International Conference on Architecture of Computing Systems (ARCS),

Delft, The Netherlands, March 10-13, 2009,
volume 5455 of Lecture Notes in Computer Science (LNCS), pp. 16-27, Springer, 2009.

63

inproceedings

Hritam Dutta, Frank Hannig, and Jürgen Teich.

Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis.

In Proceedings of the 22nd International Conference on Architecture of Computing Systems (ARCS),

Delft, The Netherlands, March 10-13, 2009,
volume 5455 of Lecture Notes in Computer Science (LNCS), pp. 233-245, Springer, 2009.

62

article

Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, and Bernard Pottier.

A Holistic Approach for Tightly Coupled Reconfigurable Parallel Processors.

Microprocessors and Microsystems,

33(1), pp. 53-62, 2009.

61

unpublished

Frank Hannig.

Power-Efficient Design of Tightly Coupled Parallel Processors with Dynamic Reconfiguration Capabilities.

Talk, HiPEAC Cluster Meeting, Paris, France, November 27-28, 2008.

60

inproceedings

Dmitrij Kissler, Andreas Strawetz, Frank Hannig, and Jürgen Teich.

Power-efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures.

In Proceedings of the 18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS),

Lisbon, Portugal, September 10-12, 2008,
volume 5349 of Lecture Notes in Computer Science (LNCS), pp. 307-317, Springer, 2008.

59

inproceedings

Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, and Frank Hannig.

Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures.

In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL),

pp. 391-396, IEEE, Heidelberg, Germany, September 8-10, 2008.

58

inproceedings

Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, and Manfred Glesner.

SPP1148 Booth: Coarse-Grained Reconfiguration.

In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL),

p. 349, Heidelberg, Germany, September 8-10, 2008.

57

inproceedings

Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, and Frank Hannig.

Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures.

In Proceedings of the 11th Euromicro Conference on Digital System Design (DSD),

pp. 345-352, IEEE, Parma, Italy, September 3-5, 2008.

56

inproceedings

Rainer Schaffer, Renate Merker, Frank Hannig, and Jürgen Teich.

Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism.

In Proceedings of the 11th Euromicro Conference on Digital System Design (DSD),

pp. 391-398, IEEE, Parma, Italy, September 3-5, 2008.

55

inproceedings

Hritam Dutta, Frank Hannig, and Jürgen Teich.

PARO: A Design Tool for Automatic Generation of Hardware Accelerators.

In Proceedings of ACACES 2008 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems,

pp. 317-320, Academia Press, Ghent, L'Aquila, Italy, July 13-19, 2008.

54

incollection

Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, and Jürgen Teich.

MAML: An ADL for Designing Single and Multiprocessor Architectures.

In Prabhat Mishra and Nikil Dutt, editors, Processor Description Languages,

chapter 12, pp. 295-327. In Systems on Silicon, Morgan Kaufmann, 2008.

53

inproceedings

Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, and Frank Hannig.

Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures.

In Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM),

pp. 306-309, IEEE Computer Society, Palo Alto, CA, USA, April 14-15, 2008.

52

inproceedings

Frank Hannig, Holger Ruckdeschel, Hritam Dutta, and Jürgen Teich.

PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications.

In Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing (ARC),

London, United Kingdom, March 26-28, 2008,
volume 4943 of Lecture Notes in Computer Science (LNCS), pp. 287-293, Springer, 2008.

51

unpublished

Dmitrij Kissler, Hritam Dutta, Alexey Kupriyanov, Frank Hannig, and Jürgen Teich.

A High-Speed Dynamic Reconfigurable Multilevel Parallel Architecture.

Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), Munich, Germany, March 11-14, 2008.

50

unpublished

Hritam Dutta, Frank Hannig, and Jürgen Teich.

The PARO Design Tool for Automatic Generation of Hardware Accelerators.

Interactive Presentation at Friday Workshop, The New Wave of the High-Level Synthesis, Design, Automation and Test in Europe (DATE), Munich, Germany, March 10-14, 2008.

49

unpublished

Jürgen Teich, Frank Hannig, Hritam Dutta, Dmitrij Kissler, and Matthias Hartl.

Domain-specific Reconfigurable MPSoC-Systems - Challenges and Trends.

Talk at Friday Workshop, Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures, Design, Automation and Test in Europe (DATE), Munich, Germany, March 10-14, 2008.

48

inproceedings

Frank Hannig, Holger Ruckdeschel, and Jürgen Teich.

The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications.

In Proceedings of the GI/ITG/GMM-Workshop - Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen,

pp. 129-138, Shaker, Freiburg, Germany, March 3-5, 2008.

47

inproceedings

Frank Hannig, Hritam Dutta, Holger Ruckdeschel, and Jürgen Teich.

Quantitative Evaluation of Behavioral Synthesis Approaches for Reconfigurable Devices.

In Proceedings of the 2nd HiPEAC Workshop on Reconfigurable Computing (WRC),

pp. 73-82, Gothenburg, Sweden, January 27, 2008.

46

unpublished

Frank Hannig.

Reconfigurable Computing Activities at University of Erlangen-Nuremberg, Hardware/Software Co-Design.

Talk, HiPEAC Cluster Meeting, Cambridge, United Kingdom, November 27, 2007.

45

unpublished

Frank Hannig.

A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays - Case Study and Quantitative Evaluation.

Talk, Dagstuhl Seminar No. 07361, Programming Models for Ubiquitous Parallelism, Wadern, Germany, September 7, 2007.

44

inproceedings

Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, and Andrej Stravet.

A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation.

In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Invited paper,

pp. 14-24, CSREA Press, Las Vegas, NV, USA, June 25-28, 2007.

43

inproceedings

Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, and Bernard Pottier.

Massively Parallel Processor Architectures: A Co-design Approach.

In Proceedings of the 3rd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC),

pp. 61-68, Univ. Montpellier II, Montpellier, France, June 18-20, 2007.

42

article

Hritam Dutta, Frank Hannig, Holger Ruckdeschel, and Jürgen Teich.

Efficient Control Generation for Mapping Nested Loop Programs onto Processor Arrays.

Journal of Systems Architecture,

53(5-6), pp. 300-309, 2007.

41

inproceedings

Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, and Jürgen Teich.

Efficient Event-driven Simulation of Parallel Processor Architectures.

In Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems (SCOPES),

pp. 71-80, ACM Press, Nice, France, April 20, 2007.

40

article

Dmitrij Kissler, Frank Hannig, and Jürgen Teich.

Schwach programmiert macht stark - Massiv parallele Prozessorfelder.

Design&Elektronik,

(4), pp. 34-39, 2007.

39

inproceedings

Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, and Sébastien Pillement.

Modeling of Interconnection Networks in Massively Parallel Processor Architectures.

In Paul Lukowicz, Lothar Thiele, and Gerhard Tröster, editors, Proceedings of the 20th International Conference on Architecture of Computing Systems (ARCS),

Zurich, Switzerland, March 12-15, 2007,
volume 4415 of Lecture Notes in Computer Science (LNCS), pp. 268-282, Springer, 2007.

38

inproceedings

Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, and Jürgen Teich.

A Highly Parameterizable Parallel Processor Array Architecture.

In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT),

pp. 105-112, IEEE, Bangkok, Thailand, December 13-15, 2006.

37

inproceedings

Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, and Jürgen Teich.

Hardware Cost Analysis for Weakly Programmable Processor Arrays.

In Proceedings of the International Symposium on System-on-Chip (SoC),

pp. 179-182, IEEE, Tampere, Finland, November 14-16, 2006.

36

inproceedings

Sebastian Siegel, Renate Merker, Frank Hannig, and Jürgen Teich.

Communication-conscious Mapping of Regular Nested Loop Programs onto Massively Parallel Processor Arrays.

In Proceedings of the 18th International Conference on Parallel and Distributed Computing and Systems (PDCS),

pp. 71-76, ACTA Press, Dallas, TX, USA, November 13-15, 2006.

35

inproceedings

Hritam Dutta, Frank Hannig, and Jürgen Teich.

Hierarchical Partitioning for Piecewise Linear Algorithms.

In Proceedings of the 5th International Conference on Parallel Computing in Electrical Engineering (PARELEC),

pp. 153-160, IEEE Computer Society, Bialystok, Poland, September 13-17, 2006.

34

inproceedings

Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, and Heinz Hornegger.

A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing.

In Proceedings of the 17th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP),

pp. 331-337, IEEE Computer Society, Steamboat Springs, CO, USA, September 11-13, 2006.

33

techreport

Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, and Sébastien Pillement.

Modeling of Interconnection Networks in Massively Parallel Processor Architectures.

University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, August 15, 2006.

32

inproceedings

Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, and Jürgen Teich.

A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template.

In Proceedings of the 2nd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC),

pp. 31-37, Montpellier, France, July 3-5, 2006.

31

inproceedings

Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, and Jürgen Teich.

A Generic Framework for Rapid Prototyping of System-on-Chip Designs.

In Proceedings of International Conference on Computer Design (CDES),

pp. 189-195, Las Vegas, NV, USA, June 26-29, 2006.

30

techreport

Hritam Dutta, Frank Hannig, and Jürgen Teich.

A Formal Methodology for Hierarchical Partitioning of Piecewise Linear Algorithms.

University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, April 3, 2006.

29

techreport

Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Rainer Schaffer, and Jürgen Teich.

MAML - An Architecture Description Language for Modeling and Simulation of Processor Array Architectures, Part I.

University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, March 23, 2006.

28

inproceedings

Hritam Dutta, Frank Hannig, and Jürgen Teich.

Controller Synthesis for Mapping Partitioned Programs on Array Architectures.

In Werner Grass, Bernhard Sick, and Klaus Waldschmidt, editors, Proceedings of the 19th International Conference on Architecture of Computing Systems (ARCS),

Frankfurt am Main, Germany, March 13-16, 2006,
volume 3894 of Lecture Notes in Computer Science (LNCS), pp. 176-191, Springer, 2006.

27

inproceedings

Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, and Renate Merker.

An Architecture Description Language for Massively Parallel Processor Architectures.

In Proceedings of the GI/ITG/GMM-Workshop - Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen,

pp. 11-20, Shaker, Dresden, Germany, February 20-22, 2006.

26

inproceedings

Hritam Dutta, Frank Hannig, and Jürgen Teich.

Mapping of Nested Loop Programs onto Massively Parallel Processor Arrays with Memory and I/O Constraints.

In Friedhelm Meyer auf der Heide and Burkhard Monien, editors, Proceedings of the 6th International Heinz Nixdorf Symposium, New Trends in Parallel & Distributed Computing,

Paderborn, Germany, January 17-18, 2006,
volume 181 of HNI-Verlagsschriftenreihe, pp. 97-119, Heinz Nixdorf Institut, Universität Paderborn, 2006.

25

article

Frank Hannig, Hritam Dutta, and Jürgen Teich.

Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays: Architectural Parameters and Methodology.

International Journal of Embedded Systems,

2(1/2), pp. 114-127, 2006.

24

techreport

Hritam Dutta, Frank Hannig, and Jürgen Teich.

Controller Synthesis for Mapping Partitioned Programs on Array Architectures.

University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, November 1, 2005.

23

inproceedings

Thomas Schlichter, Christian Haubelt, Frank Hannig, and Jürgen Teich.

Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems.

In Proceedings of the 16th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP),

pp. 9-14, IEEE Computer Society, Island of Samos, Greece, July 23-25, 2005.

22

inproceedings

Holger Ruckdeschel, Hritam Dutta, Frank Hannig, and Jürgen Teich.

Automatic FIR Filter Generation for FPGAs.

In Timo D. Hämäläinen, Andy D. Pimentel, Jarmo Takala, and Stamatis Vassiliadis, editors, Embedded Computer Systems: Architectures, Modeling, and Simulation, 5th International Workshop, SAMOS, Proceedings,

Island of Samos, Greece, July 18-20, 2005,
volume 3553 of Lecture Notes in Computer Science (LNCS), pp. 51-61, Springer, 2005.

21

inproceedings

Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, and Olivier Sentieys.

Co-Design of Massively Parallel Embedded Processor Architectures.

In Proceedings of the first International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC),

pp. 27-34, Univ. Montpellier II, Montpellier, France, June 27-29, 2005.

20

inproceedings

Frank Hannig and Jürgen Teich.

Output Serialization for FPGA-based and Coarse-grained Processor Arrays.

In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA),

pp. 78-84, CSREA Press, Las Vegas, NV, USA, June 27-30, 2005.

19

inproceedings

Jan van der Veen, Sándor Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, and Jürgen Teich.

Defragmenting the Module Layout of a Partially Reconfigurable Device.

In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA),

pp. 92-101, CSREA Press, Las Vegas, NV, USA, June 27-30, 2005.

18

unpublished

Frank Hannig.

Architektur und Compiler Co-Design.

Talk, DFG SPP 1148 Workshop, Blaubeuren, Germany, October 4, 2004.

17

inproceedings

Frank Hannig and Jürgen Teich.

Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals.

In Proceedings of the 15th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP),

pp. 17-27, IEEE Computer Society, Galveston, TX, USA, September 27-29, 2004.

16

inproceedings

Alexey Kupriyanov, Frank Hannig, and Jürgen Teich.

Automatic and Optimized Generation of Compiled High-Speed RTL Simulators.

In Proceedings of Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES),

Washington, DC, USA, September 22, 2004.

15

inproceedings

Frank Hannig and Jürgen Teich.

Dynamic Piecewise Linear/Regular Algorithms.

In Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC),

pp. 79-84, IEEE Computer Society, Dresden, Germany, September 7-10, 2004.

14

inproceedings

Alexey Kupriyanov, Frank Hannig, and Jürgen Teich.

High-Speed Event-Driven RTL Compiled Simulation.

In Andy D. Pimentel and Stamatis Vassiliadis, editors, Computer Systems: Architectures, Modeling, and Simulation, 4th International Samos Workshop (SAMOS), Proceedings,

Island of Samos, Greece, July 19-21, 2004,
volume 3133 of Lecture Notes in Computer Science (LNCS), pp. 519-529, Springer, 2004.

13

techreport

Frank Hannig and Jürgen Teich.

Resource Constrained and Speculative Scheduling of Dynamic Piecewise Regular Algorithms.

University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, June 8, 2004.

12

inproceedings

Frank Hannig, Hritam Dutta, and Jürgen Teich.

Regular Mapping for Coarse-grained Reconfigurable Architectures.

In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP),

volume V, pp. 57-60, IEEE Signal Processing Society, Montréal, Quebec, Canada, May 17-21, 2004.

11

inproceedings

Frank Hannig, Hritam Dutta, and Jürgen Teich.

Mapping of Regular Nested Loop Programs to Coarse-grained Reconfigurable Arrays - Constraints and Methodology.

In Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS),

IEEE Computer Society, Santa Fe, NM, USA, April 26-30, 2004.

10

unpublished

Alexey Kupriyanov, Frank Hannig, Jürgen Teich, Dirk Fischer, Michael Thies, and Ralph Weper.

ArchitectureComposer.

CAD Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), Paris, France, February 16-20, 2004.

9

unpublished

Frank Hannig.

Mapping of Regular Algorithms to Massively Parallel Architectures.

Invited talk, Department of System Simulation, University Erlangen-Nuremberg, Germany, February 12, 2004.

8

incollection

Frank Hannig and Jürgen Teich.

Energy Estimation and Optimization for Piecewise Regular Processor Arrays.

In Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation,

chapter 6, pp. 107-126. Number 20 in Signal Processing and Communications, Marcel Dekker, New York, USA, 2004.

7

inproceedings

Frank Hannig and Jürgen Teich.

Energy Estimation of Nested Loop Programs.

In Proceedings 14th Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA),

pp. 149-150, ACM Press, Winnipeg, Manitoba, Canada, August 10-13, 2002.

6

inproceedings

Frank Hannig and Jürgen Teich.

Energy Estimation for Piecewise Regular Processor Arrays.

In Proceedings of the Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS),

Island of Samos, Greece, July 22-25, 2002.

5

incollection

Marcus Bednara, Frank Hannig, and Jürgen Teich.

Generation of Distributed Loop Control.

In Ed F. Deprettere, Jürgen Teich, and Stamatis Vassiliadis, editors, Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS,

pp. 154-170. Volume 2268 of Lecture Notes in Computer Science (LNCS), Springer, 2002.

4

inproceedings

Marcus Bednara, Frank Hannig, and Jürgen Teich.

Boundary Control: A new Distributed Control Architecture for Space-Time Transformed (VLSI) Processor Arrays.

In Proceedings of the 35th IEEE Asilomar Conference on Signals, Systems, and Computers,

volume 2, pp. 468-474, IEEE Computer Society, Pacific Grove, CA, USA, November 4-7, 2001.

3

inproceedings

Frank Hannig and Jürgen Teich.

Design Space Exploration for Massively Parallel Processor Arrays.

In Victor Malyshkin, editor, Proceedings of the 6th International Conference on Parallel Computing Technologies (PaCT),

Novosibirsk, Russia, September 3-7, 2001,
volume 2127 of Lecture Notes in Computer Science (LNCS), pp. 51-65, Springer, 2001.

2

masterthesis

Frank Hannig.

Exploration von Raum- und Zeittransformationen für Algorithmen mit uniformen Datenabhängigkeiten.

Diplomarbeit, Universität Paderborn, Fachbereich Elektrotechnik und Informationstechnik, Fachgebiet Datentechnik, October 31, 2000.

1

masterthesis

Frank Hannig.

Eine Softwareumgebung für neuronale Assoziativspeicher.

Studienarbeit, Universität Paderborn, Fachbereich Elektrotechnik und Informationstechnik, Fachgebiet Schaltungstechnik, April 6, 1999.

Copyright © Frank Hannig
  Impressum Stand: 13 September 2016.   F.H.