||Prof. Dr. J. Teich
||Reconfigurable Computing and
Reconfigurable Computing including Labs
||V2 + Ü2 (combined 5 ECTS) + optional P2 (FPGA & VHDL Labs, 2.5 ECTS),
Computer Science, IuK, SIM, Medical and Health Engineering, Mechatronics, and Computational Engineering
|Lecture, location and time
||Di 10:15 - 11:45, 01.255-128 (Cauerstraße 11) (Prof. Dr. J. Teich)
|Exercise, location and time
||Mi 8:15 - 9:45, 01.255-128 (Cauerstraße 11) (F. Khosravi and J. Echavarria)
|Lab, location and time
||Fr 14:15 - 17:15, 02.133-128 (Cauerstraße 11) (E. Sousa and M. Letras)
First lecture is on 18.10.2016 (Tuesday), 10:15, Cauerstraße 11 Room No: 01.255-128
First exercise is on 09.11.2016 (Wednesday), 08:15, Cauerstraße 11 Room No: 01.255-128
Reconfigurable (adaptive) computing is a novel yet important research field investigating the capability of
hardware to adapt to changing computational requirements such as emerging standards, late design changes,
and even to changing processing requirements arising at run-time. Reconfigurable computing thus benefits from
a) the programmability of software similar to the Von Neumann computer and b) the speed and efficiency of parallel hardware execution.
The purpose of the course reconfigurable computing is to instruct students about the possibilities and rapidly
growing interest in adaptive hardware and corresponding design techniques by providing them the necessary
knowledge for understanding and designing reconfigurable hardware systems and studying applications benefiting
from dynamic hardware reconfiguration.
After a general introduction about benefits and application ranges of reconfigurable (adaptive) computing
in contrast to general-purpose and application-specific computing, the following topics will be covered:
Reconfigurable computing is an interdisciplinary field of research between computer science and electrical
engineering on a 4 SWS (4 hours/week) basis. Lecture and Exercises will give 5 ECTS, the FPGA & VHDL labs 2.5 ECTS.
- Reconfigurable computing systems: Introduction of available technology including fine grained
look up table (LUT-) based reconfigurable systems such as field programmable gate arrays (FPGA) as well as
newest coarse grained architectures and technology.
- Design and implementation: Algorithms and steps (design entry, functional simulation, logic synthesis,
technology mapping, place and route, bit stream generation) to implement (map) algorithms to FPGAs. The main focus
lies on logic synthesis algorithms for FPGAs, in particular LUT technology mapping.
- Temporal partitioning: techniques to reconfigure systems over time. Covered are the problems
of mapping large circuits which do not fit one single device. Several temporal partitioning techniques
are studied and compared.
- Temporal placement: Techniques and algorithms to exploit the possibility of partial and
dynamic (run-time) hardware reconfiguration. Here, OS-like services are needed that optimize the allocation
and scheduling of modules at run-time.
- On-line communication: Modules dynamically placed at run-time on a given device need to communicate
as well as transport data off-chip. State-of-the-art techniques are introduced how modules can communicate
data at run-time including bus-oriented as well as network-on-a-chip (NoC) approaches.
- Designing reconfigurable applications on Xilinx Virtex FPGAs: In this part, the generation of partial
bitstreams for components to be placed at run-time on Xilinx FPGAs is introduced and discussed including newest
available tool flows.
- Applications: This section presents applications benefiting from dynamic hardware reconfiguration.
It covers the use of reconfigurable systems including rapid prototyping, reconfigurable supercomputers, reconfigurable
massively parallel computers and studies important application domains such as distributed arithmetic, signal
processing, network packet processing, control design, and cryptography.
Documents (Will be progressively provided during the semester):