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Publications
select your optimal design
| 2010 | 66 M. Glaß, M. Lukasiewycz, C. Haubelt and J. Teich.
Towards Scalable System-Level Reliability Analysis.
To appear in Proceedings of the 2010 ACM/EDAC/IEEE Design Automation Conference (DAC 2010), Anaheim, CA, U.S.A., June 13-18, 2010. ©1
 | 65 J. Falk, C. Zebelein, C. Haubelt, J. Teich and R. Dorsch.
Integrating Hardware/Firmware Verification Efforts Using SystemC High-Level Models.
J. Falk, C. Zebelein, C. Haubelt, J. Teich and R. Dorsch
Integrating Hardware/Firmware Verification Efforts Using SystemC High-Level Models.
In 13. ITG/GI/GMM Workshop für Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen,
Fraunhofer IIS/EAS Dresden, pp. 137-146, February 22-24, 2010. ©1
 | 64 R. Kiesel, O. Löhlein, A. Terzis, M. Streubühr, C. Haubelt and J. Teich.
Actor-oriented Modeling of Driver Assistance Systems for Efficient Multi-Core ECU Implementation..
In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, to appear, Dresden, Germany, February 2010. ©1
| 63 M. Glaß, M. Lukasiewycz, C. Haubelt and J. Teich.
Lifetime Reliability Optimization for Embedded Systems: A System-Level Approach.
Proceedings of IEEE International Workshop on Reliability Aware System Design and Test (RASDAT '10), pp. 17-22, Bangalore, India, January 07-08, 2010. ©1
| | 2009 | 62 C. Haubelt.
ESL Synthesis Across Hardware/Software Boundaries.
Invited Talk at the Workshop on Compiler-Assisted System-On-Chip Assembly (CASA'09), Embedded System Week 2009, October 10th, Grenoble, France, 2009. ©1
| 61 A. Gerstlauer, C. Haubelt, A. Pimentel, T. Stefanov, D. Gajski and J. Teich.
Electronic System-Level Synthesis Methodologies.
In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(10), pages 1517-1530, October 2009. ©1
| 60 M. Streubühr, J. Gladigau, C. Haubelt and J. Teich.
Efficient Approximately-Timed Performance Modeling for Architectural Exploration of MPSoCs.
In Forum on specification and Design Languages 2009, pp. 1-6, Sophia Antipolis, France, Sep. 22-24, 2009. ©1
| 59 C. Haubelt.
Designing Multi-Processor Systems-on-Chip.
Embedded Tutorial at the 22nd International SoC Conference. September 10th, Belfast, Northern Ireland, UK, 2009. ©1
| 58 M. Streubühr.
Model-based Virtual Prototyping for Automotive Applications.
Proceedings of the 3rd Chinese-German Summer School, pp. 204-209, Erlangen, Germany, May 4-22, 2009, Department of Material Science 6 - Electrical Engineering Materials, University of Erlangen-Nuremberg. ©1
| 57 J. Keinert and J. Teich.
Data Flow Based System Level Design and Analysis of Image Processing Applications.
Poster on the EDAA PhD forum at DATE 2009, Nice, April 2009. ©1
| 56 C. Haubelt.
SystemCoDesigner: An ESL Synthesis Methodology.
DATE´09 Friday Workshop: The Future of ESL Synthesis, Nice, Farnce, 2009. Invited Talk. ©1
| 55 M. Streubühr.
High-Level-Modellierung von Automotive-Anwendungen zur schnellen Virtuellen Prototypisierung.
Talk at the Innovation Forum Embedded Systems, Munich, Germany, April 24, 2009. ©1
| 54 J. Keinert, C. Haubelt and J. Teich.
Data Flow Based System Level Design and Analysis of Concurrent Image Processing Applications.
Proceedings of DATE'09 Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Nice, April 2009, pp. 215-216. ©1
| 53 J. Keinert, H. Dutta, F. Hannig, C. Haubelt and J. Teich.
Model-Based Synthesis and Optimization of Static Multi-Rate Image Processing Algorithms.
Proceedings of Design, Automation and Test in Europe (DATE 2009), IEEE Computer Society, Nice, France, April 20-24, 2009, pp. 135-140. ©1
| 52 M. Lukasiewycz, M. Streubühr, M. Glaß, C. Haubelt and J. Teich.
Combined System Synthesis and Communication Architecture Exploration for MPSoCs.
Proceedings of Design, Automation and Test in Europe (DATE 2009), pp. 472-477, IEEE Computer Society, Nice, France, April 20-24, 2009. ©1
| 51 M. Glaß, M. Lukasiewycz, C. Haubelt and J. Teich.
Incorporating Graceful Degradation into Embedded System Design.
Proceedings of Design, Automation and Test in Europe (DATE 2009), pp. 320-323, IEEE Computer Society, Nice, France, April 20-24, 2009. ©1
| 50 J. Teich and C. Haubelt.
Principles: Analysis, Optimization and Exploration.
DATE´09 Monday Tutorial: System-Level Modeling, Analysis and Synthesis of Embedded Multi-Core Designs, Nice, Farnce, 2009. Invited Talk. ©1
| 49 C. Haubelt.
Practice: ESL Case Studies (Motion-JPEG Example).
DATE´09 Monday Tutorial: System-Level Modeling, Analysis and Synthesis of Embedded Multi-Core Designs, Nice, Farnce, 2009. Invited Talk. ©1
| 48 J. Teich.
Embedded System Design.
3rd Chinese-German Summer School, 11.5.2009, Erlangen, Germany. Invited Lecture. ©1
| 47 M. Streubühr, M. Jäntsch, C. Haubelt and J. Teich.
From Model-based Design to Virtual Prototypes for Automotive Applications.
In Proceedings of the Embedded World Conference, pp. 1-10, Nuremberg, Germany, March 03-05, 2009. ©1
| 46 J. Keinert, M. Streubühr, T. Schlichter, J. Falk, J. Gladigau, C. Haubelt, J. Teich and M. Meredith.
SYSTEMCODESIGNER - An Automatic ESL Synthesis Approach by Design Space Exploration and Behavioral Synthesis for Streaming Applications.
In ACM Transactions on Design Automation of Electronic Systems, 14(1), pp. 1-23, 2009. ©1
| 45 M. Streubühr, C. Haubelt and J. Teich.
System Level Performance Simulation for Heterogeneous Multi-Processor Architectures.
1st HiPEAC Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), in conjunction with the 4th HiPEAC Conference, pp. 47-52, Paphos, Cyprus, January 25, 2009. ©1
| | 2008 | 44 C. Haubelt.
An Actor-Oriented Design Methodology Using SystemC.
Invited talk at IBM Future Technology Forum, Böblingen, Germany, December 12, 2008. ©1
| 43 C. Haubelt.
SystemCoDesigner - Map2MPSoC 2008.
Invited talk at ARTIST Design Map2MPSoC 2008 Workshop, Düsseldorf, Germany, November 28, 2008. ©1
| 42 C. Haubelt.
SystemCoDesigner - A Methodology for an Early Assessment of Design Options.
Invited talk at the Fraunhofer Institut für Integrierte Schaltungen (FhG-IIS), Erlangen, Germany, November 25, 2008. ©2
| 41 J. Falk, J. Keinert, C. Haubelt, J. Teich and S. Bhattacharyya.
A Generalized Static Data Flow Clustering Algorithm for MPSoC Scheduling of Multimedia Applications.
In Proc. of the 8th ACM & IEEE international conference on Embedded software (EMSOFT'2008), pp. 189-198,
Atlanta, Georgia, USA, October 20-22, 2008. ©1
| 40 F. Reimann, M. Glaß, M. Lukasiewycz, J. Keinert, C. Haubelt and J. Teich.
Symbolic Voter Placement for Dependability-Aware System Synthesis.
In Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 237-242, Atlanta, GA USA, October 19-24 2008. ©1
| 39 J. Keinert, C. Haubelt and J. Teich.
Automatic Synthesis of Design Alternatives for Fast Stream-Based Out-of-Order Communication.
Proceedings of the 2008 IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, (VLSI-SoC 2008) pp. 265-270, Rhodes Island, Greece, October 13-15, 2008. ©1
| 38 M. Glaß, M. Lukasiewycz, F. Reimann, C. Haubelt and J. Teich.
Symbolic Reliability Analysis of Self-healing Networked Embedded Systems.
In Proceedings of the 27th International Conference on Computer Safety, Reliability and Security (SAFECOMP 2008), pp. 139-152, Newcastle upon Tyne, UK, September 22-25, 2008. ©1
| 37 C. Haubelt, J. Teich and R. Dorsch.
Entdecke die Möglichkeiten.
In Design&Elektronik (8):22-27, 2008, WEKA. ©1
| 36 M. Glaß, M. Lukasiewycz, R. Wanka, C. Haubelt and J. Teich.
Multi-Objective Routing and Topology Optimization in Networked Embedded Systems.
In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2008), pp. 74-81, Samos, Greece, July 21-24, 2008. ©1
| 35 C. Haubelt, J. Falk, C. Zebelein, J. Keinert, J. Teich and S. Bhattacharyya.
SystemCoDesigner - An ESL Design Methodology Based on the FunState MoC.
Talk at 2nd Artist Workshop on Models of Computation and Communication, Eindhoven, The Netherlands, July 3, 2008. ©1
| 34 C. Haubelt.
SystemCoDesigner: Automatic Design Space Exploration and Rapid Prototyping from Behavioral Models.
Talk at Center of Embedded Computer Systems, Irvine, CA, USA, June 13, 2008. ©1
| 33 C. Haubelt, M. Meredith, T. Schlichter and J. Keinert.
SystemCoDesigner: Automatic Design Space Exploration and Rapid Prototyping from Behavioral Models.
In Proceedings of 2008 ACM/EDAC/IEEE Design Automation Conference (DAC 2008), pp. 580-585, Anaheim, CA, USA, June 8-13, 2008. ©1
| 32 M. Lukasiewycz, M. Glaß, C. Haubelt, J. Teich, R. Regler and B. Lang.
Concurrent Topology and Routing Optimization in Automotive Network Integration.
In Proceedings of the 2008 ACM/EDAC/IEEE Design Automation Conference (DAC 2008), pp. 626-629, Anaheim, CA, U.S.A., June 08-13, 2008. ©1
| 31 C. Zebelein, J. Falk, C. Haubelt and J. Teich.
Classification of General Data Flow Actors into Known Models of Computation.
In Proc. of the Sixth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2008), pp. 119-128, Anaheim, CA, USA, June 5-7, 2008. ©1
| 30 M. Glaß, M. Lukasiewycz, F. Reimann, C. Haubelt and J. Teich.
Symbolic Reliability Analysis and Optimization of ECU Networks.
Proceedings of Design, Automation and Test in Europe (DATE 2008), IEEE Computer Society, pp. 158-163, Munich, Germany, March 10-14, 2008. ©1
| 29 M. Streubühr, M. Jäntsch, C. Haubelt, J. Teich and A. Schneider.
Semi-Automatic Generation of mixed Hardware-Software Prototypes from Simulink Models.
11. GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Freiburg, Germany, pp. 139-148, March 03-05, 2008. ©1
| 28 J. Keinert, C. Haubelt and J. Teich.
Synthesis of Multi-Dimensional High-Speed FIFOs for Out-of-Order Communication.
Proceedings of the International Conference on Architecture of Computing Systems (ARCS 2008), pp. 130-143, Dresden, Germany, February 25-28, 2008. ©1
  | | 2007 | 27 J. Keinert, J. Falk, C. Haubelt and J. Teich.
Actor-Oriented Modeling and Simulation of Sliding Window Image Processing Algorithms.
Proceedings of the 2007 IEEE/ACM/IFIP Workshop of Embedded Systems for Real-Time Multimedia (ESTIMEDIA 2007), pp. 113-118, Salzburg, Oct. 4-5, 2007. ©1
| 26 T. Streichert, M. Glaß, C. Haubelt and J. Teich.
Design space exploration of reliable networked embedded systems.
In Journal on Systems Architecture (JSA). Volume 53(10): 751-763, 2007. ©1
| 25 J. Gladigau, C. Haubelt, B. Niemann and J. Teich.
Mapping Actor-Oriented Models to TLM Architectures.
In Proceedings FDL'07, Forum on specification and Design Languages 2007, Barcelona, Spain, September 18-20, 2007. ©1
| 24 J. Keinert, C. Haubelt and J. Teich.
Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow.
In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, Acoustics, Speech, and Signal Processing (IC-SAMOS VII), Samos (Greece) July 16-19, 2007. ©1
| 23 M. Glaß, M. Lukasiewycz, T. Streichert, C. Haubelt and J. Teich.
Reliability-Aware System Synthesis.
In Proceedings of Design, Automation and Test in Europe (DATE 2007), IEEE Computer Society, Nice, France, pp. 409-414, April 16-20, 2007. ©1
| 22 M. Streubühr, C. Riedel, C. Haubelt and J. Teich.
System Level Modeling and Performance Simulation for Dynamic Reconfigurable Computing Systems in SystemC.
10. Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen", Erlangen, Germany, pp. 59-68, March 05-07, 2007. ©1
| 21 C. Haubelt, J. Falk, J. Keinert, T. Schlichter, M. Streubühr, A. Deyhle, A. Hadert and J. Teich.
A SystemC-based Design Methodology for Digital Signal Processing Systems.
In EURASIP Journal on Embedded Systems, Special Issue on Embedded Digital Signal Processing Systems, Volume 2007 (2007), Article ID 47580, 22 pages, March 2007. ©1
| | 2006 | 20 C. Haubelt.
SystemCoDesigner - Eine Entwurfsmethodik für SystemC-Beschreibungen.
Invited Talk, Siemens Medical Solutions, July 17, Erlangen, Germany, 2006. ©1
| 19 C. Haubelt, T. Schlichter and J. Teich.
Improving Automatic Design Space Exploration by Integrating Symbolic Techniques into Multi-Objective Evolutionary Algorithms.
In International Journal of Computational Intelligence Research (IJCIR), Special Issue on Multiobjective Optimization and Applications, Volume 2, Issue 3. pp. 239-254, 2006. ©1
| 18 J. Keinert, C. Haubelt and J. Teich.
Modeling and Analysis of Windowed Synchronous Algorithms.
In Proceedings of the 31st International Conference on Acoustics, Speech, and Signal Processing (ICASSP2006), Toulouse (France) May 14-19, 2006. ©1
| 17 C. Haubelt.
SystemCoDesigner - Eine Entwurfsmethodik für SystemC-Beschreibungen.
Invited talk, Institute of Computer and Communication Network Engineering, TU Braunschweig, April 28, Braunschweig, Germany, 2006. ©1
| 16 C. Haubelt.
SystemCoDesigner - Eine Entwurfsmethodik für SystemC-Beschreibungen.
Invited Talk, Oldenburger Forschungs- und Entwicklungsinstitut für Informatik-Werkzeuge und Systeme OFFIS, April 24, Oldenburg, Germany, 2006. ©1
| 15 M. Streubühr, J. Falk, C. Haubelt, J. Teich, R. Dorsch and T. Schlipf.
Task-Accurate Performance Modeling in SystemC for Real-Time Multi-Processor Architectures.
In Proceedings of Design, Automation and Test in Europe (DATE 2006), IEEE Computer Society, Munich, Germany, pp. 480-481, March 6-10, 2006. ©1
| 14 T. Schlichter, M. Lukasiewycz, C. Haubelt and J. Teich.
Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms.
In Proceedings of IEEE Computer Society Annual Symposium on VLSI. Karlsruhe, Germany, pp. 309-314, March 2-3, 2006. ©1
| | 2005 | 13 C. Haubelt.
SystemCoDesigner: Entwurfsraumexploration für SystemC-Beschreibungen.
Invited Talk, Fraunhofer Institut für Integrierte Schaltungen (FhG-IIS), December 12, Erlangen, Germany, 2005. ©1
| 12 T. Schlichter, C. Haubelt, F. Hannig and J. Teich.
Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems.
In Proceedings of Application-specific Systems, Architectures and Processors (ASAP). Samos, Greece, pp. 9-14, July 23-25, 2005. ©1
| 11 C. Haubelt.
Automatic Model-Based Design Space Exploration for Embedded Systems - A System Level Approach.
Dissertation, University of Erlangen-Nuremberg, ISBN 3-89574-572-3, © Verlag Dr. Köster, Berlin, 2005. ©1
| 10 T. Schlichter, C. Haubelt and J. Teich.
Improving EA-based Design Space Exploration by Utilizing Symbolic Feasibility Tests.
In Proceedings of Genetic and Evolutionary Computation Conference (GECCO). Washington, DC, pp. 1945-1952, June 25-29, 2005. ©1
| 9 C. Haubelt.
A System-Level Approach to Automated Model-Based Design Space Exploration.
Invited Talk at the Computer Engineering and Networks Laboratory (TIK), ETH Zurich, March 31, Zurich, Switzerland, 2005. ©1
| 8 C. Haubelt, J. Gamenik and J. Teich.
Initial Population Construction for Convergence Improvement of MOEAs.
In Evolutionary Multi-Criterion Optimization, Carlos A. Coello Coello, Arturo Hernández Aguirre, and Eckart Zitzler (eds.), Lecture Notes in Computer Science, Vol. 3410, pp. 191-205, Springer, Berlin, Heidelberg, New York, 2005. ©1
| 7 C. Haubelt.
Automated Model-Based Design Space Exploration of Embedded Systems.
PhD Forum at the Design, Automation and Test in Europe (DATE'05), March 7-11, Munich, Germany, 2005. ©1
| 6 C. Haubelt, S. Otto, C. Grabbe and J. Teich.
A System-Level Approach to Hardware Reconfigurable Systems.
In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC'05). Shanghai, China, pp. 298-301, January 18-21, 2005. ©1
| | 2004 | 5 C. Haubelt.
Design Space Exploration for Distributed Hardware Reconfigurable Systems.
In Field-Programmable Logic and Applications by Jürgen Becker, Marco Platzner, and Serge Vernalde (Eds.). In Lecture Notes in Computer Science, Vol. 3203, p. 1171, Springer, Berlin, Heidelberg, 2004. ©1
| | 2003 | 4 C. Haubelt and J. Teich.
Accelerating Design Space Exploration.
In Proceedings of 5th International Conference on ASIC (ASICON 2003), pp. 79-84, Beijing, China, October 21-24, 2003. ©1
| 3 C. Haubelt, S. Mostaghim, J. Teich and A. Tyagi.
Solving Hierarchical Optimization Problems Using MOEAs.
In Evolutionary Multi-Criterion Optimization, Carlos M. Fonseca, Peter J. Fleming, Eckart Zitzler, Kalyanmoy Deb, and Lothar Thiele (eds.),
Lecture Notes in Computer Science, Vol. 2632, pp. 162-176, Springer, Berlin, Heidelberg, New York, 2003. ©1
| 2 C. Haubelt, S. Mostaghim, F. Slomka, J. Teich and A. Tyagi.
Hierachical Synthesis of Embedded Systems Using Evolutionary Algorithms.
In Evolutionary Algorithms in System Design by Drechsler, R. and Drechsler, N., in Genetic Algorithms and Evolutionary Computation (GENA), pp. 63-104, Kluwer Academic Publishers, Boston, Dordrecht, London, 2003. ©1
| 1 C. Haubelt and J. Teich.
Accelerating Design Space Exploration Using Pareto-Front Arithmetics.
In Proceedings ASP-DAC 2003, Asia and South Pacific Design Automation Conference, pp. 525-531, Kitakyushu, Japan, January 21-24, 2003. ©1
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Semester and Diploma Thesis
| 2009 | 10 S. Graf.
Virtuelle Integration von Fahrzeugfunktionalität in die AUTOSAR-Laufzeitumgebung.
Diplomarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, November, 2009. ©1
| | 2008 | 9 S. Graf.
Simulative Laufzeituntersuchung in Automotive-Anwendungen mit SystemC.
Studienarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, November, 2008. ©1
| 8 M. Jäntsch.
Modellierung und Simulation eines elektronischen Bremssystems im Personenkraftwagen.
Projektarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Juli, 2008. ©1
| | 2007 | 7 T. Schilling.
Konzeption und Implementierung von Transformationen und Optimierungsmethoden zur automatischen Hardwaresynthese aus SysteMoC-Systembeschreibungen.
Diplomarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Dezember 2007. ©1
| | 2006 | 6 C. Riedel.
Entwurfsraumexploration und Leistungsbewertung von dynamisch rekonfigurierbaren Systemen.
Diplomarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Juli, 2006. ©1
| 5 M. Streubühr.
Untersuchung zum Einsatz simulativer Verfahren zur Zeitanalyse in der Entwurfsraumexploration eingebetteter Systeme.
Diplomarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Januar 2006. ©1
| 4 J. Gladigau.
Symbolische Ablaufplanung von SysteMoC-Beschreibungen.
Diploma thesis (Diplomarbeit), Department of Computer Science, University of Erlangen-Nuremberg, Germany, June 2006. ©1
| | 2005 | 3 M. Streubühr.
Generierung von Simulatonsmodellen für heterogene eingebettete Systeme.
Studienarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, April 2005. ©1
| | 2004 | 2 J. Gamenik.
Bewertungskriterien für mengenorientierte Explorationsverfahren.
Diplomarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, April 2004 . ©1
| | 2003 | 1 S. Otto.
Systemsynthese hierarchischer Prozessgraphen für rekonfigurierbare Hardware.
Diplomarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, November 2003. ©1
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