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Optimization methodologies for reconfiguration management on reconfigurable hardware nodes - Publications
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Project ReCoNodes
Publications
| 2010 | 71 J. Teich.
The DFG Priority Program 1148 Reconfigurable Computing - Achievements and Lessons Learned.
DATE Friday Workshop The European Landscape of Reconfigurable Computing: Lessons Learned, new Perspectives and Innovations, Dresden, Germany, March 2010. Invited Talk. ©1
 | 70 S. Fekete, T. Kamphans, N. Schweer, C. Tessars, J. van der Veen, A. Ahmadinia, J. Angermeier, D. Koch, M. Majer and J. Teich.
ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices.
In Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications, p. 199-222, Springer, Heidelberg, February 2010. ©1
| 69 M. Platzner, J. Teich and N. Wehn.
Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications.
Springer, Heidelberg, February 2010. ©1
| 68 J. Angermeier, C. Bobda, M. Majer and J. Teich.
Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform.
In Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications, p. 51-71, Springer, Heidelberg, February 2010. ©1
| | 2009 | 67 E. Sibirko.
Paralleles Sortieren auf der Erlangen Slot Machine.
Studienarbeit, Lehrstuhl für Informatik 12, Universität Erlangen-Nürnberg, Dezember 2009. ©1
| 66 R. Rauschecker.
Simulator zur Darstellung der Virtualisierung von rekonfigurierbaren Hardware-Strukturen.
Projektarbeit, Lehrstuhl für Informatik 12, Universität Erlangen-Nürnberg, September 2009. ©1
| 65 D. Koch, C. Beckhoff and J. Teich.
A Communication Architecture for Complex Runtime Reconfigurable Systems and its Implementation on Spartan-3 FPGAs.
Proceedings of the 17th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2009), pp. 233-236, Monterey, California, USA
Extended paper version:. ©2
 | 64 J. Sim, W. Wong and J. Teich.
Optimal Placement-aware Trace-based Scheduling of Hardware Reconfigurations for FPGA Accelerators.
Proceedings 17th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2009), Napa, California, pp. 279-282, April, 2009. ©1
| 63 D. Koch, C. Beckhoff and J. Teich.
Minimizing Internal Fragmentation by Fine-grained Two-dimensional Module Placement for Runtime Reconfigurable Systems.
Proceedings 17th Annual IEEE Symposium on
Field-Programmable Custom Computing Machines (FCCM 2009), pp. 251-254, Napa, California, April, 2009. ©1
| 62 D. Koch, C. Beckhoff and J. Teich.
Hardware Decompression Techniques for FPGA-based Embedded Systems.
ACM Transactions on Reconfigurable Technology and Systems (TRETS),
vol.2, no. 9, June 2009. ©1
| | 2008 | 61 M. Schmid, D. Ziener and J. Teich.
Netlist-Level IP Protection by Watermarking for LUT-Based FPGAs.
In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2008), pp. 209-216, Taipei, Taiwan, December 08-10, 2008. ©1
| 60 S. Fekete, J. van der Veen, A. Ahmadinia, D. Göhringer, M. Majer and J. Teich.
Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.16(9):1210-1219, September 2008. ©1
| 59 C. Claus, W. Stechele, M. Kovatsch, J. Angermeier and J. Teich.
A comparison of embedded reconfigurable video-processing architectures.
Proceedings of 18th International Conference on Field Programmable Logic and Applications (FPL 2008), Heidelberg, Germany, September 8 - 10, 2008, pp. 587-590.. ©1
| 58 D. Koch, T. Streichert, C. Haubelt and J. Teich.
Logic Chip, Method and Computer Program for Providing a Configuration Information for a Configurable Logic Chip.
Patent PCT/EP2008/007343, filed 8.9.2008. ©1
| 57 D. Koch, C. Beckhoff and J. Teich.
ReCoBus-Builder – a Novel Tool and Technique to Build Statically and Dynamically Reconfigurable Systems for FPGAs.
Proceedings of International Conference on Field-Programmable Logic and Applications (FPL 08), pp. 119-124, Heidelberg, Germany. ©1
| 56 S. Fekete, J. van der Veen, J. Angermeier, D. Koch and J. Teich.
No-Break Dynamic Defragmentation of Reconfigurable Devices.
Proceedings of International Conference on Field-Programmable Logic and Applications (FPL 08), pp. 113-118, Heidelberg, Germany. ©1
| 55 D. Koch, T. Streichert, C. Haubelt and J. Teich.
Logic Chip, Logic System and Method for Designing a Logic Chip.
Patent PCT/EP2008/007342, filed 8.9.2008. ©1
| 54 H. Killer.
Leistungsbewertung von Strategien zur dynamischen Hardware-Rekonfiguration.
Studienarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, August 2008. ©1
| 53 M. Kovatsch.
Entwurf und Test von Speicherinterfaces für Module für die Bildverarbeitung auf der Erlangen Slot Machine (ESM).
Projektarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Mai 2008. ©1
| 52 U. Batzer.
Hardware-Software-Co-Design von Echtzeitbilderkennungsalgorithmen für die Erlangen Slot Machine (ESM).
Projektarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Mai 2008. ©1
| 51 J. Angermeier and J. Teich.
Heuristics for Scheduling Reconfigurable Devices with Consideration of Reconfiguration Overheads.
Proceedings 15th Reconfigurable Architectures Workshop (RAW 2008), pp. 1-8,
Miami, Florida, April 2008. ©1
| 50 D. Koch, C. Haubelt and J. Teich.
Efficient Reconfigurable On-Chip Buses for FPGAs.
Proceedings 16th Annual IEEE Symposium on
Field-Programmable Custom Computing Machines (FCCM 2008), pp. 287-290, Palo Alto, California,
April 14-15, 2008. ©1
| 49 J. Angermeier, U. Batzer, M. Majer, J. Teich, C. Claus and W. Stechele.
Reconfigurable HW/SW Architecture of a Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System.
Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing (ARC), Lecture Notes in Computer Science (LNCS), pp. 149-159, Springer, London, United Kingdom, March 26-28, 2008. ©1
| | 2007 | 48 D. Koch, T. Streichert, C. Haubelt and J. Teich.
Efficient Reconfigurable On-Chip Buses.
Europäisches Patent EP07017975, Anmeldetag 13.09.2007. ©1
| 47 J. Teich.
Reconfigurable Computing Systems.
it - Information Technology, http://it-information-technology.de, Oldenbourg Wissenschaftsverlag, vol. 49(3):139-142, 2007. ©1
| 46 B. Kleinert.
Kernelmodularchitektur für den Rekonfigurationsmanager der Erlangen Slot Machine.
Studienarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, August 2007. ©1
| 45 S. Fekete, J. van der Veen, J. Angermeier, D. Göhringer, M. Majer and J. Teich.
Scheduling and communication-aware mapping of HW-SW modules for dynamically and partially reconfigurable SoC architectures.
In Proceedings of the Dynamically Reconfigurable Systems Workshop (DRS 2007), Zürich, Switzerland, pages 151-160, March 15, 2007. ©1
| 44 J. Angermeier, D. Göhringer, M. Majer and J. Teich.
The Erlangen Slot Machine: A flexible FPGA-platform for partially reconfigurable applications at run-time.
Tutorial, 20th International Conference on Architecture of Computing Systems (ARCS 2007), Springer LNCS series, Swiss Federal Institute of Technology (ETH) Zurich, Switzerland, March 12-15, 2007. ©1
| 43 M. Majer, J. Teich, A. Ahmadinia and C. Bobda.
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-Based Computer.
Journal of VLSI Signal Processing Systems, Springer, vol. 47(1), pages 15-31, March 2007. ©1
| 42 T. Stark.
Entwurf und Implementierung einer Treiberarchitektur und ESM-Shell für die Erlangen Slot Machine.
Diplomarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Februar 2007. ©1
| 41 J. Zhai and T. Stark.
Entwurf und Implementierung einer Treiberarchitektur und ESM-Shell für die Erlangen Slot Machine.
.. ©1
| 40 N. Bergmann, M. Platzner and J. Teich.
Dynamically Reconfigurable Architectures.
EURASIP Journal of Embedded Systems, Volume 2007 (2007), Article ID 28405, 2 pages, February 2007. ©1
| 39 P. Shterev.
SlotComposer – Design and Implementation of an Automated Design Flow for Partially Reconfigurable FPGA Modules.
Master-Thesis, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Januar 2007. ©1
| 38 A. Ahmadinia, C. Bobda, S. Fekete, J. Teich and J. van der Veen.
Optimal free-space management and routing-conscious dynamic placement for reconfigurable computing.
IEEE Transactions on Computers, volume 56, number 3, pages 673-680, 2007. ©1
| 37 J. Angermeier, D. Göhringer, M. Majer, J. Teich, S. Fekete and J. van der Veen.
The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Reconfigurable Computing.
it - Information Technology, http://it-information-technology.de, Oldenbourg Wissenschaftsverlag, vol. 49(3):143-148, 2007. ©1
| | 2006 | 36 D. Ziener and J. Teich.
FPGA Core Watermarking Based on Power Signature Analysis.
In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2006), pp. 205-212, Bangkok, Thailand, December 13-15, 2006. ©1
| 35 J. Grembler.
Dynamisch rekonfigurierbare Videomodule auf der Erlangen Slot Machine.
Diplomarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, November 2006. ©1
| 34 C. Freiberger.
Reconfiguration Manager for the Erlangen Slot Machine.
Diplomarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Oktober 2006. ©1
| 33 M. Majer.
An FPGA-Based Dynamically Reconfigurable Platform: from Concept to Realization.
In Proceedings of 16th International Conference on Field Programmable Logic and Applications, pp. 963-964, Madrid, Spain, August 28-30, 2006. ©1
| 32 D. Ziener, S. Aßmus and J. Teich.
Identifying FPGA IP-Cores based on Lookup Table Content Analysis.
In Proceedings of 16th International Conference on Field Programmable Logic and Applications, Madrid, Spain, pp. 481-486, August 28-30, 2006. ©1
| 31 S. Fekete, J. van der Veen, M. Majer and J. Teich.
Minimizing communication cost for reconfigurable slot modules.
In Proceedings 16th International Conference on Field-Programmable Logic and Applications (FPL 2006), pp. 535-540, Madrid, Spain, August 28-30, 2006. ©1
| 30 S. Fekete, E. Köhler and J. Teich.
Higher-dimensional packing with order constraints.
SIAM Journal on Discrete Mathematics,Vol. 20, No. 4, pp. 1056-1078, 2006. ©1
| 29 D. Göhringer, M. Majer and J. Teich.
Bridging the Gap between Relocation and Available Technology: The Erlangen Slot Machine.
In Proceedings of the Dagstuhl Seminar Nº 06141 on Dynamically Reconfigurable Architectures, P. M. Athanas, J. Becker, G. Brebner, J. Teich (Eds.), ISSN 1862 - 4405, Dagstuhl, Germany, April 02-07, 2006. ©1
| 28 D. Koch, M. Körber and J. Teich.
Searching RC5-Keys with Distributed Reconfigurable Computing.
In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA 2006), Las Vegas, USA, June 26-29, 2006. ©1
| 27 A. Ahmadinia, C. Bobda and J. Teich.
Online Placement for Dynamically Reconfigurable Devices.
Int. J. Embedded Systems, Vol. 1, Nos. 3/4, pp.165-178, 2006. ©1
| 26 J. Becker, J. Teich, P. Athanas and G. Brebner.
Dynamically Reconfigurable Architectures.
Proceedings of the Dagstuhl Seminar Nº 06141, ISSN 1862 - 4405, Dagstuhl, Germany, April 02-07, 2006. ©1
| 25 M. Majer, A. Ahmadinia, C. Bobda and J. Teich.
A Flexible Reconfiguration Manager for the Erlangen Slot Machine.
In Proceedings of the Dynamically Reconfigurable Systems Workshop (DRS'2006), Frankfurt/Main, Germany, pp.183-194, March 16, 2006. ©1
| 24 C. Bobda, M. Platzner and J. Teich.
The Renaissance of FPGA-Based High-Performance Computing.
DATE'06 Friday Workshop, Conference Design Automation and Test in Europe, March 10, 2006, Munich, Germany. ©1
| | 2005 | 23 A. Ahmadinia, C. Bobda, T. Haller, A. Linarth, M. Majer and J. Teich.
Increasing the Flexibility in FPGA-Based Reconfigurable Platforms: The Erlangen Slot Machine.
In Proc. IEEE 2005 Conference on Field-Programmable Technology (FPT), Singapore, Singapore, pages 37-42, December 11-14, 2005. ©1
| 22 A. Ahmadinia, C. Bobda, J. Ding, M. Majer and J. Teich.
Modular Video Streaming on a Reconfigurable Platform.
In Proc. IFIP VLSI SOC 2005, pages 103-108, Perth, Australia, pp. 103-108, October 17-19, 2005. ©1
| 21 A. Ahmadinia, C. Bobda, S. Fekete, M. Majer, J. Teich and J. van der Veen.
DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices.
In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL),Tampere, Finland, pp. 153-158, August 24-26, 2005. ©1
| 20 A. Ahmadinia, C. Bobda, S. Fekete, F. Hannig, M. Majer, J. Teich and J. van der Veen.
Defragmenting the Module Layout of a Partially Reconfigurable Device.
In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, USA, pp. 92-101, June 27-30, 2005. ©1
| 19 A. Ahmadinia, C. Bobda, J. Ding, S. Fekete, M. Majer, J. Teich and J. van der Veen.
A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices.
In Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping, Montreal, Canada, pp. 84-90, June 8-10, 2005. ©1
| 18 A. Ahmadinia, C. Bobda, S. Fekete, T. Haller, A. Linarth, M. Majer, J. Teich and J. van der Veen.
The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform.
In Proceedings of the 2005 IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, USA, pp. 319-320, April 17-20, 2005. ©1
| 17 A. Ahmadinia, C. Bobda, M. Majer and J. Teich.
Packet Routing in Dynamically Changing Networks on Chip.
In Proceedings of the 12th Reconfigurable Architectures Workshop (RAW 2005), Denver, USA, p. 154b, IEEE Computer Society, April 4-5, 2005. ©1
| 16 A. Ahmadinia, C. Bobda, R. Kurapati, M. Majer and A. Niyonkuru.
Partial Configuration Design and Implementation Challenges on Xilinx Virtex FPGAs.
System Aspects in Organic and Pervasive Computing - Workshop Proceedings - Dynamically Reconfigurable Systems, Self-Organization and Emergence, Innsbruck, Austria, pp. 61-66, March 14-17, 2005. ©1
| 15 J. Teich.
The Future of Reconfigurable Computing.
DATE'05 Friday Workshop, Conference Design Automation and Test in Europe,
March 11, 2005, Munich, Germany. ©1
| 14 A. Ahmadinia, C. Bobda, T. Haller, A. Linarth, M. Majer and J. Teich.
The Erlangen Slot Machine (ESM): A Flexible Platform for Dynamic Reconfigurable Computing.
Board Demo at the University Booth at Design, Automation and Test in Europe (DATE 2005), Munich, Germany, March 7-11, 2005. ©1
| | 2004 | 13 A. Ahmadinia, C. Bobda, H. Kalte, D. Koch and J. Teich.
FPGA Architecture Extensions for Preemptive Multitasking and Hardware Defragmentation.
In Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology (FPT), Brisbane, Australia, pp. 433-436, December 6-8, 2004. ©1
| 12 A. Ahmadinia, C. Bobda, J. Ding and J. Teich.
Design and Implementation of Reconfigurable Multiple Bus on Chip (RMBoC).
Technical Report 02-2004, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, November 2004. ©1
| 11 A. Ahmadinia, B. Blodget, C. Bobda, M. Hübner, M. Majer and A. Niyonkuru.
Designing Partial and Dynamically Reconfigurable Applications on Xilinx Virtex-II FPGAs using HandelC.
Technical Report 03-2004, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, November 2004. ©1
| 10 A. Ahmadinia, C. Bobda, D. Koch, M. Majer and J. Teich.
Task Scheduling for Heterogeneous Reconfigurable Computers.
In Proceedings of the 17th Symposium on Integrated Circuits and Systems Design (SBCCI), Pernambuco, Brazil, pp. 22-27, ACM Press, September 7-11, 2004. ©1
| 9 A. Ahmadinia, C. Bobda, D. Koch, M. Majer and J. Teich.
A Dynamic NoC Approach for Communication in Reconfigurable Devices.
In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL), Antwerp, Belgium, LNCS 3203, pp. 1032-1036, Springer, August 30 - September 1, 2004. ©1
| 8 A. Ahmadinia, C. Bobda, S. Fekete, J. Teich and J. van der Veen.
Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices.
In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL), Antwerp, Belgium, LNCS 3203, pp. 847-851, Springer, August 30 - September 01, 2004. ©1
| 7 A. Ahmadinia.
Optimization Algorithms for Dynamic Reconfigurable Embedded Systems.
In Proceedings of International Conference on Field-Programmable Logic and Applications (FPL), Antwerp, Belgium, LNCS 3203, p. 1168, Springer, August 30 - September 1, 2004. ©1
| 6 A. Ahmadinia, M. Bednara, C. Bobda and J. Teich.
A New Approach for On-line Placement on Reconfigurable Devices.
In Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), Santa Fe, NM, U.S.A., April 26-30, 2004. ©1
| 5 A. Ahmadinia, C. Bobda, K. Danne and J. Teich.
Generation of Distributed Arithmetic Designs for Reconfigurable Applications.
In Proc. GI/ITG Dynamically Reconfigurable Systems Workshop at ARCS - Organic and Pervasive Computing, Augsburg, Germany, pp. 205-214, March 26, 2004. ©1
| 4 A. Ahmadinia, C. Bobda and J. Teich.
A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware.
In Proc. 17th International Conference on Architecture of Computing Systems (ARCS 2004), Augsburg, Germany, LNCS 2981, pp. 125-139, Springer, March 23-26, 2004. ©1
| | 2003 | 3 A. Ahmadinia, C. Bobda, K. Danne and J. Teich.
A New Approach for Reconfigurable Massively Parallel Computers.
In Proceedings of the IEEE International Conference on Field-Programmable Technology, Tokyo, Japan, pp. 391-394, December 15-17, 2003. ©1
| 2 A. Ahmadinia, C. Bobda and J. Teich.
Temporal Task Clustering for Online Placement on Reconfigurable Hardware.
In Proceedings of the IEEE International Conference on
Field-Programmable Technology, Tokyo, Japan, pp. 359-362, December 15-17, 2003. ©1
| 1 A. Ahmadinia and J. Teich.
Speeding up Online Placement for XILINX FPGAs by Reducing Configuration Overhead .
In Proceedings of the IFIP International Conference on VLSI-SOC, Darmstadt, Germany, pp. 118-122, December 1-3, 2003. ©1
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Studienarbeiten and Diploma Theses
| 2009 | 10 E. Sibirko.
Paralleles Sortieren auf der Erlangen Slot Machine.
Studienarbeit, Lehrstuhl für Informatik 12, Universität Erlangen-Nürnberg, Dezember 2009. ©1
| 9 R. Rauschecker.
Simulator zur Darstellung der Virtualisierung von rekonfigurierbaren Hardware-Strukturen.
Projektarbeit, Lehrstuhl für Informatik 12, Universität Erlangen-Nürnberg, September 2009. ©1
| | 2008 | 8 H. Killer.
Leistungsbewertung von Strategien zur dynamischen Hardware-Rekonfiguration.
Studienarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, August 2008. ©1
| 7 M. Kovatsch.
Entwurf und Test von Speicherinterfaces für Module für die Bildverarbeitung auf der Erlangen Slot Machine (ESM).
Projektarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Mai 2008. ©1
| 6 U. Batzer.
Hardware-Software-Co-Design von Echtzeitbilderkennungsalgorithmen für die Erlangen Slot Machine (ESM).
Projektarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Mai 2008. ©1
| | 2007 | 5 B. Kleinert.
Kernelmodularchitektur für den Rekonfigurationsmanager der Erlangen Slot Machine.
Studienarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, August 2007. ©1
| 4 T. Stark.
Entwurf und Implementierung einer Treiberarchitektur und ESM-Shell für die Erlangen Slot Machine.
Diplomarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Februar 2007. ©1
| 3 P. Shterev.
SlotComposer – Design and Implementation of an Automated Design Flow for Partially Reconfigurable FPGA Modules.
Master-Thesis, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Januar 2007. ©1
| | 2006 | 2 J. Grembler.
Dynamisch rekonfigurierbare Videomodule auf der Erlangen Slot Machine.
Diplomarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, November 2006. ©1
| 1 C. Freiberger.
Reconfiguration Manager for the Erlangen Slot Machine.
Diplomarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Oktober 2006. ©1
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