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ReCoBus - Publications
The following publications list only work that is closely related to the ReCoBus project.
You may also be interested in some of
our other papers on Hardware-Software-Co-Design.
The two projects ReCoNets and ReCoNodes provide
papers on reconfigurable computing and FPGA technology in general.
If you have published a paper related to the ReCoBus project, you can submit the title,
abstract, and bibtex entry to be listed on this side.
| 2009 | 13 D. Koch, C. Beckhoff and J. Teich.
A Communication Architecture for Complex Runtime Reconfigurable Systems and its Implementation on Spartan-3 FPGAs.
Proceedings of the 17th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2009), pp. 233-236, Monterey, California, USA
Extended paper version:. ©2
  | 12 D. Koch, C. Beckhoff and J. Teich.
Minimizing Internal Fragmentation by Fine-grained Two-dimensional Module Placement for Runtime Reconfigurable Systems.
Proceedings 17th Annual IEEE Symposium on
Field-Programmable Custom Computing Machines (FCCM 2009), pp. 251-254, Napa, California, April, 2009. ©1
| 11 D. Koch, C. Beckhoff and J. Teich.
Hardware Decompression Techniques for FPGA-based Embedded Systems.
ACM Transactions on Reconfigurable Technology and Systems (TRETS),
vol.2, no. 9, June 2009. ©1
| | 2008 | 10 D. Koch, T. Streichert, C. Haubelt and J. Teich.
Logic Chip, Method and Computer Program for Providing a Configuration Information for a Configurable Logic Chip.
Patent PCT/EP2008/007343, filed 8.9.2008. ©1
| 9 D. Koch, T. Streichert, C. Haubelt and J. Teich.
Logic Chip, Logic System and Method for Designing a Logic Chip.
Patent PCT/EP2008/007342, filed 8.9.2008. ©1
| 8 S. Fekete, J. van der Veen, J. Angermeier, D. Koch and J. Teich.
No-Break Dynamic Defragmentation of Reconfigurable Devices.
Proceedings of International Conference on Field-Programmable Logic and Applications (FPL 08), pp. 113-118, Heidelberg, Germany. ©1
| 7 D. Koch, C. Beckhoff and J. Teich.
ReCoBus-Builder – a Novel Tool and Technique to Build Statically and Dynamically Reconfigurable Systems for FPGAs.
Proceedings of International Conference on Field-Programmable Logic and Applications (FPL 08), pp. 119-124, Heidelberg, Germany. ©1
| 6 D. Koch, C. Haubelt and J. Teich.
Efficient Reconfigurable On-Chip Buses for FPGAs.
Proceedings 16th Annual IEEE Symposium on
Field-Programmable Custom Computing Machines (FCCM 2008), pp. 287-290, Palo Alto, California,
April 14-15, 2008. ©1
| | 2007 | 5 D. Koch, C. Beckhoff and J. Teich.
Bitstream Decompression for High Speed FPGA Configuration from Slow Memories.
In Proceedings of the IEEE International Conference on
Field-Programmable Technology 2007 (ICFPT'07), pp. 161-168. ©1
| 4 D. Koch, T. Streichert, C. Haubelt and J. Teich.
Efficient Reconfigurable On-Chip Buses.
Europäisches Patent EP07017975, Anmeldetag 13.09.2007. ©1
| | 2006 | 3 D. Koch, M. Körber and J. Teich.
Searching RC5-Keys with Distributed Reconfigurable Computing.
In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA 2006), Las Vegas, USA, June 26-29, 2006. ©1
| | 2004 | 2 A. Ahmadinia, C. Bobda, H. Kalte, D. Koch and J. Teich.
FPGA Architecture Extensions for Preemptive Multitasking and Hardware Defragmentation.
In Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology (FPT), Brisbane, Australia, pp. 433-436, December 6-8, 2004. ©1
| 1 D. Koch and J. Teich.
Platform-Independent Methodology for Partial Reconfiguration.
Proceedings of the 2004 ACM conference Computing Frontiers (CF 04), pp. 398-403, April 14-16, 2004, Ischia, Italy. ©1
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