Goals:

In the final phase, it should be possible to generate a set of possible architectures and their associated optimizing compiler in order to best perform a given class of applications due to given constraints. Therefore, we have to trade off multiple design goals, e.g., hardware cost, execution time, code size, etc. Often, these design goals are conflicting so that it is impossible to find a design point which is optimal in all design parameters. Here, we prune the huge possible design space for an architecture/compiler codesign to a relatively small set of so-called Pareto-optimal design points.

The design space is spanned by both

• the backend design space spanned by architecture parameters, e.g.,number and types of functional units, register set structure, etc., and
• the frontend design space spanned by possible code optimization strategies of the associated compiler.

The main problems tackled in this phase are:

• to formalize such a trade-off as a multi-objective optimization problem,
• to formally define the design space for such an architecture/compiler co-exploration,
• to define the constraints on the architecture as adequate objective functions, and
• to develop a sophisticated optimization strategy in order to prune the huge design space to a preferably small set of Pareto-optimal design points in reasonable time.

Future work is to maintain a library with Pareto-optimal design points due to a given class of applications. With such a library, we are able to optimally adapt the architecture and compiler settings for each program of a benchmark individually by dynamic hardware reconfiguration.

Recent Publications:

1. D. Fischer, U. Kastens, J. Teich, M. Thies, R. Weper. Design Space Characterization for Architecture/Compiler Co-Exploration; in: ACM SIG Proc. International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES2001). Atlanta, Ga. U.S.A.; November 2001. (<.ps.gz>)
2. D. Fischer, J. Teich, M.Thies, R. Weper. Efficient Architecture/Compiler Co-Exploration for ASIPs; in: ACM SIG Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES2002), October 8-11, Grenoble, France , pp. 27 - 34, October 2002. (<.ps.gz>)