Abstract In this paper we focus on the derivation of optimal code when generating high-speed event-driven compiled simulators for processor architectures described on register transfer level (RTL). The simulators' generation is part of a framework, which aims at architecture and compiler co-generation for special purpose processors. The main contribution of this paper is an efficient algorithm to generate optimal if-then-else structures in order to perform the update cycle during the event-driven simulation process. Our approach guarantees that during one simulation cycle a possible change of each register content is checked exactly once and that each register is updated at most once. Additionally, the proposed technique minimizes the code size of the generated simulator. The simulator's superior performance compared to an existing commercial simulator is shown. Finally, we demonstrate the pertinence of our approach by simulating a MIPS processor.