Abstract. In this paper, we introduce a methodology for the systematic mapping, evaluation, and exploration of massively parallel processor architectures that are designed for special purpose applications in the world of embedded computers. The investigated class of computer architectures can be described by massively parallel networked processing elements that, using today's hardware technology, may be implemented on a single chip (SoC - System on a Chip). Existing approaches for mapping computational-intensive algorithms to parallel architectures either consider the implementation in dedicated hardware or the implementation on a given supercomputer. Many intermediate solutions between these extremes are coming up ranging from fine-grained FPGAs to coarse-grained processor arrays. For these architectures, we propose in this contribution a co-design approach in the sense of designing special purpose parallel processor architectures and efficient mapping tools simultaneously.

^*Supported in part by the German Science Foundation (DFG) in project under contract TE 163/13-1 and ME 1625/4-1.
¹Department of Computer Science 12, Hardware-Software-Co-Design, University of Erlangen-Nuremberg, Germany. {hannig, dutta, kupriyanov, teich}@cs.fau.de
²Institute of Circuits and Systems, Department of Electrical Engineering and Information Technology, Dresden University of Technology, Germany. {schaffer, siegel, merker}@iee1.et.tu-dresden.de
³ENST Bretagne, Département Informatique, CS 83818, 29238 Plouzané Cédex, France. rk@enstb.org
⁴Architectures et Systèmes, Université de Bretagne Occidentale, Brest, France. bernard.pottier@univ-brest.fr
⁵IRISA, University of Rennes, France. {chillet, menard, sentieys}@irisa.fr