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Publikationen am Lehrstuhl für Hardware-Software-Co-Design
| 2010 | 25 M. Glaß, M. Lukasiewycz, C. Haubelt and J. Teich.
Towards Scalable System-Level Reliability Analysis.
To appear in Proceedings of the 2010 ACM/EDAC/IEEE Design Automation Conference (DAC 2010), Anaheim, CA, U.S.A., June 13-18, 2010. ©1
 | 24 T. Ziermann, N. Mühleis, S. Wildermann and J. Teich.
Self-organizing Distributed Reinforcement Learning Algorithm to Achieve Fair Bandwidth Allocation for Priority-based Bus Communication.
1st IEEE Workshop on Self-Organizing Real-Time systems (SORT 2010), Camora, Spain, May 2010, invited Paper. ©1
| 23 J. Sim, W. Wong, G. Walla, T. Ziermann and J. Teich.
Interprocedural Placement-Aware Configuration Prefetching for FPGA-based Systems.
To appear in Proceedings of the 18th Annual International IEEE Symposium on
Field-Programmable Custom Computing Machines (FCCM\'10), Charlotte, USA, May 02-04, 2010. ©1
 | 22 D. Ziener, F. Baueregger and J. Teich.
Using the Power Side Channel of FPGAs for Communication.
To appear in Proceedings of the 18th Annual International IEEE Symposium on
Field-Programmable Custom Computing Machines (FCCM'10), Charlotte, USA, May 02-04, 2010. ©1
| 21 J. Angermeier, J. Teich, T. Kamphans and S. Fekete.
Virtual Area Management: Multitasking on Dynamically Partially Reconfigurable Devices.
To appear in Proceedings of 17th Reconfigurable Architectures Workshop (RAW 2010), Atlanta, USA, April 2010. ©1
| 20 T. Ziermann and J. Teich.
Adaptive Traffic Scheduling Techniques for Mixed Real-Time and Streaming Applications on Reconfigurable Hardware.
To appear in Proceedings of 17th Reconfigurable Architectures Workshop (RAW), Atlanta, USA, April 19-20, 2010. ©2
| 19 F. Reimann, A. Kern, C. Haubelt, T. Streichert and J. Teich.
Echtzeitanalyse Ethernet-basierter E/E-Architekturen im Automobil.
In: Proc. of Automotive meets Electronics (AmE 2010), to appear.. ©1
| 18 T. Ziermann and J. Teich.
Electromagnetic Compatibility (EMC) of CAN+.
To appear in Proc. of Automotive meets Electronics (AmE 2010). ©1
| 17 T. Ritscher, S. Helwig and R. Wanka.
Design and Experimental Evaluation of Multiple Adaptation Layers in Self-optimizing Particle Swarm Optimization.
Proc. IEEE Congress on Evolutionary Computation (CEC 2010), to appear. ©1
| 16 J. Teich.
DFG Priority Program 1148 Reconfigurable Computing - Achievements and Lessons Learned.
DATE Friday Workshop The European Landscape of Reconfigurable Computing: Lessons Learned, new Perspectives and Innovations, Dresden, Germany, March 2010. Invited Talk. ©1
| 15 H. Dutta, F. Hannig and J. Teich.
PARO - A Design Tool for Synthesis of Hardware Accelerators for SoCs.
Tool Presentation at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March 8-12, 2010. ©1
| 14 M. Lukasiewycz, M. Glaß and J. Teich.
Robust Design of Embedded Systems.
To appear in Proceedings of Design, Automation and Test in Europe (DATE'10), Dresden, Germany, March 08-12, 2010. ©1
| 13 C. Zebelein, J. Falk, C. Haubelt, J. Teich and R. Dorsch.
Efficient High-Level Modeling in the Networking Domain.
To appear in Proceedings of Design, Automation and Test in Europe (DATE'10), Dresden, Germany, March 08-12, 2010. ©1
| 12 M. May, N. Wehn, A. Bouajila, J. Zeppenfeld, W. Stechele, A. Herkersdorf, D. Ziener and J. Teich.
A Rapid Prototyping System for Error-Resilient Multi-Processor Systems-on-Chip.
To appear in Proceedings of Design, Automation and Test in Europe (DATE\'10), Dresden, Germany, March 08-12, 2010. ©1
| 11 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Comparison of Parallelization Frameworks for Shared Memory Multi-Core Architectures.
Proceedings of the Embedded World Conference, Nuremberg, Germany, March 03-05, 2010. ©1
| 10 M. Schmid, F. Hannig, J. Teich, R. Diefenbach, H. Pettendorf and H. Hornegger.
Discourse on Extending Embedded Medical Image Processing Systems Using the High Speed Serial RapidIO Interconnect.
To appear in Proceedings of the Embedded World Conference, Nuremberg, Germany, March 03-05, 2010.. ©1
| 9 R. Kiesel, O. Löhlein, A. Terzis, M. Streubühr, C. Haubelt and J. Teich.
Actor-oriented Modeling of Driver Assistance Systems for Efficient Multi-Core ECU Implementation..
In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, to appear, Dresden, Germany, February 2010. ©1
| 8 J. Falk, C. Zebelein, C. Haubelt, J. Teich and R. Dorsch.
Integrating Hardware/Firmware Verification Efforts Using SystemC High-Level Models.
J. Falk, C. Zebelein, C. Haubelt, J. Teich and R. Dorsch
Integrating Hardware/Firmware Verification Efforts Using SystemC High-Level Models.
In 13. ITG/GI/GMM Workshop für Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen,
Fraunhofer IIS/EAS Dresden, pp. 137-146, February 22-24, 2010. ©1
| 7 M. Platzner, J. Teich and N. Wehn.
Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications.
Springer, Heidelberg, February 2010. ©1
| 6 M. Mühlenthaler and R. Wanka.
Improving Bitonic Sorting by Wire Elimination.
Proc. 23rd PARS-Workshop on Parallel Systems and Architectures of the 23rd Int. Conf. on Architecture of Computing Systems (ARCS), pp. 15-22, 2010. ©1
| 5 S. Fekete, T. Kamphans, N. Schweer, C. Tessars, J. van der Veen, A. Ahmadinia, J. Angermeier, D. Koch, M. Majer and J. Teich.
ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices.
In Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications, p. 199-222, Springer, Heidelberg, February 2010. ©1
| 4 J. Angermeier, C. Bobda, M. Majer and J. Teich.
Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform.
In Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications, p. 51-71, Springer, Heidelberg, February 2010. ©1
| 3 D. Koch, T. Streichert, C. Haubelt, F. Reimann and J. Teich.
ReCoNets – Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections.
In Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications, p. 223-244, Springer, Heidelberg, February 2010. ©1
| 2 M. Glaß, D. Herrscher, H. Meier, M. Piastowski and P. Schoo.
SEIS - Sicherheit in Eingebetteten IP-Basierten Systemen.
In ATZelektronik. Volume 5(1), pp. 50-55, February 2010. ©1
| 1 M. Glaß, M. Lukasiewycz, C. Haubelt and J. Teich.
Lifetime Reliability Optimization for Embedded Systems: A System-Level Approach.
Proceedings of IEEE International Workshop on Reliability Aware System Design and Test (RASDAT '10), pp. 17-22, Bangalore, India, January 07-08, 2010. ©1
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