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CV |
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| March 31, 1978 |
born in Alzenau i.Ufr., Germany |
| 08/2002 |
Diploma degree in EE,
University of Applied Sciences Aschaffenburg, Germany |
| 09/2002 - 03/2003 |
Developer at the
University of Applied Sciences Aschaffenburg, Germany |
| 05/2003 - 06/2009 |
Researcher and developer at the
Fraunhofer Institute for Integrated Circuits (IIS), Germany |
| since 2003 |
Researcher at the
Department of Computer Science 12 (Hardware-Software-Co-Design), University of Erlangen-Nuremberg, Germany |
| since 2010 |
Head of the Reconfigurable Computing Group at the Department of Computer Science 12 (Hardware-Software-Co-Design), University of Erlangen-Nuremberg, Erlangen, Germany |
| 07/2010 |
Dr.-Ing. degree in Computer Science, University of Erlangen-Nuremberg, Erlangen, Germany |
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| Experience |
Petri AG, Aschaffenburg, Germany
09/1994 - 07/1997 |
Apprenticeship: electrical engineering |
IBM Entwicklung GmbH, Böblingen, Germany
09/2000 - 02/2001 |
Internship at IBM Germany Development Labs. Verification of dynamic logic SRAM models. |
University of Applied Sciences Aschaffenburg, Germany
10/2001 - 08/2002 |
Diploma: Analysis and hardware implementation of a multi symbol arithmetic coder. |
University of Applied Sciences Aschaffenburg, Germany
09/2002 - 03/2003 |
Project thesis: Analysis and implementation of an Alarm and Status Management System with an J2EE Application Server |
Fraunhofer Institute for Integrated Circuits (IIS), Germany
05/2003 - 06/2009 |
Design and implementation of high speed FPGA cores for image and signal processing
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Research Interests |
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 IP core watermarking
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Design of signal processing FPGA cores
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Reliable and fault tolerant embedded systems
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Efficient usage of FPGA structures
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Secure embedded systems
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Partial dynamic reconfiguration
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Education |
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Awards |
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| Best Paper Award, FPT 2006 |
D. Ziener and J. Teich. FPGA Core Watermarking Based on Power Signature Analysis.
In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2006), pp. 205-212, Bangkok, Thailand, December 13-15, 2006. |
| HiPEAC Award, 2010 |
D. Ziener, F. Baueregger and J. Teich. Using the Power Side Channel of FPGAs for Communication. In Proceedings of the 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 10), Charlotte, USA, May 02-04, pp. 237-244, 2010. |
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Publications |
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| 2012 | 28 C. Dennl, D. Ziener and J. Teich.
On-the-fly Composition of FPGA-Based SQL Query Accelerators Using A Partially Reconfigurable Module Library.
Proceedings of the IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM'12), Toronto, Canada, April 29th - May 1st, 2012 (to appear). ©1
 | 27 D. Koch, J. Torresen, C. Beckhoff, D. Ziener, C. Dennl, V. Breuer, J. Teich, M. Feilen and W. Stechele.
Partial Reconfiguration on FPGAs in Practice - Tools and Applications.
To appear in Tutorial Proceedings of the 2012 Architecture of Computing Systems (ARCS'12), Munich, Germany. February 28-29, 2012. ©1
| | 2011 | 26 T. Ziermann, B. Schmidt, M. Mühlenthaler, D. Ziener, J. Angermeier and J. Teich.
An FPGA Implementation of a Threat-based Strategy for Connect6.
Proceedings of the International Conference on Field-Programmable Technology (FPT'11), New Delhi, India. Dec. 12-14, 2011. ©1
| 25 J. Angermeier, D. Ziener, M. Glaß and J. Teich.
Runtime Stress-Aware Replica Placement on Reconfigurable Devices under Safety Constraints.
Proceedings of the International Conference on Field-Programmable Technology (FPT'11), New Delhi, India. Dec. 12-14, 2011. ©1
| 24 S. Wildermann, F. Reimann, D. Ziener and J. Teich.
Symbolic Design Space Exploration for Multi-Mode Reconfigurable Systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 129-138, Taipei, Taiwan. Oct. 9-14, 2011. (Best Paper Candidate). ©1
| 23 J. Angermeier, D. Ziener, M. Glaß and J. Teich.
Stress-Aware Module Placement on Reconfigurable Devices.
Proceedings of the Conference on Field-Programmable Logic and Applications (FPL 2011), pp. 277-281, Chania, Crete, Greece. Sep 5-7. 2011. ©1
| 22 S. Wildermann, D. Ziener and J. Teich.
Unifying Partitioning and Placement for SAT-based Exploration of Heterogeneous Reconfigurable SoCs.
Proceedings of the Conference on Field Programmable Logic and Applications (FPL 2011), pp. 429-434, Chania, Crete, Greece, Sep. 5-7, 2011. ©1
| 21 D. Ziener, S. Wildermann, A. Oetken, A. Weichslgartner and J. Teich.
A Flexible Smart Camera System based on a Partially Reconfigurable Dynamic FPGA-SoC.
Proceedings of the Workshop on Computer Vision on Low-Power Reconfigurable Architectures at FPL 2011, pp. 29-30, Chania, Crete, Greece, Sep. 4, 2011. ©1
 | 20 J. Teich and D. Ziener.
Verifying the Authorship of Embedded IP Cores: Watermarking and Core Identification Techniques.
Proceedings of the International Conference on
Engineering of Reconfigurable Systems and Algorithms (ERSA'11), pp. 93-103, Las Vegas, USA, Jul. 18-21, 2011. ©1
| | 2010 | 19 D. Ziener and J. Teich.
New Directions for FPGA IP Core Watermarking and Identification.
In Dagstuhl Seminar 10281 Proceedings, 2010. ©1
| 18 D. Ziener, M. Schmid and J. Teich.
Robustness Analysis of Watermark Verification Techniques for FPGA Netlist Cores.
In Design Methodologies for Secure Embedded Systems, A. Biedermann and H. Gregor Molter (Eds.), Lecture Notes in Electrical Engineering, volume 78, pp. 105-127, Springer-Verlag, Berlin Heidelberg, 2010. ©1
| 17 D. Ziener.
Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs.
Dissertation, University of Erlangen-Nuremberg, ISBN 978-3-86853-657-7, Verlag Dr. Hut, Munich, Germany, July, 2010. ©1
| 16 D. Ziener, F. Baueregger and J. Teich.
Multiplexing Methods for Power Watermarking.
In Proceedings of the IEEE Int. Symposium on Hardware-Oriented Security and Trust (HOST 2010), pp. 54-59, Anaheim, USA, June 13-14, 2010. ©2
| 15 D. Ziener, F. Baueregger and J. Teich.
Using the Power Side Channel of FPGAs for Communication.
In Proceedings of the 18th Annual International IEEE Symposium on
Field-Programmable Custom Computing Machines (FCCM'10), pp. 237-244, Charlotte, USA, May 02-04, 2010. ©1
| 14 M. May, N. Wehn, A. Bouajila, J. Zeppenfeld, W. Stechele, A. Herkersdorf, D. Ziener and J. Teich.
A Rapid Prototyping System for Error-Resilient Multi-Processor Systems-on-Chip.
Proceedings of Design, Automation and Test in Europe (DATE'10), Dresden, Germany, March 08-12, pp. 375-380, 2010. ©1
| | 2009 | 13 V. Schöber, O. Bringmann, A. Herkersdorf, W. Stechele, N. Wehn, M. May, D. Ziener, A. Bouajila, D. Baldin, J. Zeppenfeld, B. Sanders, J. Teich, M. Sebastian, R. Ernst and D. Treytnar.
AIS-Autonomous Integrated Systems.
In newsletter edacentrum 04 2009, pp. 05-13, edacentrum, Hannover, 2009. ©1
| 12 D. Ziener and J. Teich.
Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs.
Int. Journal of Autonomous and Adaptive Communications Systems, Vol. 2, No. 3, pp. 256-275, Inderscience Enterprises Ltd, 2009. ©1
| | 2008 | 11 M. Schmid, D. Ziener and J. Teich.
Netlist-Level IP Protection by Watermarking for LUT-Based FPGAs.
In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2008), pp. 209-216, Taipei, Taiwan, December 08-10, 2008. ©1
| 10 D. Ziener and J. Teich.
Concepts for Autonomous Control Flow Checking for Embedded CPUs.
In Proceedings of the 5th International Conference on Autonomic and Trusted Computing (ATC08), pp. 234-248, Oslo, Norway, June 23-25, 2008. ©1
| 9 D. Ziener and J. Teich.
Power Signature Watermarking of IP Cores for FPGAs .
Journal of Signal Processing Systems, Volume 51, Number 1 / April 2008, pages 123-136, Springer. ©1
| | 2007 | 8 D. Ziener and J. Teich.
Watermarking Apparatus, Software Enabling an Implementation of an Electronic Circuit Comprising a Watermark, Method for Detecting a Watermark and Apparatus for Detecting a Watermark.
US-Patent US2007/0220263, Anmeldetag 19.10.2006 aus EP 1835425, veröffentlicht 20.09.2007, Patentklassen (IPC) H04L 9/00. ©1
| 7 D. Ziener and J. Teich.
Watermarking apparatus, software enabling an implementation of an electronic circuit comprising a watermark, method for detecting a watermark and apparatus for detecting a watermark.
Europäisches Patent EP1835425, Anmeldetag 17.03.2006, veröffentlicht 19.09.2007, Patentklassen (IPC) G06F 17/50; G06F 21/00. ©1
| 6 W. Stechele, O. Bringmann, R. Ernst, A. Herkersdorf, K. Hojenski, P. Janacik, F. Rammig, J. Teich, N. Wehn, J. Zeppenfeld and D. Ziener.
Concepts for Autonomic Integrated Systems.
In Proceedings of edaWorkshop07, Hannover, Germany, June 19-20, 2007. ©1
| 5 W. Stechele, O. Bringmann, R. Ernst, A. Herkersdorf, K. Hojenski, P. Janacik, F. Rammig, J. Teich, N. Wehn, J. Zeppenfeld and D. Ziener.
Autonomic MPSoCs for Reliable Systems.
In Proceedings of Zuverlässigkeit und Entwurf (ZuD 2007), pp. 137-138, Munich, Germany, March 26-28, 2007. ©1
| | 2006 | 4 D. Ziener and J. Teich.
FPGA Core Watermarking Based on Power Signature Analysis.
In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2006), pp. 205-212, Bangkok, Thailand, December 13-15, 2006. ©1
| 3 D. Ziener, S. Aßmus and J. Teich.
Identifying FPGA IP-Cores based on Lookup Table Content Analysis.
In Proceedings of 16th International Conference on Field Programmable Logic and Applications, Madrid, Spain, pp. 481-486, August 28-30, 2006. ©1
| 2 H. Adel, G. Hofmann, R. Wansch and D. Ziener.
A Method for Measuring Time Delay Behavior of Antennas.
First AMTA Europe Symposium, Munich, May 1-4, 2006. ©1
| | 2005 | 1 D. Ziener and J. Teich.
Evaluation of Watermarking methods for FPGA-based IP-cores.
Technical Report 01-2005, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, March 2005. ©1
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