Prof. Dr.-Ing. Jürgen Teich
	Address: Department of Computer Science 12 (Hardware-Software-Co-Design) University of Erlangen-Nuremberg Am Weichselgarten 3 D-91058 Erlangen Germany Phone: +49 9131 85-25150 Fax: +49 9131 85-25149 Email: teich@informatik.uni-erlangen.de

Synthesis and Optimization of Digital Hardware/Software Systems

Recent and future conference organization activities

Publications since 2004

2008

172 H. Dutta, D. Kissler, F. Hannig, A. Kupriyanov, J. Teich and B. Pottier. A Holistic Approach for Tightly Coupled Reconfigurable Parallel Processors. To appear in Journal of Embedded Hardware Design (Microprocessors and Microsystems), 2008.

171 M. Schmid, D. Ziener and J. Teich. Netlist-Level IP Protection by Watermarking for LUT-Based FPGAs. In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2008), Taipei, Taiwan , December 08-10, 2008.

170 F. Reimann, M. Glaß, M. Lukasiewycz, C. Haubelt, J. Keinert and J. Teich. Symbolic Voter Placement for Dependability-Aware System Synthesis. To appear in Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Atlanta, GA USA, October 19-24 2008.

169 J. Teich. Invasive Algorithms and Architectures. it - Information Technology, invited paper, October 2008.

168 M. Glaß, M. Lukasiewycz, F. Reimann, C. Haubelt and J. Teich. Symbolic Reliability Analysis of Self-healing Networked Embedded Systems. To appear in Proceedings of the 27th International Conference on Computer Safety, Reliability and Security (SAFECOMP 2008), Newcastle upon Tyne, UK, September 22-25, 2008.

167 M. Lukasiewycz, M. Glaß and J. Teich. A Feasibility-preserving Crossover and Mutation Operator for Constrained Combinatorial Problems. To appear in Proceedings of the 10th International Conference on Parallel Problem Solving from Nature (PPSN 2008), Dortmund, Germany, September 13-17, 2008.

166 C. Claus, W. Stechele, J. Angermeier and J. Teich. A comparison of embedded reconfigurable A comparison of embedded reconfigurable video-processing architectures. To appear in Proceedings of 18th International Conference on Field Programmable Logic and Applications (FPL 2008), Heidelberg, Germany, September 8 - 10, 2008.

165 C. Wolinski, K. Kuchcinski, J. Teich and F. Hannig. Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures. To appear in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Heidelberg, Germany, September 8-10, 2008.

164 D. Koch, C. Beckhoff and J. Teich. ReCoBus-Builder – a Novel Tool and Technique to Build Statically and Dynamically Reconfigurable Systems for FPGAs. Proceedings of International Conference on Field-Programmable Logic and Applications (FPL 08), Heidelberg, Germany.

163 S. Fekete, J. van der Veen, J. Angermeier, D. Koch and J. Teich. No-Break Dynamic Defragmentation of Reconfigurable Devices. Proceedings of International Conference on Field-Programmable Logic and Applications (FPL 08), Heidelberg, Germany.

162 C. Wolinski, K. Kuchcinski, J. Teich and F. Hannig. Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. To appear in Proceedings of the 11th Euromicro Conference on Digital System Design (DSD), Parma, Italy, September 3-5, 2008.

161 R. Schaffer, R. Merker, F. Hannig and J. Teich. Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. To appear in Proceedings of the 11th Euromicro Conference on Digital System Design (DSD), Parma, Italy, September 3-5, 2008.

160 M. Glaß, M. Lukasiewycz, R. Wanka, C. Haubelt and J. Teich. Multi-Objective Routing and Topology Optimization in Networked Embedded Systems. In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2008), pp. 74-81, Samos, Greece, July 21-24, 2008.

159 D. Ziener and J. Teich. Concepts for Autonomous Control Flow Checking for Embedded CPUs. In Proceedings of the 5th International Conference on Autonomic and Trusted Computing (ATC-08), pp. 234-248, Oslo, Norway, June 23-25, 2008.

158 J. Teich and F. Schäfer. ESL Methodologies for Platform-Based Synthesis. Special Session, 2008 ACM/EDAC/IEEE Design Automation Conference (DAC 2008), Anaheim, USA, June 08-13, 2008.

157 M. Lukasiewycz, M. Glaß, C. Haubelt, J. Teich, R. Regler and B. Lang. Concurrent Topology and Routing Optimization in Automotive Network Integration. In Proceedings of the 2008 ACM/EDAC/IEEE Design Automation Conference (DAC 2008), pp. 626-629, Anaheim, CA, U.S.A., June 08-13, 2008.

156 C. Zebelein, J. Falk, C. Haubelt and J. Teich. Classification of General Data Flow Actors into Known Models of Computation. In Proc. of the Sixth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE\\\'2008), pp. 119-128, Anaheim, CA, USA, June 5-7, 2008.

155 M. Majer, S. Wildermann, J. Angermeier, S. Hanke and J. Teich. Co-Design Architecture and Implementation for Point-Based Rendering on FPGAs. Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping (RSP 2008), Monterey, California, June 2-5, 2008.

154 M. Lukasiewycz, M. Glaß, C. Haubelt and J. Teich. A Feasibility-preserving Local Search Operator for Constrained Discrete Optimization Problems. In Proceedings of the 2008 IEEE Congress on Evolutionary Computation (CEC 2008), pp. 1968-1975, Hong Kong, China, June 01-06, 2008.

153 A. Kupriyanov, F. Hannig, D. Kissler and J. Teich. MAML: An ADL for Designing Single and Multiprocessor Architectures. In Prabhat Mishra and Nikil Dutt (eds.). Chapter 12 in Processor Description Languages, pp. 295-327. In Systems on Silicon Series, Morgan Kaufmann, June 2008.

152 D. Kissler, A. Strawetz, F. Hannig and J. Teich. Power-efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. To appear in Proceedings of the 18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'08), Lisbon, Portugal, September 10-12, 2008.

151 D. Koch, C. Haubelt and J. Teich. Efficient Reconfigurable On-Chip Buses for FPGAs. Proceedings 16th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2008), Palo Alto, California, April 14-15, 2008.

150 J. Angermeier and J. Teich. Heuristics for Scheduling Reconfigurable Devices with Consideration of Reconfiguration Overheads. Proceedings 15th Reconfigurable Architectures Workshop (RAW 2008), Miami, Florida, April 2008.

149 C. Wolinski, K. Kuchcinski, J. Teich and F. Hannig. Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. To appear in Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Palo Alto, CA, USA, April 14-15, 2008.

148 J. Teich. Invasion - A New Parallel Computing and Architecture Paradigm. Dagstuhl Seminar No. 08141, Organic Computing - Controlled Self-organization, IBFI, March 31- April 4, 2008.

147 D. Ziener and J. Teich. Power Signature Watermarking of IP Cores for FPGAs . Journal of Signal Processing Systems, Volume 51, Number 1 / April 2008, pages 123-136, Springer.

146 F. Hannig, H. Ruckdeschel, H. Dutta and J. Teich. PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing (ARC), Lecture Notes in Computer Science (LNCS), Springer, London, United Kingdom, March 26-28, 2008.

145 J. Angermeier, U. Batzer, M. Majer, J. Teich, C. Claus and W. Stechele. Reconfigurable HW/SW Architecture of a Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System. Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing (ARC), Lecture Notes in Computer Science (LNCS), Springer, London, United Kingdom, March 26-28, 2008.

144 J. Teich, F. Hannig, H. Dutta, D. Kissler and M. Hartl. Domain-Specific Reconfigurable MPSoC-Systems - Challenges and Trends. Friday Workshop Reconfigurable Hardware, Design, Automation and Test in Europe (DATE 2008), Munich, Germany, March 14, 2008.

143 H. Dutta, F. Hannig and J. Teich. The PARO Design Tool for Automatic Generation of Hardware Accelerators. Friday Workshop: The New Wave of the High-Level Synthesis, Automation and Test in Europe (DATE), Munich, Germany, March 10-14, 2008.

142 D. Kissler, H. Dutta, A. Kupriyanov, F. Hannig and J. Teich. A High-Speed Dynamic Reconfigurable Multilevel Parallel Architecture. Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), Munich, Germany, March 10-14, 2008.

141 M. Glaß, M. Lukasiewycz, F. Reimann, C. Haubelt and J. Teich. Symbolic Reliability Analysis and Optimization of ECU Networks. Proceedings of Design, Automation and Test in Europe (DATE 2008), IEEE Computer Society, pp. 158-163, Munich, Germany, March 10-14, 2008.

140 M. Streubühr, M. Jäntsch, C. Haubelt, J. Teich and A. Schneider. Semi-Automatic Generation of mixed Hardware-Software Prototypes from Simulink Models. 11. Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen", Freiburg, Germany, pp. 139-148, March 03-05, 2008.

139 F. Hannig, H. Ruckdeschel and J. Teich. The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications. Proceedings of the GIITGGMM-Workshop - Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Freiburg, Germany, March 3-5, 2008.

138 J. Gladigau, F. Blendinger, C. Haubelt and J. Teich. Symbolische Modellprüfung Aktor-orientierter High-level SystemC-Modelle mit Intervalldiagrammen. 11. GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Freiburg, Germany, pp. 109-118, March 03-05, 2008.

137 T. Streichert, C. Haubelt, D. Koch and J. Teich. Concepts for Self-Adaptive and Self-Healing Networked Embedded Systems. Organic Computing, Rolf Würtz (Ed.), Springer Series Understanding Complex Systems, pp. 241-260, Springer, 2008.

136 R. Brendle, T. Streichert, D. Koch, C. Haubelt and J. Teich. Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks. Proceedings of the International Conference on Architecture of Computing Systems (ARCS 2008), pp. 117-129, Dresden, Germany, February 25-28, 2008.

135 T. Streichert, M. Glaß, R. Wanka, C. Haubelt and J. Teich. Topology-Aware Replica Placement in Fault-Tolerant Embedded Networks. Proceedings of the International Conference on Architecture of Computing Systems (ARCS 2008), pp. 23-37, Dresden, Germany, February 25-28, 2008.

134 S. Wildermann and J. Teich. Stereo Person Tracking with a Color-Based Particle Filter. G. Sommer and R. Klette (Eds.): RobVis 2008, LNCS 4931, pp. 327–340, Springer-Verlag Berlin Heidelberg, 2008.

133 F. Hannig, H. Dutta, H. Ruckdeschel and J. Teich. Quantitative Evaluation of Behavioral Synthesis Approaches for Reconfigurable Devices. Proceedings of the 2nd HiPEAC Workshop on Reconfigurable Computing, Gothenburg, Sweden, January 27, 2008.

132 M. Lukasiewycz, M. Glaß, C. Haubelt and J. Teich. Efficient Symbolic Multi–Objective Design Space Exploration. In Proceedings of the 13th Asia and South Pacific Design Automation Conference (ASP-DAC 2008), pp. 691-696, Seoul, Korea.

2007

131 D. Koch, C. Beckhoff and J. Teich. Bitstream Decompression for High Speed FPGA Configuration from Slow Memories. In Proceedings of the IEEE International Conference on Field-Programmable Technology 2007 (ICFPT'07), pp. 161-168.

130 J. Keinert, J. Falk, C. Haubelt and J. Teich. Actor-Oriented Modeling and Simulation of Sliding Window Image Processing Algorithms. Proceedings of the 2007 IEEE/ACM/IFIP Workshop of Embedded Systems for Real-Time Multimedia (ESTIMEDIA 2007), pp. 113-118, Salzburg, Oct. 4-5, 2007.

129 T. Streichert, M. Glaß, C. Haubelt and J. Teich. Design space exploration of reliable networked embedded systems. In Journal on Systems Architecture (JSA). Volume 53(10): 751-763, 2007.

128 M. Lukasiewycz, M. Glaß, C. Haubelt and J. Teich. SAT-Decoding in Evolutionary Algorithms for Discrete Constrained Optimization Problems. In Proceedings of the 2007 IEEE Congress on Evolutionary Computation (CEC 2007), Singapore, Singapore, pp. 935-942, September 25-28, 2007.

127 D. Ziener and J. Teich. Watermarking Apparatus, Software Enabling an Implementation of an Electronic Circuit Comprising a Watermark, Method for Detecting a Watermark and Apparatus for Detecting a Watermark. US-Patent US2007/0220263, Anmeldetag 19.10.2006 aus EP 1835425, veröffentlicht 20.09.2007, Patentklassen (IPC) H04L 9/00.

126 D. Ziener and J. Teich. Watermarking apparatus, software enabling an implementation of an electronic circuit comprising a watermark, method for detecting a watermark and apparatus for detecting a watermark. Europäisches Patent EP1835425, Anmeldetag 17.03.2006, veröffentlicht 19.09.2007, Patentklassen (IPC) G06F 17/50; G06F 21/00.

125 J. Gladigau, C. Haubelt, B. Niemann and J. Teich. Mapping Actor-Oriented Models to TLM Architectures. In Proceedings FDL'07, Forum on Design Languages 2007, Barcelona, Spain, September 18-20, 2007.

124 D. Koch, T. Streichert, C. Haubelt and J. Teich. Efficient Reconfigurable On-Chip Buses. Europäisches Patent EP07017975, Anmeldetag 13.09.2007.

123 S. Fekete, J. van der Veen, A. Ahmadinia, D. Göhringer, M. Majer and J. Teich. Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, accepted, September 2007.

122 J. Teich. Reconfigurable Computing Systems. it - Information Technology, http://it-information-technology.de, Oldenbourg Wissenschaftsverlag, vol. 49(3):139-142, 2007.

121 B. Niemann, C. Haubelt, M. Uribe and J. Teich. Formalizing TLM with Communicating State Machines. In Advances in Design and Specification Languages for Embedded Systems, pp. 225-242, Springer, 2007.

120 J. Keinert, C. Haubelt and J. Teich. Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow. In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, Acoustics, Speech, and Signal Processing (IC-SAMOS VII), Samos (Greece) July 16-19, 2007.

119 H. Dutta, F. Hannig, A. Kupriyanov, D. Kissler, J. Teich, R. Schaffer, S. Siegel, R. Merker and B. Pottier. Massively Parallel Processor Architectures: A Co-design Approach. Proceedings of the 3rd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC), pp. 61-68, Montpellier, France, June 18-20, 2007.

118 J. Teich, F. Hannig, H. Ruckdeschel, H. Dutta, D. Kissler and A. Stravet. A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Invited paper, pp. 14-24, Las Vegas, NV, USA, June 25-28, 2007.

117 W. Stechele, O. Bringmann, R. Ernst, A. Herkersdorf, K. Hojenski, P. Janacik, F. Rammig, J. Teich, N. Wehn, J. Zeppenfeld and D. Ziener. Concepts for Autonomic Integrated Systems. In Proceedings of edaWorkshop07, Hannover, Germany, June 19-20, 2007.

116 H. Dutta, F. Hannig, H. Ruckdeschel and J. Teich. Efficient Control Generation for Mapping Nested Loop Programs onto Processor Arrays. In Journal of Systems Architecture, 53(5-6):300-309, 2007.

115 M. Lukasiewycz, M. Glaß, C. Haubelt and J. Teich. Solving Multiobjective Pseudo-Boolean Problems. In Proceedings of Tenth International Conference on Theory and Applications of Satisfiability Testing (SAT 2007), Lisbon, Portugal, pp. 56-69, May 28-31, 2007.

114 D. Koch, C. Haubelt, T. Streichert and J. Teich. Modeling and Synthesis of Hardware-Software Morphing. In Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), pp. 2746-2749, New Orleans, LA, U.S.A., May 2007.

113 D. Kissler, F. Hannig and J. Teich. Schwach-programmiert macht stark. Design&Elektronik, April 2007, pp. 34-39, WEKA Fachzeitschriften-Verlag GmbH.

112 A. Kupriyanov, D. Kissler, F. Hannig and J. Teich. Efficient Event-driven Simulation of Parallel Processor Architectures. In Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems (SCOPES), Nice, France, pp. 71-80, April 20, 2007.

111 M. Glaß, M. Lukasiewycz, T. Streichert, C. Haubelt and J. Teich. Reliability-Aware System Synthesis. In Proceedings of Design, Automation and Test in Europe (DATE 2007), IEEE Computer Society, Nice, France, pp. 409-414, April 16-20, 2007.

110 T. Streichert, C. Strengert, D. Koch, C. Haubelt and J. Teich. Communication Aware Optimization of the Task Binding in Hardware/Software Reconfigurable Networks. Journal on Integrated Circuits and Systems, Volume 2, Number 1, pp. 29-36, March 2007.

109 W. Stechele, O. Bringmann, R. Ernst, A. Herkersdorf, K. Hojenski, P. Janacik, F. Rammig, J. Teich, N. Wehn, J. Zeppenfeld and D. Ziener. Autonomic MPSoCs for Reliable Systems. In Proceedings of Zuverlässigkeit und Entwurf (ZuD 2007), pp. 137-138, Munich, Germany, March 26-28, 2007.

108 M. Glaß, M. Lukasiewycz, T. Streichert, C. Haubelt and J. Teich. Synthese zuverlässiger und flexibler Systeme. In Proceedings of Zuverlässigkeit und Entwurf (ZuD 2007), Munich, Germany, pp. 141-148, March 26-28, 2007.

107 S. Fekete, J. van der Veen, J. Angermeier, D. Göhringer, M. Majer and J. Teich. Scheduling and communication-aware mapping of HW-SW modules for dynamically and partially reconfigurable SoC architectures. In Proceedings of the Dynamically Reconfigurable Systems Workshop (DRS 2007), Zürich, Switzerland, pages 151-160, March 15, 2007.

106 J. Angermeier, D. Göhringer, M. Majer and J. Teich. The Erlangen Slot Machine: A flexible FPGA-platform for partially reconfigurable applications at run-time. Tutorial, 20th International Conference on Architecture of Computing Systems (ARCS 2007), Springer LNCS series, Swiss Federal Institute of Technology (ETH) Zurich, Switzerland, March 12-15, 2007.

105 A. Kupriyanov, F. Hannig, D. Kissler, J. Teich, J. Lallet, O. Sentieys and S. Pillement. Modeling of Interconnection Networks in Massively Parallel Processor Architectures. In Proceedings of the 20th International Conference on Architecture of Computing Systems (ARCS 2007), Springer LNCS series, Swiss Federal Institute of Technology (ETH), Zurich, Switzerland, pp. 268-282, March 12-15, 2007.

104 M. Lukasiewycz, M. Glaß, C. Haubelt and J. Teich. Symbolic Archive Representation for a Fast Nondominance Test. In Proceedings of the Fourth International Conference on Evolutionary Multi-Criterion Optimization (EMO 2007), Sendai, Japan, pp. 111-125, March 5-8, 2007.

103 M. Streubühr, C. Riedel, C. Haubelt and J. Teich. System Level Modeling and Performance Simulation for Dynamic Reconfigurable Computing Systems in SystemC. 10. Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen", Erlangen, Germany, pp. 59-68, March 05-07, 2007.

102 J. Teich and C. Haubelt. Digitale Hardware/Software-Systeme: Synthese und Optimierung. 2. Auflage, Springer-Verlag, Berlin Heidelberg, 2007.

101 C. Haubelt, J. Falk, J. Keinert, T. Schlichter, M. Streubühr, A. Deyhle, A. Hadert and J. Teich. A SystemC-based Design Methodology for Digital Signal Processing Systems. In EURASIP Journal on Embedded Systems, Special Issue on Embedded Digital Signal Processing Systems, Volume 2007 (2007), Article ID 47580, 22 pages, March 2007.

100 M. Majer, J. Teich, A. Ahmadinia and C. Bobda. The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-Based Computer. Journal of VLSI Signal Processing Systems, Springer, vol. 47(1), pages 15-31, March 2007.

99 C. Haubelt and J. Teich. Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen. Shaker Verlag, Aachen, Germany, 2007.

98 D. Koch, C. Haubelt and J. Teich. Efficient Hardware Checkpointing -- Concepts, Overhead Analysis, and Implementation. In Proceedings of the 15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2007), Monterey, CA, pp. 188-196, February 18-20, 2007. Download demo video.

97 N. Bergmann, M. Platzner and J. Teich. Dynamically Reconfigurable Architectures. EURASIP Journal of Embedded Systems, Volume 2007 (2007), Article ID 28405, 2 pages, February 2007.

96 J. Teich. Evaluation and Optimization of Reliability of Embedded Systems during Design Space Exploration. Dagstuhl Seminar No. 07101, Quantitative Aspects of Embedded Systems, IBFI, March 5-9, 2007.

95 A. Ahmadinia, C. Bobda, S. Fekete, J. Teich and J. van der Veen. Optimal free-space management and routing-conscious dynamic placement for reconfigurable computing. IEEE Transactions on Computers, volume 56, number 3, pages 673-680, 2007.

94 J. Angermeier, D. Göhringer, M. Majer, J. Teich, S. Fekete and J. van der Veen. The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Reconfigurable Computing. it - Information Technology, http://it-information-technology.de, Oldenbourg Wissenschaftsverlag, vol. 49(3):143-148, 2007.

2006

93 D. Kissler, F. Hannig, A. Kupriyanov and J. Teich. A Highly Parameterizable Parallel Processor Array Architecture. In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT 2006), pp. 105-112, Bangkok, Thailand, December 13-15, 2006.

92 D. Ziener and J. Teich. FPGA Core Watermarking Based on Power Signature Analysis. In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2006), pp. 205-212, Bangkok, Thailand, December 13-15, 2006.

91 J. Falk, J. Gladigau, C. Haubelt and J. Teich. SysteMoC - Verification and Refinement of Actor-Based Models of Computation. Talk, ARTIST2 Workshop on MoCC - Models of Computation and Communication, November 16-17, Zurich, Switzerland, 2006.

90 D. Kissler, F. Hannig, A. Kupriyanov and J. Teich. Hardware Cost Analysis for Weakly Programmable Processor Arrays. In Proceedings of the International Symposium on System-on-Chip (SoC), pp. 179-182, Tampere, Finland, November 14-16, 2006.

89 S. Siegel, R. Merker, F. Hannig and J. Teich. Communication-conscious Mapping of Regular Nested Loop Programs onto Massively Parallel Processor Arrays. In Proceedings of the 18th International Conference on Parallel and Distributed Computing and Systems (PDCS), pp. 71-76, Dallas, TX, USA, November 13-15, 2006.

88 J. Teich. Are Current ESL Tools Meeting the Requirements of Advanced Embedded Systems?. In Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), p. 166, Seoul, Korea, October 22-25, 2006.

87 T. Streichert, D. Koch, C. Haubelt and J. Teich. Modeling and Design of Fault-Tolerant and Self-Adaptive Reconfigurable Networked Embedded Systems. EURASIP Journal on Embedded Systems, Volume 2006 (2006), Article ID 42168, 15 pages, Hindawi Publishing Corporation.

86 J. Falk, C. Haubelt and J. Teich. Efficient Representation and Simulation of Model-Based Designs in SystemC. In Proceedings FDL'06, Forum on Design Languages 2006, Darmstadt, Germany, September 19-22, pp. 129 - 134, 2006.

85 H. Dutta, F. Hannig and J. Teich. Hierarchical Partitioning for Piecewise Linear Algorithms. In Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering (PARELEC), pp. 153-159, Bialystok, Poland, September 13-17, 2006.

84 H. Dutta, F. Hannig, J. Teich, B. Heigl and H. Hornegger. A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. In Proceedings of IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 331-337, Steamboat Springs, CO, USA, September 11-13, 2006.

83 D. Ziener, S. Aßmus and J. Teich. Identifying FPGA IP-Cores based on Lookup Table Content Analysis. In Proceedings of 16th International Conference on Field Programmable Logic and Applications, Madrid, Spain, pp. 481-486, August 28-30, 2006.

82 J. Teich, S. Kaxiras, T. Plaks and K. Flautner. Topic 18: Embedded Parallel Systems. In Proceedings of12th International Euro-Par Conference, p. 1179, Dresden, Germany, August 28-September 1, 2006.

81 S. Fekete, J. van der Veen, M. Majer and J. Teich. Minimizing communication cost for reconfigurable slot modules. In Proceedings 16th International Conference on Field-Programmable Logic and Applications (FPL 2006), pp. 535-540, Madrid, Spain, August 28-30, 2006.

80 T. Streichert, C. Strengert, C. Haubelt and J. Teich. Dynamic Task Binding for Hardware/Software Reconfigurable Networks . In Proceedings of SBCCI 2006, pages 38-43, Ouro Preto, Brasil, August 28th - September 1st, 2006.

79 A. Kupriyanov, F. Hannig, D. Kissler, J. Teich, J. Lallet, O. Sentieys and S. Pillement. Modeling of Interconnection Networks in Massively Parallel Processor Architectures. Technical Report 05-2006, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, August 2006.

78 S. Fekete, E. Köhler and J. Teich. Higher-dimensional packing with order constraints. SIAM Journal on Discrete Mathematics,Vol. 20, No. 4, pp. 1056-1078, 2006.

77 T. Streichert, C. Haubelt and J. Teich. Multi-Objective Topology Optimization for Networked Embedded Systems. In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2006), pp. 93--98, Samos (Greece), July 17-20, 2006..

76 D. Kissler, F. Hannig, A. Kupriyanov and J. Teich. A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. In Proceedings of the 2nd International Workshop on Reconfigurable Communication-Centric System-on-Chips (ReCoSoC), pp. 31-37, France, July 3-5, 2006.

75 D. Göhringer, M. Majer and J. Teich. Bridging the Gap between Relocation and Available Technology: The Erlangen Slot Machine. In Proceedings of the Dagstuhl Seminar Nº 06141 on Dynamically Reconfigurable Architectures, P. M. Athanas, J. Becker, G. Brebner, J. Teich (Eds.), ISSN 1862 - 4405, Dagstuhl, Germany, April 02-07, 2006.

74 D. Koch, M. Körber and J. Teich. Searching RC5-Keys with Distributed Reconfigurable Computing. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA 2006), Las Vegas, USA, June 26-29, 2006.

73 D. Kissler, A. Kupriyanov, F. Hannig, D. Koch and J. Teich. A Generic Framework for Rapid Prototyping of System-on-Chip Designs. In Proceedings of the International Conference on Computer Design (CDES), pp. 189-195, Las Vegas, NV, USA, June 2006.

72 F. Hannig, H. Dutta and J. Teich. Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays: Architectural Parameters and Methodology. In International Journal of Embedded Systems, Vol. 2, Nos. 1/2, pp. 114-127, 2006.

71 C. Haubelt, T. Schlichter and J. Teich. Improving Automatic Design Space Exploration by Integrating Symbolic Techniques into Multi-Objective Evolutionary Algorithms. In International Journal of Computational Intelligence Research (IJCIR), Special Issue on Multiobjective Optimization and Applications, Volume 2, Issue 3. pp. 239-254, 2006.

70 A. Ahmadinia, C. Bobda and J. Teich. Online Placement for Dynamically Reconfigurable Devices. Int. J. Embedded Systems, Vol. 1, Nos. 3/4, pp.165-178, 2006.

69 J. Keinert, C. Haubelt and J. Teich. Modeling and Analysis of Windowed Synchronous Algorithms. In Proceedings of the 31st International Conference on Acoustics, Speech, and Signal Processing (ICASSP2006), Toulouse (France) May 14-19, 2006.

68 H. Dutta, F. Hannig and J. Teich. A Formal Methodology for Hierarchical Partitioning of Piecewise Linear Algorithms. Technical Report 04-2006, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, April 2006.

67 J. Becker, J. Teich, P. Athanas and G. Brebner. Dynamically Reconfigurable Architectures. Proceedings of the Dagstuhl Seminar Nº 06141, ISSN 1862 - 4405, Dagstuhl, Germany, April 02-07, 2006.

66 A. Kupriyanov, F. Hannig, D. Kissler, R. Schaffer and J. Teich. MAML - An Architecture Description Language for Modeling and Simulation of Processor Array Architectures, Part I. Technical Report 03-2006, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, March 2006.

65 D. Koch, T. Streichert, S. Dittrich, C. Strengert, C. Haubelt and J. Teich. An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks. In Proceedings of the 19th International Conference on Architecture of Computing Systems (ARCS 2006), Frankfurt/Main, Germany, pp. 202-216, March 13-16, 2006.

64 H. Dutta, F. Hannig and J. Teich. Controller Synthesis for Mapping Partitioned Programs on Array Architectures. In Proceedings of the 19th International Conference on Architecture of Computing Systems (ARCS), Frankfurt/Main, Germany, pp. 176-191, March 13-16, 2006.

63 J. Teich, C. Haubelt, D. Koch and T. Streichert. Concepts for Self-Adaptive Automotive Control Architectures. DATE'06 Friday Workshop Future Trends in Automotive Electronics and Tool Integration, Conference Design Automation and Test in Europe, March 10, 2006, Munich, Germany.

62 C. Bobda, M. Platzner and J. Teich. The Renaissance of FPGA-Based High-Performance Computing. DATE'06 Friday Workshop, Conference Design Automation and Test in Europe, March 10, 2006, Munich, Germany.

61 M. Streubühr, J. Falk, C. Haubelt, J. Teich, R. Dorsch and T. Schlipf. Task-Accurate Performance Modeling in SystemC for Real-Time Multi-Processor Architectures. In Proceedings of Design, Automation and Test in Europe (DATE 2006), IEEE Computer Society, Munich, Germany, pp. 480-481, March 6-10, 2006.

60 T. Schlichter, M. Lukasiewycz, C. Haubelt and J. Teich. Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms. In Proceedings of IEEE Computer Society Annual Symposium on VLSI. Karlsruhe, Germany, pp. 309-314, March 2-3, 2006.

59 A. Kupriyanov, F. Hannig, D. Kissler, J. Teich, R. Schaffer and R. Merker. An Architecture Description Language for Massively Parallel Processor Architectures. In Proceedings of the 9th ITG/GMM/GI Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Dresden, Germany, pp. 11-20, February 20-22, 2006.

58 H. Dutta, F. Hannig and J. Teich. Mapping of Nested Loop Programs onto Massively Parallel Processor Arrays with Memory and I/O Constraints. In Friedhelm Meyer auf der Heide and Burkhard Monien, editors, Proceedings of the 6th International Heinz Nixdorf Symposium, New Trends in Parallel & Distributed Computing, volume 181 of HNI-Verlagsschriftenreihe, pp. 97-119, Paderborn, Germany, January 17-18, 2006.

57 J. Teich. Timing Analysis of Systems of Communicating Tasks with Internal State. Technical Report 01-2006, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, January 2006.

56 J. Teich. Stochastic Timing Analysis of Communicating Tasks with Internal State. Technical Report 02-2006, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, January 2006.

2005

55 J. Falk, C. Haubelt and J. Teich. Syntax and execution behavior of SysteMoC. Technical Report 04-2005, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, December 2005.

54 A. Ahmadinia, C. Bobda, T. Haller, A. Linarth, M. Majer and J. Teich. Increasing the Flexibility in FPGA-Based Reconfigurable Platforms: The Erlangen Slot Machine. In Proc. IEEE 2005 Conference on Field-Programmable Technology (FPT), Singapore, Singapore, pages 37-42, December 11-14, 2005.

53 H. Dutta, F. Hannig and J. Teich. Control Path Generation for Mapping Partitioned Dataflow-dominant Algorithms onto Array Architectures. Technical Report 03-2005, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, November 2005.

52 J. Keinert, C. Haubelt and J. Teich. Windowed Synchronous Data Flow. Department of Computer Science 12, Hardware-Software-Co-Design, University of Erlangen-Nuremberg, Am Weichselgarten 3, D-91058 Erlangen, Germany Co-Design-Report 02-2005.

51 A. Ahmadinia, C. Bobda, J. Ding, M. Majer and J. Teich. Modular Video Streaming on a Reconfigurable Platform. In Proc. IFIP VLSI SOC 2005, pages 103-108, Perth, Australia, pp. 103-108, October 17-19, 2005.

50 C. Haubelt, M. Jersak, K. Richter, K. Strehl, D. Ziegenbein, R. Ernst, J. Teich and L. Thiele. SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme. In Proceedings of INFORMATIK 2005 - Informatik LIVE. by Armin B. Cremers, Rainer Manthey, Peter Martini, and Volker Steinhage (Eds.). In Lecture Notes in Informatics. VOL. P-68, No. 2, Bonn, Germany, pp. 693-697, September 19-22, 2005. © Gesellschaft für Informatik, Bonn, Germany, 2005.

49 S. Helwig, C. Haubelt and J. Teich. Modeling and Analysis of Indirect Communication in Particle Swarm Optimization. In Proceedings of the 2005 IEEE Congress on Evolutionary Computation, volume 2, pages 1246-1253, Edinburgh, UK, September 2nd-5th, 2005.

48 A. Ahmadinia, C. Bobda, S. Fekete, M. Majer, J. Teich and J. van der Veen. DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL),Tampere, Finland, pp. 153-158, August 24-26, 2005.

47 T. Schlichter, C. Haubelt, F. Hannig and J. Teich. Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems. In Proceedings of Application-specific Systems, Architectures and Processors (ASAP). Samos, Greece, pp. 9-14, July 23-25, 2005.

46 H. Ruckdeschel, H. Dutta, F. Hannig and J. Teich. Automatic FIR Filter Generation for FPGAs. In Proceedings of the International Workshop on Embedded Computer Systems, Architectures, Modeling, and Simulation (SAMOS), Samos, Greece, pp. 51-61, July 18-20, 2005.

45 F. Hannig and J. Teich. Output Serialization for FPGA-based and Coarse-grained Processor Arrays. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, USA, pp. 78-84, June 27-30, 2005.

44 F. Hannig, H. Dutta, A. Kupriyanov, J. Teich, R. Schaffer, S. Siegel, R. Merker, R. Keryell, B. Pottier and D. Chillet, D. Ménard, O. Sentieys. Co-Design of Massively Parallel Embedded Processor Architectures. In Proceedings of the first ReCoSoC Workshop. Montpellier, France, June 27-29, 2005.

43 A. Ahmadinia, C. Bobda, S. Fekete, F. Hannig, M. Majer, J. Teich and J. van der Veen. Defragmenting the Module Layout of a Partially Reconfigurable Device. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, USA, pp. 92-101, June 27-30, 2005.

42 T. Schlichter, C. Haubelt and J. Teich. Improving EA-based Design Space Exploration by Utilizing Symbolic Feasibility Tests. In Proceedings of Genetic and Evolutionary Computation Conference (GECCO). Washington, DC, pp. 1945-1952, June 25-29, 2005.

41 A. Ahmadinia, C. Bobda, J. Ding, S. Fekete, M. Majer, J. Teich and J. van der Veen. A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices. In Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping, Montreal, Canada, pp. 84-90, June 8-10, 2005.

40 S. Mostaghim and J. Teich. Quad-trees: A Data structure for storing Pareto-sets in Multi-objective Evolutionary Algorithms with Elitism. In Ajith Abraham and Lakhmi Jain and Robert Goldberg (eds.), Evolutionary Multiobjective Optimization, Theoretical Advances and Applications. Springer Advanced Information and Knowledge Processing Series, London, pp. 81-104, 2005.

39 A. Ahmadinia, C. Bobda, S. Fekete, T. Haller, A. Linarth, M. Majer, J. Teich and J. van der Veen. The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform. In Proceedings of the 2005 IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, USA, pp. 319-320, April 17-20, 2005.

38 T. Dinkel, C. Haubelt, U. Heinkel, J. Knäblein, T. Schlichter, S. Schock and J. Teich. Comparison of Techniques for the Automatic Verification of ADeVA Specifications. In Dresdener Arbeitstagung Schaltungs- und Systementwurf (DASS 2005). Dresden, Germany, April 13-14, 2005.

37 T. Dinkel, C. Haubelt, U. Heinkel, T. Schlichter and J. Teich. Automatische Verification von ADeVA-Spezifikationen. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen. GI/ITG/GMM-Workshop 2005, Munich, Germany, April 06-07, 2005.

36 J. Falk, C. Haubelt and J. Teich. Representing Models of Computation in SystemC. GI/ITG/GMM-Workshop 2005, Munich, Germany, April 06-07, 2005.

35 A. Ahmadinia, C. Bobda, M. Majer and J. Teich. Packet Routing in Dynamically Changing Networks on Chip. In Proceedings of the 12th Reconfigurable Architectures Workshop (RAW 2005), Denver, USA, p. 154b, IEEE Computer Society, April 4-5, 2005.

34 J. Teich. Model-Based System-Level Design Using SystemC. Invited talk, Akademische Tage'05, IBM Forschungslaboratorium, March 18, 2005, Böblingen, Germany.

33 J. Teich. The Future of Reconfigurable Computing. DATE'05 Friday Workshop, Conference Design Automation and Test in Europe, March 11, 2005, Munich, Germany.

32 A. Ahmadinia, C. Bobda, T. Haller, A. Linarth, M. Majer and J. Teich. The Erlangen Slot Machine (ESM): A Flexible Platform for Dynamic Reconfigurable Computing. Board Demo at the University Booth at Design, Automation and Test in Europe (DATE 2005), Munich, Germany, March 7-11, 2005.

31 C. Haubelt, J. Gamenik and J. Teich. Initial Population Construction for Convergence Improvement of MOEAs. In Evolutionary Multi-Criterion Optimization, Carlos A. Coello Coello, Arturo Hernández Aguirre, and Eckart Zitzler (eds.), Lecture Notes in Computer Science, Vol. 3410, pp. 191-205, Springer, Berlin, Heidelberg, New York, 2005.

30 T. Streichert, C. Haubelt and J. Teich. Distributed HW/SW-Partitioning for Embedded Reconfigurable Systems. In Proceedings of DATE 2005, Munich, Germany, pp. 894-895, March 7-11, 2005.

29 D. Ziener and J. Teich. Evaluation of Watermarking methods for FPGA-based IP-cores. Technical Report 01-2005, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, March 2005.

28 T. Streichert, C. Haubelt and J. Teich. Verteilte HW/SW-Partitionierung für fehlertolerante rekonfigurierbare Netzwerke. In Proceedings of 17. ITG/GI/GMM Workshop für Testmethoden und Zuverlässigkeit und Fehlertoleranz von Schaltungen und Systemen. Innsbruck, Austria, pp. 50-54, February 27 - March 1, 2005.

27 C. Haubelt, S. Otto, C. Grabbe and J. Teich. A System-Level Approach to Hardware Reconfigurable Systems. In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC'05). Shanghai, China, pp. 298-301, January 18-21, 2005.

26 T. Streichert, C. Haubelt and J. Teich. Online Hardware/Software Partitioning in Networked Embedded Systems. In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC'05). Shanghai, China, pp. 982-985, January 18-21, 2005.

2004

25 A. Ahmadinia, C. Bobda, H. Kalte, D. Koch and J. Teich. FPGA Architecture Extensions for Preemptive Multitasking and Hardware Defragmentation. In Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology (FPT), Brisbane, Australia, pp. 433-436, December 6-8, 2004.

24 A. Ahmadinia, C. Bobda, J. Ding and J. Teich. Design and Implementation of Reconfigurable Multiple Bus on Chip (RMBoC). Technical Report 02-2004, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, November 2004.

23 S. Mostaghim and J. Teich. Multi-Objective Particle Swarm Optimization. Dagstuhl Seminar No. 04461, Practical Approaches to Multi-Objective Optimization, IBFI, November 7 - 12, 2004.

22 F. Hannig and J. Teich. Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. In Proceedings of the 15th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2004), pp. 17-27, Galveston, TX, USA, September 27-29, 2004.

21 A. Kupriyanov, F. Hannig and J. Teich. Automatic and Optimized Generation of Compiled High-Speed RTL Simulators. In Proceedings of the Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES 2004). Washington, DC, U.S.A., September 22, 2004.

20 F. Hannig and J. Teich. Dynamic Piecewise Linear/Regular Algorithms. In Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), pp. 79-84, Dresden, Germany, September 7-10, 2004.

19 A. Ahmadinia, C. Bobda, D. Koch, M. Majer and J. Teich. Task Scheduling for Heterogeneous Reconfigurable Computers. In Proceedings of the 17th Symposium on Integrated Circuits and Systems Design (SBCCI), Pernambuco, Brazil, pp. 22-27, ACM Press, September 7-11, 2004.

18 A. Ahmadinia, C. Bobda, D. Koch, M. Majer and J. Teich. A Dynamic NoC Approach for Communication in Reconfigurable Devices. In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL), Antwerp, Belgium, LNCS 3203, pp. 1032-1036, Springer, August 30 - September 1, 2004.

17 A. Ahmadinia, C. Bobda, S. Fekete, J. Teich and J. van der Veen. Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices. In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL), Antwerp, Belgium, LNCS 3203, pp. 847-851, Springer, August 30 - September 01, 2004.

16 C. Haubelt, D. Koch and J. Teich. Basic OS Support for Distributed Reconfigurable Hardware. In Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04), Samos, Greece, July 19-21, published as Springer Lecture Notes in Computer Science (LNCS), volume 3133, pages 30-38, 2004.

15 N. Bambha, S. Bhattacharyya, J. Teich and E. Zitzler. Systematic Integration of Parameterized Local Search Into Evolutionary Algorithms. IEEE Transactions on Evolutionary Computation, vol. 8, no. 2, pages 137-155, April 2004.

14 A. Kupriyanov, F. Hannig and J. Teich. High-Speed Event-Driven RTL Compiled Simulation. In Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04), Samos, Greece, July 19-21, published as Springer Lecture Notes in Computer Science (LNCS), volume 3133, pages 519-529, 2004.

13 S. Bhattacharyya and J. Teich. Analysis of Dataflow Programs with Interval-Limited Data-Rates. In Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04), Samos, Greece, July 19-21, published as Springer Lecture Notes in Computer Science (LNCS), volume 3133, pages 507-518, 2004.

12 N. Bambha, S. Bhattacharyya, J. Teich and E. Zitzler. Systematic Integration of Parameterized Local Search Techniques in Evolutionary Algorithms. In Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '04), Part II, pp. 383-384, Seattle, U.S.A., June 26-30, 2004.

11 S. Mostaghim and J. Teich. Covering Pareto-optimal Fronts by Subswarms in Multi-objective Particle Swarm Optimization. In Proceedings of the Congress on Evolutionary Computation (CEC '04), pp. 1404-1411, Portland, U.S.A., June 20-23, 2004.

10 T. Frauenheim, M. Hoffman, P. Koenig, S. Mostaghim and J. Teich. Molecular Force Field Parameterization using Multi-Objective Evolutionary Algorithms. In Proceedings of the Congress on Evolutionary Computation (CEC '04), pp. 212-219, Portland, U.S.A., June 20-23, 2004.

9 F. Hannig and J. Teich. Resource Constrained and Speculative Scheduling of Dynamic Piecewise Regular Algorithms. Technical Report 01-2004, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, June 2004.

8 F. Hannig, H. Dutta and J. Teich. Regular Mapping for Coarse-grained Reconfigurable Architectures. In Proceedings of the 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2004), Vol. V, pp. 57-60, Montréal, Quebec, Canada, May 17-21, 2004.

7 F. Hannig, H. Dutta and J. Teich. Mapping of Regular Nested Loop Programs to Coarse-grained Reconfigurable Arrays -- Constraints and Methodology. In Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), Santa Fe, NM, USA, April 26-30, 2004.

6 A. Ahmadinia, M. Bednara, C. Bobda and J. Teich. A New Approach for On-line Placement on Reconfigurable Devices. In Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), Santa Fe, NM, U.S.A., April 26-30, 2004.

5 C. Haubelt and J. Teich. Modeling and Analysis of Distributed Reconfigurable Hardware. In Dresdener Arbeitstagung Schaltungs- und Systementwurf (DASS 2004), pp. 106-111, Dresden, Germany, April 19-20, 2004.

4 D. Koch and J. Teich. Platform-Independent Methodology for Partial Reconfiguration. Proceedings of the 2004 ACM conference Computing Frontiers (CF 04), pp. 398-403, April 14-16, 2004, Ischia, Italy.

3 A. Ahmadinia, C. Bobda, K. Danne and J. Teich. Generation of Distributed Arithmetic Designs for Reconfigurable Applications. In Proc. GI/ITG Dynamically Reconfigurable Systems Workshop at ARCS - Organic and Pervasive Computing, Augsburg, Germany, pp. 205-214, March 26, 2004.

2 A. Ahmadinia, C. Bobda and J. Teich. A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware. In Proc. 17th International Conference on Architecture of Computing Systems (ARCS 2004), Augsburg, Germany, LNCS 2981, pp. 125-139, Springer, March 23-26, 2004.

1 F. Hannig and J. Teich. Energy Estimation and Optimization for Piecewise Regular Processor Arrays. In Shuvra S. Bhattacharyya, Ed F. Deprettere and Jürgen Teich (eds.). Chapter 6 in Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation, pages 107-126. Number 20 in Signal Processing and Communication Series, Marcel Dekker, New York, U.S.A., 2004.