Prof. Dr.-Ing. Jürgen Teich
	Address: Department of Computer Science 12 (Hardware-Software-Co-Design) University of Erlangen-Nuremberg Cauerstr. 11 D-91058 Erlangen Germany Phone: +49 9131 85-25150 Fax: +49 9131 85-25149 Email: teich@informatik.uni-erlangen.de

Recent text books

Synthesis and Optimization of Digital Hardware/Software Systems

Specification and Verification of Digital Hardware/Software Systems

Recent and future conference organization activities

Publications

2012

458 M. Eberl, M. Glaß, J. Teich and U. Abelein. Considering Diagnosis Functionality during Automatic System-Level Design of Automotive Networks. To appear in Proceedings of the 49th Design Automation Conference (DAC 2012), San Francisco, USA, Jun. 3-7, 2012. ©1

457 J. Teich. Hardware/Software Co-Design: Past, Present, and Predicting the Future. To appear in Proceedings of the IEEE, vol. 100, no. 5, May 2012. Invited paper. [DOI: 10.1109/JPROC.2011.2182009]. ©1

456 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert. Generating Device-specific GPU Code for Local Operators in Medical Imaging. To appear in Proceedings of the 26th IEEE International Parallel & Distributed Processing Symposium (IPDPS), Shanghai, China, May 21-25, 2012. ©3

455 S. Graf, T. Russ, M. Glaß and J. Teich. Considering MOST150 during Virtual Prototyping of Automotive E/E Architectures. To appear in Proceedings of Automotive meets Electronics (AmE 2012), Dortmund, Germany, April 17-18, 2012. ©1

454 Y. Xu, B. Li, R. Hasholzner, B. Rohfleisch, C. Haubelt and J. Teich. Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis. To appear in Proceedings of the Design, Automation and Test in Europe Conference (DATE), March 2012. ©1

453 P. Milbredt, M. Glaß, M. Lukasiewycz, A. Steininger and J. Teich. Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach. To appear in Proceedings of Design, Automation and Test in Europe (DATE 2012), Dresden, Germany, March 12-16, 2012. ©1

452 L. Zhang, M. Glaß, M. Streubühr, J. Teich, A. v. Schwerin and K. Liu. Actor-oriented Modeling and Simulation of Cut-through Communication in Network Controllers. To appear in Proceedings of Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2012), Kaiserslautern, Germany, March 05-07, 2012. ©1

451 S. Graf, M. Glaß and J. Teich. Unreliable Data Transmissions and Limited Hardware Communication Buffers in Automotive E/E Virtual Prototypes. To appear in Proceedings of Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2012), Kaiserslautern, Germany, March 05-07, 2012. ©1

450 Y. Xu, R. Rosales, B. Wang, M. Streubühr, R. Hasholzner, C. Haubelt and J. Teich. A Very Fast and Quasi-Accurate Power-State-Based System-Level Power Modeling Methodology. To appear In Proceedings of the International Conference on Architecture of Computing Systems (ARCS), Munich, Germany, March 2012. ©1

449 L. Zhang, M. Streubühr, M. Glaß and J. Teich. System-Level Modeling and Simulation of Networked PROFINET IO Controllers. To appear in Proceedings of the Embedded World Conference, Nuremberg, Germany, February 28 - March 01, 2012. ©1

448 D. Koch, J. Torresen, C. Beckhoff, D. Ziener, C. Dennl, V. Breuer, J. Teich, M. Feilen and W. Stechele. Partial Reconfiguration on FPGAs in Practice - Tools and Applications. To appear in Tutorial Proceedings of the 2012 Architecture of Computing Systems (ARCS'12), Munich, Germany. February 28-29, 2012. ©1

447 R. Membarth, J. Lupp, F. Hannig, J. Teich, M. Körner and W. Eckert. Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging. To appear in Proceedings of the 24th International Conference on Architecture of Computing Systems (ARCS), Munich, Germany, February 28 - March 02, 2012. ©1

446 S. Wildermann, J. Angermeier, E. Sibirko and J. Teich. Placing Multi-mode Streaming Applications on Dynamically Partially Reconfigurable Architectures. International Journal of Reconfigurable Computing. Volume 2012 (2012), Article ID 608312, 12 pages. [doi:10.1155/2012/608312] . ©1

445 S. Roloff, F. Hannig and J. Teich. Approximate Time Functional Simulation of Resource-Aware Programming Concepts for Heterogeneous MPSoCs. Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 187-192, Sydney, Australia, January 30-February 2, 2012. ©1

444 S. Fekete, T. Kamphans, N. Schweer, C. Tessars, J. van der Veen, J. Angermeier, D. Koch and J. Teich. Dynamic Defragmentation of Reconfigurable Devices. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2012. ©1

2011

443 S. Wildermann, F. Reimann, J. Teich and Z. Salcic. Operational Mode Exploration for Reconfigurable Systems with Multiple Applications. Proceedings of the International Conference on Field-Programmable Technology (FPT'11), New Delhi, India. Dec. 12-14, 2011. ©1

442 T. Ziermann, B. Schmidt, M. Mühlenthaler, D. Ziener, J. Angermeier and J. Teich. An FPGA Implementation of a Threat-based Strategy for Connect6. Proceedings of the International Conference on Field-Programmable Technology (FPT'11), New Delhi, India. Dec. 12-14, 2011. ©1

441 J. Angermeier, D. Ziener, M. Glaß and J. Teich. Runtime Stress-Aware Replica Placement on Reconfigurable Devices under Safety Constraints. Proceedings of the International Conference on Field-Programmable Technology (FPT'11), New Delhi, India. Dec. 12-14, 2011. ©1

440 S. Boppu,, F. Hannig, J. Teich and R. Perez-Andrade. Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays. Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), pp. 392-397, Cancun, Mexico, Nov. 30 - Dec.2, 2011. ©1

439 V. Lari, S. Boppu, S. Muddasani, F. Hannig and J. Teich. Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays. International Workshop on Adaptive Power Management with Machine Intelligence at International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov. 10, 2011. ©1

438 S. Wildermann, F. Reimann, D. Ziener and J. Teich. Symbolic Design Space Exploration for Multi-Mode Reconfigurable Systems. Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 129-138, Taipei, Taiwan. Oct. 9-14, 2011. (Best Paper Candidate). ©1

437 P. Marwedel, J. Teich, G. Kouveli, I. Bacivarov, L. Thiele, S. Ha, C. Lee, Q. Xu and L. Huang. Mapping of Applications to MPSoCs. Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 109-118, Taipei, Taiwan. Oct. 9-14, 2011. ©1

436 J. Henkel, L. Bauer, J. Becker, O. Bringmann, U. Brinkschulte, S. Chakraborty, M. Engel, R. Ernst, H. Härtig, L. Hedrich, A. Herkersdorf, R. Kapitza, D. Lohmann, P. Marwedel, M. Platzner, W. Rosenstiel, U. Schlichtmann, O. Spinczyk, M. Tahoori, J. Teich, N. Wehn and H. Wunderlich. Design and Architectures for Dependable Embedded Systems. Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 69-78, Taipei, Taiwan. Oct. 9-14, 2011. ©1

435 M. Streubühr, R. Rosales, R. Hasholzner, C. Haubelt and J. Teich. ESL Power and Performance Estimation for Heterogeneous MPSoCs Using SystemC. In Forum on specification and Design Languages 2011, pp. 202-209, Oldenburg, Germany, Sep. 13-15, 2011. ©3

434 V. Lari, A. Narovlyanskyy, F. Hannig and J. Teich. Decentralized Dynamic Resource Management Support for Massively Parallel Processor Arrays. In Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), pp. 87-94, Santa Monica, CA, USA, Sep. 11-14, 2011. ©3

433 J. Angermeier, D. Ziener, M. Glaß and J. Teich. Stress-Aware Module Placement on Reconfigurable Devices. Proceedings of the Conference on Field-Programmable Logic and Applications (FPL 2011), pp. 277-281, Chania, Crete, Greece. Sep 5-7. 2011. ©1

432 S. Wildermann, D. Ziener and J. Teich. Unifying Partitioning and Placement for SAT-based Exploration of Heterogeneous Reconfigurable SoCs. Proceedings of the Conference on Field Programmable Logic and Applications (FPL 2011), pp. 429-434, Chania, Crete, Greece, Sep. 5-7, 2011. ©1

431 D. Ziener, S. Wildermann, A. Oetken, A. Weichslgartner and J. Teich. A Flexible Smart Camera System based on a Partially Reconfigurable Dynamic FPGA-SoC. Proceedings of the Workshop on Computer Vision on Low-Power Reconfigurable Architectures at FPL 2011, pp. 29-30, Chania, Crete, Greece, Sep. 4, 2011. ©1

430 T. Ziermann, Z. Salcic and J. Teich. Self-organized Message Scheduling for Asynchronous Distributed Embedded Systems. Proceedings of the 8th International Conference on Autonomic and Trusted Computing, Banff, Canada, pp. 132-148, Sep. 2-4, 2011. ©1

429 R. Membarth, A. Lokhmotov and J. Teich. Generating GPU Code from a High-level Representation for Image Processing Kernels. In Proceedings of the 5th Workshop on Highly Parallel Processing on a Chip (HPPC), pp. 1-10, Bordeaux, France, Aug. 30, 2011. ©1

428 J. Gladigau, A. Gerstlauer, C. Haubelt, M. Streubühr and J. Teich. Automatic System-Level Synthesis: From Formal Application Models to Generic Bus-Based MPSoCs. Transactions on HiPEAC: Volume 5, Issue 4, pp. 1-22, Springer, 2011. ©1

427 J. Teich. Invasive Parallel Computing - In Introduction. Par Lab and AMP Lab Seminar Talk, UC Berkeley, CA, USA, July 22, 2011. ©1

426 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert. Domain-specific Computing and Code Generation for Medical Imaging. Poster Presentation at the 2nd Programming and Tuning Massively Parallel Systems Summer School (PUMPS), Barcelona, Spain, Jul. 18-22, 2011. ©1

425 J. Teich and D. Ziener. Verifying the Authorship of Embedded IP Cores: Watermarking and Core Identification Techniques. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'11), pp. 93-103, Las Vegas, USA, Jul. 18-21, 2011. ©1

424 M. Lukasiewycz, M. Glaß, F. Reimann and J. Teich. Opt4J - A Modular Framework for Meta-heuristic Optimization. Proceedings of the Genetic and Evolutionary Computing Conference (GECCO 2011), pp. 1723-1730, Dublin, Ireland, Jul. 12-16, 2011. ©1

423 G. Kouveli, F. Hannig, J. Lupp and J. Teich. Towards Resource-Aware Programming on Intel's Single-Chip Cloud Computer Processor. In 3rd Many-core Applications Research Community (MARC) Symposium, Ettlingen, Germany, Jul. 5-6, 2011, volume 7598 of KIT Scientific Reports, pp. 111-114, KIT Scientific Publishing, 2011. ©1

422 F. Hannig, S. Roloff, G. Snelting, J. Teich and A. Zwinkau. Resource-Aware Programming and Simulation of MPSoC Architectures through Extension of X10. In Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems (SCOPES'11). ACM, New York, NY, USA, pp. 48-55, St. Goar, Germany, Jun. 27-28, 2011. ©1

421 D. Kissler, D. Gran, Z. Salcic, F. Hannig and J. Teich. Scalable Many-Domain Power Gating in Coarse-grained Reconfigurable Processor Arrays. IEEE Embedded Systems Letters, 3(2):58-61, 2011. ©1

420 T. Ziermann, S. Wildermann and J. Teich. OrganicBus: Organic Self-organising Bus-Based Communication Systems. In Organic Computing - A Paradigm Shift for Complex Systems, pp. 489-501, Birkhäuser Verlag, 2011. ©1

419 R. Kiesel, M. Streubühr, C. Haubelt, O. Löhlein and J. Teich. Calibration and Validation of Software Performance Models for Pedestrian Detection Systems. In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XI), pp. 182-189, Samos, Greece, Jul. 18-21, 2011. ©1

418 A. Kern, H. Zhang, T. Streichert and J. Teich. Testing Switched Ethernet Networks in Automotive Embedded Systems. In Proceedings of the 6th IEEE International Symposium on Industrial Embedded Systems (SIES 2011), pp. 150-155, Västerås, Sweden, Jun. 15-17, 2011. ©1

417 F. Reimann, M. Lukasiewycz, M. Glaß, C. Haubelt and J. Teich. Symbolic System Synthesis in the Presence of Stringent Real-Time Constraints. Proceedings of the 48th Design Automation Conference (DAC 2011), pp. 393-398, San Diego, USA, Jun. 5-10, 2011. ©1

416 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert. Frameworks for GPU Accelerators: A Comprehensive Evaluation using 2D/3D Image Registration. In Proceedings of the 9th IEEE Symposium on Application Specific Processors (SASP), pp. 78-81, San Diego, CA, USA, Jun. 5-6, 2011. ©3

415 A. Kern, H. Zinner, T. Streichert, J. Nöbauer and J. Teich. Accuracy of Ethernet AVB Time Synchronization Under Varying Temperature Conditions for Automotive Networks. Proceedings of the 48th Design Automation Conference (DAC 2011), pp. 597-602, San Diego, USA, Jun. 5–10, 2011. ©1

414 R. Membarth, H. Dutta, F. Hannig and J. Teich. Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards. Transactions on High-Performance Embedded Architectures and Compilers (Transactions on HiPEAC), 5(3), 2011. ©3

413 P. Kutzer, J. Gladigau, C. Haubelt and J. Teich. Automatic Generation of System-Level Virtual Prototypes from Streaming Application Models. Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, pp. 128-134, Karlsruhe, Germany, May 24-27, 2011. ©1

412 V. Lari, F. Hannig and J. Teich. Distributed Resource Reservation in Massively Parallel Processor Arrays. In Proceedings of the International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 318-321, Anchorage, AK, USA, May 16-17, 2011. ©3

411 S. Graf, M. Streubühr, M. Glaß and J. Teich. Analyzing Automotive Networks using Virtual Prototypes. In Proceedings of Automotive meets Electronics (AmE 2011) GMM Fachbericht 69, pp. 10-15, Dortmund, Germany, May 4-5, 2011. ©1

410 A. Weichslgartner, S. Wildermann and J. Teich. Dynamic Decentralized Mapping of Tree-Structured Applications on NoC Architectures. In Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2011), pp. 201-208, Pittsburgh, USA, May 1-4. ©1

409 T. Ziermann, S. Wildermann and J. Teich. Distributed Self-organizing Bandwidth Allocation for Priority-based Bus Communication. In Concurrency and Computation: Practice and Experience, Wiley Online Library, DOI=http://dx.doi.org/10.1002/cpe.1759, 2011. ©1

408 N. Mühleis, M. Glaß, L. Zhang and J. Teich. A Co-Simulation Approach for Control Performance Analysis during Design Space Exploration of Cyber-Physical Systems. ACM SIGBED Review - Work-in-Progress (WiP) Session of the 2nd International Conference on Cyber Physical Systems (ICCPS 2011). Volume 8(2): pp. 23-26, 2011. ©1

407 J. Angermeier, E. Sibirko, R. Wanka and J. Teich. Bitonic Sorting on Dynamically Reconfigurable Architectures. In Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing (IPDPS'11), pp. 314-317, Anchorage, USA, May 16-20, 2011, [doi:10.1109/IPDPS.2011.164]. ©1

406 J. Falk, C. Zebelein, C. Haubelt and J. Teich. A Rule-Based Static Dataflow Clustering Algorithm for Efficient Embedded Software Synthesis. Proceedings of Design, Automation and Test in Europe (DATE'11), IEEE Computer Society, Grenoble, France, pp. 521-526, Mar. 14-18, 2011. ©3

405 T. Ziermann, Z. Salcic and J. Teich. DynOAA - Dynamic Offset Adaptation Algorithm for Improving Response Times of CAN Systems. Proceedings of Design, Automation and Test in Europe (DATE'11), IEEE Computer Society, Grenoble, France, pp. 269-272, Mar. 14-18, 2011. ©3

404 A. Kern, T. Streichert and J. Teich. An Automated Data Structure Migration Concept - From CAN to Ethernet/IP in Automotive Embedded Systems (CANoverIP). Proceedings of Design, Automation and Test in Europe (DATE'11), IEEE Computer Society, Grenoble, France, pp. 112-117, Mar. 14-18, 2011 . ©1

403 P. Kutzer, M. Streubühr, C. Haubelt, J. Teich and A. von Schwerin. Actor-oriented Modeling of Industrial Ethernet in the Automation Domain Using SystemC . Proceedings of the Embedded World Conference, pp. 1-10, Nuremberg, Germany, Mar. 1-3, 2011. ©1

402 N. Mühleis, M. Glaß and J. Teich. Control Performance-Aware System Level Design. In Proceedings of the 8th Workshop on Cyber-Physical Systems – Enabling Multi-Nature Systems (CPMNS 2011), pp. 15-20, Bremen, Germany, Feb. 23-24, 2011. ©1

401 J. Keinert and J. Teich. Design of Image Processing Embedded Systems Using Multidimensional Data Flow. Series Embedded Systems, Springer, New York, 1st edition, 2011. ©1

400 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert. Frameworks for Multi-core Architectures: A Comprehensive Evaluation using 2D/3D Image Registration. In Proceedings of the 24th International Conference on Architecture of Computing Systems (ARCS), pp. 62-73, Lake Como, Italy, February 22-25, 2011. ©1

399 A. Kern, D. Reinhard, T. Streichert and J. Teich. Gateway Strategies for Embedding of Automotive CAN-frames into Ethernet-packets and Vice Versa. Proceedings of Architecture of Computing Systems Conference (ARCS'11), pp. 259-270, Lake Como, Italia, Feb. 22-25, 2011. ©1

398 R. Membarth, F. Hannig, J. Teich, G. Litz and H. Hornegger. Detector Defect Correction of Medical Images on Graphics Processors. Proceedings of the SPIE: Medical Imaging 2011: Image Processing, pp. 79624M 1-12, Lake Buena Vista, Orlando, FL, USA, Feb. 12-17, 2011. ©1

397 D. Kissler, F. Hannig and J. Teich. Efficient Evaluation of Power/Area/Latency Design Trade-offs for Coarse-Grained Reconfigurable Processor Arrays. Journal of Low Power Electronics, 7(1):29-40, 2011. ©1

396 J. Teich, J. Henkel, A. Herkersdorf, D. Schmitt-Landsiedel, W. Schröder-Preikschat and G. Snelting. Invasive Computing: An Overview. In Multiprocessor System-on-Chip, M. Hübner and J. Becker (Eds.), Chapter 11, pages 241-268, Springer, 2011. ©1

2010

395 J. Falk, C. Zebelein, J. Keinert, C. Haubelt, J. Teich and S. Bhattacharyya. Analysis of SystemC actor networks for efficient synthesis. ACM Transactions on Embedded Computing Systems, 10(2):94–127, 2010. ©1

394 J. Angermeier, S. Wildermann, E. Sibirko and J. Teich. Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures. Proceedings of International Conference on ReConFigurable Computing and FPGAs, pp. 91-96, December 13-15, 2010, Cancun, Mexico. ©1

393 F. Hannig, M. Schmid, J. Teich and H. Hornegger. A Deeply Pipelined and Parallel Architecture for Denoising Medical Images. In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT), pp. 485-490, Beijing, China, December 8-10, 2010. ©3

392 D. Ziener and J. Teich. New Directions for FPGA IP Core Watermarking and Identification. In Dagstuhl Seminar 10281 Proceedings, 2010. ©1

391 M. Glaß, M. Lukasiewycz, F. Reimann, C. Haubelt and J. Teich. Symbolic System Level Reliability Analysis. In Proceedings of the International Conference on Computer-Aided Design (ICCAD), pp. 185-189, San Jose, USA, November 07-11, 2010. Tutorial Paper. ©1

390 S. Wildermann, A. Oetken, J. Teich and Z. Salcic. Self-Organizing Computer Vision for Robust Object Tracking in Smart Cameras. In Proceedings of the 7th International Conference on Autonomic and Trusted Computing, pp. 1-16, Xi'an, China, October 26-29, 2010. (Best Paper). ©1

389 F. Reimann, M. Glaß, C. Haubelt, M. Eberl and J. Teich. Improving Platform-Based System Synthesis by Satisfiability Modulo Theories Solving. In Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 135-144, Scottsdale, USA. October 24-29 2010. ©3

388 D. Ziener, M. Schmid and J. Teich. Robustness Analysis of Watermark Verification Techniques for FPGA Netlist Cores. In Design Methodologies for Secure Embedded Systems, A. Biedermann and H. Gregor Molter (Eds.), Lecture Notes in Electrical Engineering, volume 78, pp. 105-127, Springer-Verlag, Berlin Heidelberg, 2010. ©1

387 J. Teich. Invasive Computing - Basic Concepts and Foreseen Benefits. Artist Network of Excellence on Embedded System Design Summer School Europe 2010, Autrans, France, September 7, 2010, Invited Tutorial. ©1

386 A. Oetken, S. Wildermann, J. Teich and D. Koch. A Bus-based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs. In Proceedings of International Conference on Field-Programmable Logic and Applications (FPL'10), pp. 234-239, Milan, Italy, 2010. ©3

385 J. Falk, J. Keinert, C. Haubelt, J. Teich and C. Zebelein. Integrated Modeling Using Finite State Machines and Dataflow Graphs. In Handbook of Signal Processing Systems, pp. 1041-1075, Springer, 2010. ©1

384 J. Teich. Invasive Computing - An Overview. Invited Talk, The University of Sydney, Australia, August 9, 2010. ©1

383 J. Teich. Invasive Computing - A Novel Paradigm for Parallel Computing. Presentation at the School of Computing, National University of Singapore (NUS), Singapore, August 6. 2010. ©1

382 A. Kern, C. Schmutzler, T. Streichert, M. Hübner and J. Teich. Network Bandwidth Optimization of Ethernet-based Streaming Applications in Automotive Embedded Systems. In Proceedings of the Internaional Conference on Computer Communication Networks (ICCCN) 2010 – Track on Network Algorithms, Performance Evaluation and Theory (NAPET), Zurich, Switzerland, August 2-5, 2010. ©1

381 M. Streubühr, J. Gladigau, C. Haubelt and J. Teich. Efficient Approximately-Timed Performance Modeling for Architectural Exploration of MPSoCs. In D. Borrione editor, Advances in Design Methods from Modeling Languages for Embedded Systems and SoC's, volume 63 of Lecture Notes in Electrical Engineering. pp. 59-72, Springer Netherlands, 2010. ©1

380 J. Gladigau, A. Gerstlauer, M. Streubühr, C. Haubelt and J. Teich. A System-Level Synthesis Approach from Formal Application Models to Generic Bus-Based MPSoCs. Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), pp. 118-125, Samos, Greece, July 19-22, 2010. ©3

379 F. Charot, F. Hannig, J. Teich and C. Wolinski. Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society, 2010, ISBN 978-1-4244-6967-3. ©3

378 C. Haubelt and J. Teich. Digitale Hardware/Software-Systeme: Spezifikation und Verifikation. 1. Auflage, ©Springer-Verlag, Berlin, Heidelberg, Germany, 2010. ©1

377 D. Ziener, F. Baueregger and J. Teich. Multiplexing Methods for Power Watermarking. In Proceedings of the IEEE Int. Symposium on Hardware-Oriented Security and Trust (HOST 2010), pp. 54-59, Anaheim, USA, June 13-14, 2010. ©2

376 J. Teich. Invasive Computing - A Novel Parallel Computing Paradigm. Invited Talk, Workshop Multiprocessor System-On-Chip (MPSOC): Programmability, Run-Time Support and Hardware Platforms for High Performance Applications, 47th Design Automation Conference (DAC), Anaheim, USA, June 13, 2010. ©1

375 M. Glaß, M. Lukasiewycz, C. Haubelt and J. Teich. Towards Scalable System-Level Reliability Analysis. In Proceedings of the 2010 ACM/EDAC/IEEE Design Automation Conference (DAC 2010), pp. 234-239, Anaheim, CA, U.S.A., June 13-18, 2010. ©1

374 T. Ziermann, N. Mühleis, S. Wildermann and J. Teich. Self-organizing Distributed Reinforcement Learning Algorithm to Achieve Fair Bandwidth Allocation for Priority-based Bus Communication. In Proceedings of the 1st IEEE Workshop on Self-Organizing Real-Time systems (SORT 2010), pp. 11-20, Carmona, Spain, 11 May 2010, Invited Paper. ©2

373 J. Sim, W. Wong, G. Walla, T. Ziermann and J. Teich. Interprocedural Placement-Aware Configuration Prefetching for FPGA-based Systems. In Proceedings of the 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'10), Charlotte, USA, pp. 179 - 182, May 02-04, 2010, HiPEAC Award. ©1

372 D. Ziener, F. Baueregger and J. Teich. Using the Power Side Channel of FPGAs for Communication. In Proceedings of the 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'10), pp. 237-244, Charlotte, USA, May 02-04, 2010. ©1

371 J. Angermeier, J. Teich, T. Kamphans and S. Fekete. Virtual Area Management: Multitasking on Dynamically Partially Reconfigurable Devices. In Proceedings of 17th Reconfigurable Architectures Workshop (RAW 2010), Atlanta, USA, April 2010. ©1

370 T. Ziermann and J. Teich. Adaptive Traffic Scheduling Techniques for Mixed Real-Time and Streaming Applications on Reconfigurable Hardware. In Proceedings of 17th Reconfigurable Architectures Workshop (RAW 2010), Atlanta, USA, April 19-20, 2010. ©2

369 J. Teich. Invasives Rechnen. Eingeladener Vortrag, 30. Sitzung Leitungskreis der Fachgruppe RSS (Rechnergestützter Schaltungs- und Systementwurf), VDE, Frankfurt am Main, April 9, 2010. ©1

368 F. Reimann, A. Kern, C. Haubelt, T. Streichert and J. Teich. Echtzeitanalyse Ethernet-basierter E/E-Architekturen im Automobil. In: GMM-Fachbericht -- Automotive meets Electronics (AmE 2010), (64), 2010, p. 9–14. ©1

367 T. Ziermann and J. Teich. Electromagnetic Compatibility (EMC) of CAN+. Proceedings of Automotive meets Electronics (AmE 2010), pp. 25-30, Dortmund, Germany, April 15-16, 2010. ©1

366 J. Teich. The DFG Priority Program 1148 Reconfigurable Computing - Achievements and Lessons Learned. DATE Friday Workshop The European Landscape of Reconfigurable Computing: Lessons Learned, new Perspectives and Innovations, Dresden, Germany, March 2010. Invited Talk. ©1

365 H. Dutta, F. Hannig and J. Teich. PARO - A Design Tool for Synthesis of Hardware Accelerators for SoCs. Tool Presentation at the University Booth at Design, Automation and Test in Europe (DATE), Dresden, Germany, March 8-12, 2010. ©1

364 M. Lukasiewycz, M. Glaß and J. Teich. Robust Design of Embedded Systems. In Proceedings of Design, Automation and Test in Europe (DATE 2010), pp. 1578-1583, Dresden, Germany, March 08-12, 2010. ©1

363 C. Zebelein, J. Falk, C. Haubelt, J. Teich and R. Dorsch. Efficient High-Level Modeling in the Networking Domain. In Proceedings of Design, Automation and Test in Europe (DATE 2010) Dresden, Germany, pp. 1189-1194, March 8-12, 2010. ©1

362 M. May, N. Wehn, A. Bouajila, J. Zeppenfeld, W. Stechele, A. Herkersdorf, D. Ziener and J. Teich. A Rapid Prototyping System for Error-Resilient Multi-Processor Systems-on-Chip. Proceedings of Design, Automation and Test in Europe (DATE'10), Dresden, Germany, March 08-12, pp. 375-380, 2010. ©1

361 R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert. Comparison of Parallelization Frameworks for Shared Memory Multi-Core Architectures. Proceedings of the Embedded World Conference, Nuremberg, Germany, March 03-05, 2010. ©1

360 M. Schmid, F. Hannig, J. Teich, R. Diefenbach, H. Pettendorf and H. Hornegger. Discourse on Extending Embedded Medical Image Processing Systems Using the High Speed Serial RapidIO Interconnect. Proceedings of the Embedded World Conference, Nuremberg, Germany, March 03-05, 2010. ©1

359 J. Falk, C. Zebelein, C. Haubelt, J. Teich and R. Dorsch. Integrating Hardware/Firmware Verification Efforts Using SystemC High-Level Models. In 13. ITG/GI/GMM Workshop für Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Fraunhofer IIS/EAS Dresden, pp. 137-146, February 22-24, 2010. ©1

358 R. Kiesel, O. Löhlein, A. Terzis, M. Streubühr, C. Haubelt and J. Teich. Actor-oriented Modeling of Driver Assistance Systems for Efficient Multi-Core ECU Implementation. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, pp 117-126, Dresden, Germany, Feb. 2010. ©1

357 M. Platzner, J. Teich and N. Wehn. Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications. Springer, Heidelberg, February 2010. ©1

356 S. Fekete, T. Kamphans, N. Schweer, C. Tessars, J. van der Veen, A. Ahmadinia, J. Angermeier, D. Koch, M. Majer and J. Teich. ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices. In Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications, p. 199-222, Springer, Heidelberg, February 2010. ©1

355 J. Angermeier, C. Bobda, M. Majer and J. Teich. Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform. In Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications, p. 51-71, Springer, Heidelberg, February 2010. ©1

354 D. Koch, T. Streichert, C. Haubelt, F. Reimann and J. Teich. ReCoNets – Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections. In Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications, p. 223-244, Springer, Heidelberg, February 2010. 10.1007/978-90-481-3485-4_11. ©1

353 M. Glaß, M. Lukasiewycz, C. Haubelt and J. Teich. Lifetime Reliability Optimization for Embedded Systems: A System-Level Approach. Proceedings of IEEE International Workshop on Reliability Aware System Design and Test (RASDAT '10), pp. 17-22, Bangalore, India, January 07-08, 2010. ©1

2009

352 V. Schöber, O. Bringmann, A. Herkersdorf, W. Stechele, N. Wehn, M. May, D. Ziener, A. Bouajila, D. Baldin, J. Zeppenfeld, B. Sanders, J. Teich, M. Sebastian, R. Ernst and D. Treytnar. AIS-Autonomous Integrated Systems. In newsletter edacentrum 04 2009, pp. 05-13, edacentrum, Hannover, 2009. ©1

351 S. Wildermann, T. Ziermann and J. Teich. Run time Mapping of Adaptive Applications onto Homogeneous NoC-based Reconfigurable Architectures. In Proceedings of the International Conference on Field-Programmable Technology (FPT'09), pp. 514-517, Sydney, Australia, December 9-11, 2009. ©1

350 A. Amouri, F. Arifin, F. Hannig and J. Teich. FPGA Implementation of an Invasive Computing Architecture. In Proceedings of the International Conference on Field-Programmable Technology (FPT), pp. 135-142, Sydney, Australia, December 9-11, 2009. ©2

349 J. Teich. From Dynamic Reconfiguration to Self-Configuration: Invasive Algorithms and Architectures. Proc. 2009 International Conference on Field-Programmable Technology (FPT'09), Sydney, Australia , pp. 11-12, December 9-11, 2009. ©1

348 H. Greve, S. Egelkraut, M. Rösch, M. Glaß, M. März, J. Franke, J. Teich and L. Frey. Zuverlässigkeitsuntersuchung von PBGA Lotverbindungen für Automobilanwendungen. In Proceedings of IMAPS 2009, Munich, Germany, October 27-28, 2009. ©1

347 F. Arifin, R. Membarth, A. Amouri, F. Hannig and J. Teich. FSM-Controlled Architectures for Linear Invasion. Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 59-64, Florianópolis, Brazil, October 12-14, 2009. ©2

346 M. Lukasiewycz, M. Glaß, P. Milbredt and J. Teich. FlexRay Schedule Optimization of the Static Segment. In Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 363-372, Grenoble, France, October 11-16 2009. ©1

345 M. Lukasiewycz, M. Glaß and J. Teich. Exploiting Data-Redundancy in Reliability-Aware Networked Embedded System Design. In Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 229-238, Grenoble, France, October 11-16 2009. ©1

344 A. Gerstlauer, C. Haubelt, A. Pimentel, T. Stefanov, D. Gajski and J. Teich. Electronic System-Level Synthesis Methodologies. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(10), pages 1517-1530, October 2009. ©1

343 M. Streubühr, J. Gladigau, C. Haubelt and J. Teich. Efficient Approximately-Timed Performance Modeling for Architectural Exploration of MPSoCs. In Forum on specification and Design Languages 2009, pp. 1-6, Sophia Antipolis, France, Sep. 22-24, 2009. ©1

342 V. Lari, F. Hannig and J. Teich. System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance. In proceedings of the 38th International Conference on Parallel Processing Workshops - the 4th International Symposium on Embedded Multicore Systems-on-Chip (MCSoC'09), pp. 528-534, Vienna, Austria, Sep. 22-25, 2009. ©2

341 S. Wildermann, T. Ziermann and J. Teich. Self-organizing Bandwidth Sharing in Priority-based Medium Access. In Proceedings of the Third IEEE International Conference on Self-Adaptive and Self-Organizing Systems (SASO), pp.144-153, San Francisco, California, Sep. 14-18, 2009 . ©1

340 S. Wildermann, G. Walla, T. Ziermann and J. Teich. Self-Organizing Multi-cue Fusion for FPGA-based Embedded Imaging. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), pp. 132 - 137, Prague, Czech Republic, Aug. 31 - Sep. 02, 2009. ©1

339 M. Glaß, M. Lukasiewycz, J. Teich, U. Bordoloi and S. Chakraborty. Designing Heterogeneous ECU Networks via Compact Architecture Encoding and Hybrid Timing Analysis. In Proceedings of the 2009 ACM/EDAC/IEEE Design Automation Conference (DAC 2009), pp. 43-46, San Francisco, CA, U.S.A., July 26-31, 2009. ©1

338 R. Membarth, F. Hannig, H. Dutta and J. Teich. Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. Proceedings of the 9th International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS Workshop), pp. 277-288, Samos, Greece, July 20-23, 2009. ©1

337 R. Membarth, F. Hannig, H. Dutta and J. Teich. Optimization Flow for Algorithm Mapping on Graphics Cards. Proceedings of ACACES 2009 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems, pp. 229-232, Barcelona, Spain, July 12-18, 2009. ©1

336 R. Membarth, P. Kutzer, H. Dutta, F. Hannig and J. Teich. Acceleration of Multiresolution Imaging Algorithms: A Comparative Study. Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 211-214, Boston, MA, USA, July 7-9, 2009. ©2

335 D. Ziener and J. Teich. Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs. Int. Journal of Autonomous and Adaptive Communications Systems, Vol. 2, No. 3, pp. 256-275, Inderscience Enterprises Ltd, 2009. ©1

334 J. Angermeier, A. Amouri and J. Teich. General Methodology for Mapping Iterative Aproximation Algorithms to Adaptive Dynamically Partially Reconfigurable Systems. Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pp. 302-307, Prague, Czech Republic, August 31, 2009. ©1

333 J. Gladigau, C. Haubelt and J. Teich. Symbolic Scheduling of SystemC Dataflow Designs. In M. Radetzki, editor, Languages for Embedded Systems and their Applications, volume 36 of Lecture Notes in Electrical Engineering, pages 183–199. Springer Netherlands, 2009. Available at SpringerLink: here. ©1

332 J. Keinert and J. Teich. Data Flow Based System Level Design and Analysis of Image Processing Applications. Poster on the EDAA PhD forum at DATE 2009, Nice, April 2009. ©1

331 J. Keinert, C. Haubelt and J. Teich. Data Flow Based System Level Design and Analysis of Concurrent Image Processing Applications. Proceedings of DATE'09 Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Nice, April 2009, pp. 215-216. ©1

330 H. Dutta, J. Zhai, F. Hannig and J. Teich. Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines. Proceedings of 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), pp. 161-168, Boston, MA, USA, July 7-9, 2009. ©1

329 T. Ziermann, S. Wildermann and J. Teich. CAN+: A New Backward-compatible Controller Area Network (CAN) Protocol with up to 16x Higher Data Rates. Proceedings of Design, Automation and Test in Europe (DATE 2009), IEEE Computer Society, Nice, France, pp. 1088-1093, April 20-24, 2009. ©1

328 J. Keinert, H. Dutta, F. Hannig, C. Haubelt and J. Teich. Model-Based Synthesis and Optimization of Static Multi-Rate Image Processing Algorithms. Proceedings of Design, Automation and Test in Europe (DATE 2009), IEEE Computer Society, Nice, France, April 20-24, 2009, pp. 135-140. ©1

327 M. Lukasiewycz, M. Streubühr, M. Glaß, C. Haubelt and J. Teich. Combined System Synthesis and Communication Architecture Exploration for MPSoCs. Proceedings of Design, Automation and Test in Europe (DATE 2009), pp. 472-477, IEEE Computer Society, Nice, France, April 20-24, 2009. ©1

326 M. Glaß, M. Lukasiewycz, C. Haubelt and J. Teich. Incorporating Graceful Degradation into Embedded System Design. Proceedings of Design, Automation and Test in Europe (DATE 2009), pp. 320-323, IEEE Computer Society, Nice, France, April 20-24, 2009. ©1

325 D. Koch, C. Beckhoff and J. Teich. A Communication Architecture for Complex Runtime Reconfigurable Systems and its Implementation on Spartan-3 FPGAs. Proceedings of the 17th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2009), pp. 233-236, Monterey, California, USA Extended paper version:. ©2

324 J. Sim, W. Wong and J. Teich. Optimal Placement-aware Trace-based Scheduling of Hardware Reconfigurations for FPGA Accelerators. Proceedings 17th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2009), Napa, California, pp. 279-282, April, 2009. ©1

323 D. Koch, C. Beckhoff and J. Teich. Minimizing Internal Fragmentation by Fine-grained Two-dimensional Module Placement for Runtime Reconfigurable Systems. Proceedings 17th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2009), pp. 251-254, Napa, California, April, 2009. ©1

322 T. Ziermann, J. Teich and S. Wildermann. CAN+: Techniques and Prototype for Achieving Increased Data Rates on the Basis of Common CAN Bus Structures. Proceedings of 9th Stuttgart International Symposium, pp. 327-339, Stuttgart, Germany, March 24-25, 2009 . ©1

321 H. Dutta, F. Hannig and J. Teich. Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis. In Proceedings of the 22nd International Conference on Architecture of Computing Systems (ARCS), Delft, The Netherlands, pp. 233-245, March 10-13, 2009. ©1

320 F. Hannig, H. Dutta and J. Teich. Parallelization Approaches for Hardware Accelerators - Loop Unrolling versus Loop Partitioning. In Proceedings of the 22nd International Conference on Architecture of Computing Systems (ARCS), Delft, The Netherlands, pp. 16-27, March 10-13, 2009. ©1

319 M. Streubühr, M. Jäntsch, C. Haubelt and J. Teich. From Model-based Design to Virtual Prototypes for Automotive Applications. In Proceedings of the Embedded World Conference, pp. 1-10, Nuremberg, Germany, March 03-05, 2009. ©1

318 J. Gladigau, C. Haubelt, M. Streubühr, J. Teich, A. Schneider, J. Knäblein and M. Lindig. Testfallgenerierung für SystemC-Designs mit abstrakten Modellbeschreibungen. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Seite 157-166, Berlin, Germany, March 2-4, 2009. ©1

317 D. Kissler, A. Strawetz, F. Hannig and J. Teich. Power-efficient Reconfiguration Control in Coarse-grained Dynamically Reconfigurable Architectures. Journal of Low Power Electronics, 5(1):96-105, American Scientific Publishers, 2009. ©1

316 H. Dutta, D. Kissler, F. Hannig, A. Kupriyanov, J. Teich and B. Pottier. A Holistic Approach for Tightly Coupled Reconfigurable Parallel Processors. Microprocessors and Microsystems, 33(1):53-62, 2009. ©1

315 J. Keinert, M. Streubühr, T. Schlichter, J. Falk, J. Gladigau, C. Haubelt, J. Teich and M. Meredith. SYSTEMCODESIGNER - An Automatic ESL Synthesis Approach by Design Space Exploration and Behavioral Synthesis for Streaming Applications. In ACM Transactions on Design Automation of Electronic Systems, 14(1), pp. 1-23, 2009. ©1

314 M. Streubühr, C. Haubelt and J. Teich. System Level Performance Simulation for Heterogeneous Multi-Processor Architectures. 1st HiPEAC Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), in conjunction with the 4th HiPEAC Conference, pp. 47-52, Paphos, Cyprus, January 25, 2009. ©1

313 D. Koch, C. Beckhoff and J. Teich. Hardware Decompression Techniques for FPGA-based Embedded Systems. ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol.2, no. 9, June 2009. ©1

2008

312 M. Schmid, D. Ziener and J. Teich. Netlist-Level IP Protection by Watermarking for LUT-Based FPGAs. In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2008), pp. 209-216, Taipei, Taiwan, December 08-10, 2008. ©1

311 J. Falk, J. Keinert, C. Haubelt, J. Teich and S. Bhattacharyya. A Generalized Static Data Flow Clustering Algorithm for MPSoC Scheduling of Multimedia Applications. In Proc. of the 8th ACM & IEEE international conference on Embedded software (EMSOFT'2008), pp. 189-198, Atlanta, Georgia, USA, October 20-22, 2008. ©1

310 F. Reimann, M. Glaß, M. Lukasiewycz, J. Keinert, C. Haubelt and J. Teich. Symbolic Voter Placement for Dependability-Aware System Synthesis. In Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 237-242, Atlanta, GA USA, October 19-24 2008. ©1

309 J. Keinert, C. Haubelt and J. Teich. Automatic Synthesis of Design Alternatives for Fast Stream-Based Out-of-Order Communication. Proceedings of the 2008 IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, (VLSI-SoC 2008) pp. 265-270, Rhodes Island, Greece, October 13-15, 2008. ©1

308 J. Teich. Invasive Algorithms and Architectures. it - Information Technology, http://it-information-technology.de, Oldenbourg Wissenschaftsverlag, vol. 50(5):300-310, 2008. ©1

307 J. Gladigau, C. Haubelt and J. Teich. Symbolic Quasi-Static Scheduling of Actor-Oriented SystemC Models. Proceedings of Forum on specification & Design Languages 2008 (FDL08), Digital Object Identifier 10.1109/FDL.2008.4641412, pages 1-6, Stuttgart, Germany, Sep. 23-25, 2008. ©2

306 M. Glaß, M. Lukasiewycz, F. Reimann, C. Haubelt and J. Teich. Symbolic Reliability Analysis of Self-healing Networked Embedded Systems. In Proceedings of the 27th International Conference on Computer Safety, Reliability and Security (SAFECOMP 2008), pp. 139-152, Newcastle upon Tyne, UK, September 22-25, 2008. ©1

305 M. Lukasiewycz, M. Glaß and J. Teich. A Feasibility-preserving Crossover and Mutation Operator for Constrained Combinatorial Problems. In Proceedings of the 10th International Conference on Parallel Problem Solving from Nature (PPSN 2008), pp. 919-928, Dortmund, Germany, September 13-17, 2008. ©1

304 S. Wildermann and J. Teich. A Sequential Learning Resource Allocation Network for Image Processing Applications. Proceedings of the 8th International Conference on Hybrid Intelligent Systems (HIS 2008), pp. 132-137, Barcelona, Spain, September 10-12, 2008. ©2

303 S. Fekete, J. van der Veen, A. Ahmadinia, D. Göhringer, M. Majer and J. Teich. Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.16(9):1210-1219, September 2008. ©1

302 C. Claus, W. Stechele, M. Kovatsch, J. Angermeier and J. Teich. A comparison of embedded reconfigurable video-processing architectures. Proceedings of 18th International Conference on Field Programmable Logic and Applications (FPL 2008), Heidelberg, Germany, September 8 - 10, 2008, pp. 587-590.. ©1

301 C. Wolinski, K. Kuchcinski, J. Teich and F. Hannig. Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), pp. 391-396, Heidelberg, Germany, September 8-10, 2008. ©1

300 D. Koch, T. Streichert, C. Haubelt and J. Teich. Logic Chip, Logic System and Method for Designing a Logic Chip. Patent PCT/EP2008/007342, filed 8.9.2008. ©1

299 D. Koch, C. Beckhoff and J. Teich. ReCoBus-Builder – a Novel Tool and Technique to Build Statically and Dynamically Reconfigurable Systems for FPGAs. Proceedings of International Conference on Field-Programmable Logic and Applications (FPL 08), pp. 119-124, Heidelberg, Germany. ©1

298 S. Fekete, J. van der Veen, J. Angermeier, D. Koch and J. Teich. No-Break Dynamic Defragmentation of Reconfigurable Devices. Proceedings of International Conference on Field-Programmable Logic and Applications (FPL 08), pp. 113-118, Heidelberg, Germany. ©1

297 D. Koch, T. Streichert, C. Haubelt and J. Teich. Logic Chip, Method and Computer Program for Providing a Configuration Information for a Configurable Logic Chip. Patent PCT/EP2008/007343, filed 8.9.2008. ©1

296 R. Schaffer, R. Merker, F. Hannig and J. Teich. Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. Proceedings of the 11th Euromicro Conference on Digital System Design (DSD), pp. 391-398, Parma, Italy, September 3-5, 2008. ©1

295 C. Wolinski, K. Kuchcinski, J. Teich and F. Hannig. Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. Proceedings of the 11th Euromicro Conference on Digital System Design (DSD), pp.345-352, Parma, Italy, September 3-5, 2008. ©1

294 C. Haubelt, J. Teich and R. Dorsch. Entdecke die Möglichkeiten. In Design&Elektronik (8):22-27, 2008, WEKA. ©1

293 M. Glaß, M. Lukasiewycz, R. Wanka, C. Haubelt and J. Teich. Multi-Objective Routing and Topology Optimization in Networked Embedded Systems. In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2008), pp. 74-81, Samos, Greece, July 21-24, 2008. ©1

292 S. Wildermann and J. Teich. Theoretical Analysis of Fair Bandwidth Sharing in Priority-based Medium Access. Technical Report 06-2008, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, June 2008. ©1

291 D. Ziener and J. Teich. Concepts for Autonomous Control Flow Checking for Embedded CPUs. In Proceedings of the 5th International Conference on Autonomic and Trusted Computing (ATC08), pp. 234-248, Oslo, Norway, June 23-25, 2008. ©1

290 H. Dutta, F. Hannig and J. Teich. PARO: A Design Tool for Automatic Generation of Hardware Accelerators.. In Proceedings of ACACES 2008 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems,. ©1

289 M. Lukasiewycz, M. Glaß, C. Haubelt, J. Teich, R. Regler and B. Lang. Concurrent Topology and Routing Optimization in Automotive Network Integration. In Proceedings of the 2008 ACM/EDAC/IEEE Design Automation Conference (DAC 2008), pp. 626-629, Anaheim, CA, U.S.A., June 08-13, 2008. ©1

288 J. Teich and F. Schäfer. ESL Methodologies for Platform-Based Synthesis. Special Session, 2008 ACM/EDAC/IEEE Design Automation Conference (DAC 2008), Anaheim, USA, June 08-13, 2008. ©1

287 C. Zebelein, J. Falk, C. Haubelt and J. Teich. Classification of General Data Flow Actors into Known Models of Computation. In Proc. of the Sixth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2008), pp. 119-128, Anaheim, CA, USA, June 5-7, 2008. ©1

286 M. Majer, S. Wildermann, J. Angermeier, S. Hanke and J. Teich. Co-Design Architecture and Implementation for Point-Based Rendering on FPGAs. Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping (RSP 2008), pp. 142-148, Monterey, California, June 2-5, 2008. ©2

285 M. Lukasiewycz, M. Glaß, C. Haubelt and J. Teich. A Feasibility-preserving Local Search Operator for Constrained Discrete Optimization Problems. In Proceedings of the 2008 IEEE Congress on Evolutionary Computation (CEC 2008), pp. 1968-1975, Hong Kong, China, June 01-06, 2008. ©1

284 A. Kupriyanov, F. Hannig, D. Kissler and J. Teich. MAML: An ADL for Designing Single and Multiprocessor Architectures. In Prabhat Mishra and Nikil Dutt (eds.). Chapter 12 in Processor Description Languages, pp. 295-327. In Systems on Silicon Series, Morgan Kaufmann, June 2008. ©1

283 D. Kissler, A. Strawetz, F. Hannig and J. Teich. Power-efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. In Proceedings of the 18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Lisbon, Portugal, September 10-12, 2008. LNCS vol. 5349, pp. 307–317. Springer, Heidelberg (2009). ©1

282 J. Angermeier and J. Teich. Heuristics for Scheduling Reconfigurable Devices with Consideration of Reconfiguration Overheads. Proceedings 15th Reconfigurable Architectures Workshop (RAW 2008), pp. 1-8, Miami, Florida, April 2008. ©1

281 D. Koch, C. Haubelt and J. Teich. Efficient Reconfigurable On-Chip Buses for FPGAs. Proceedings 16th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2008), pp. 287-290, Palo Alto, California, April 14-15, 2008. ©1

280 C. Wolinski, K. Kuchcinski, J. Teich and F. Hannig. Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. In Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 306-309, Palo Alto, CA, USA, April 14-15, 2008. ©1

279 J. Teich. Invasion - A New Parallel Computing and Architecture Paradigm. Dagstuhl Seminar No. 08141, Organic Computing - Controlled Self-organization, IBFI, March 31- April 4, 2008. ©1

278 D. Ziener and J. Teich. Power Signature Watermarking of IP Cores for FPGAs . Journal of Signal Processing Systems, Volume 51, Number 1 / April 2008, pages 123-136, Springer. ©1

277 F. Hannig, H. Ruckdeschel, H. Dutta and J. Teich. PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing (ARC), Lecture Notes in Computer Science (LNCS), pp. 287-293, Springer, London, United Kingdom, March 26-28, 2008. ©1

276 J. Angermeier, U. Batzer, M. Majer, J. Teich, C. Claus and W. Stechele. Reconfigurable HW/SW Architecture of a Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System. Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing (ARC), Lecture Notes in Computer Science (LNCS), pp. 149-159, Springer, London, United Kingdom, March 26-28, 2008. ©1

275 H. Dutta, F. Hannig and J. Teich. The PARO Design Tool for Automatic Generation of Hardware Accelerators. Interactive Presentation at Friday Workshop, The New Wave of the High-Level Synthesis, Design, Automation and Test in Europe (DATE), Munich, Germany, March 10-14, 2008. ©1

274 J. Teich, F. Hannig, H. Dutta, D. Kissler and M. Hartl. Domain-Specific Reconfigurable MPSoC-Systems - Challenges and Trends. Talk at Friday Workshop, Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures, Design, Automation and Test in Europe (DATE), Munich, Germany, March 10-14, 2008. ©1

273 D. Kissler, H. Dutta, A. Kupriyanov, F. Hannig and J. Teich. A High-Speed Dynamic Reconfigurable Multilevel Parallel Architecture. Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), Munich, Germany, March 10-14, 2008. ©1

272 M. Glaß, M. Lukasiewycz, F. Reimann, C. Haubelt and J. Teich. Symbolic Reliability Analysis and Optimization of ECU Networks. Proceedings of Design, Automation and Test in Europe (DATE 2008), IEEE Computer Society, pp. 158-163, Munich, Germany, March 10-14, 2008. ©1

271 M. Streubühr, M. Jäntsch, C. Haubelt, J. Teich and A. Schneider. Semi-Automatic Generation of mixed Hardware-Software Prototypes from Simulink Models. 11. GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Freiburg, Germany, pp. 139-148, March 03-05, 2008. ©1

270 F. Hannig, H. Ruckdeschel and J. Teich. The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications. In Proceedings of the GI/ITG/GMM-Workshop - Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, pp. 129-138, Freiburg, Germany, March 3-5, 2008. ©1

269 J. Gladigau, F. Blendinger, C. Haubelt and J. Teich. Symbolische Modellprüfung Aktor-orientierter High-level SystemC-Modelle mit Intervalldiagrammen. 11. GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Freiburg, Germany, pp. 109-118, March 03-05, 2008. ©1

268 T. Streichert, C. Haubelt, D. Koch and J. Teich. Concepts for Self-Adaptive and Self-Healing Networked Embedded Systems. Organic Computing, Rolf Würtz (Ed.), Springer Series Understanding Complex Systems, pp. 241-260, Springer, 2008. ©1

267 J. Keinert, C. Haubelt and J. Teich. Synthesis of Multi-Dimensional High-Speed FIFOs for Out-of-Order Communication. Proceedings of the International Conference on Architecture of Computing Systems (ARCS 2008), pp. 130-143, Dresden, Germany, February 25-28, 2008. ©1

266 R. Brendle, T. Streichert, D. Koch, C. Haubelt and J. Teich. Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks. Proceedings of the International Conference on Architecture of Computing Systems (ARCS 2008), pp. 117-129, Dresden, Germany, February 25-28, 2008. ©1

265 T. Streichert, M. Glaß, R. Wanka, C. Haubelt and J. Teich. Topology-Aware Replica Placement in Fault-Tolerant Embedded Networks. Proceedings of the International Conference on Architecture of Computing Systems (ARCS 2008), pp. 23-37, Dresden, Germany, February 25-28, 2008. ©1

264 S. Wildermann and J. Teich. 3D Person Tracking with a Color-Based Particle Filter. G. Sommer and R. Klette (Eds.): RobVis 2008, LNCS 4931, pp. 327–340, Springer-Verlag Berlin Heidelberg, 2008. ©1

263 F. Hannig, H. Dutta, H. Ruckdeschel and J. Teich. Quantitative Evaluation of Behavioral Synthesis Approaches for Reconfigurable Devices. In Proceedings of the 2nd HiPEAC Workshop on Reconfigurable Computing (WRC), pp. 73-82, Gothenburg, Sweden, January 27, 2008. ©1

262 M. Lukasiewycz, M. Glaß, C. Haubelt and J. Teich. Efficient Symbolic Multi–Objective Design Space Exploration. In Proceedings of the 13th Asia and South Pacific Design Automation Conference (ASP-DAC 2008), pp. 691-696, Seoul, Korea. ©1

2007

261 D. Koch, C. Beckhoff and J. Teich. Bitstream Decompression for High Speed FPGA Configuration from Slow Memories. In Proceedings of the IEEE International Conference on Field-Programmable Technology 2007 (ICFPT'07), pp. 161-168. ©1

260 J. Keinert, J. Falk, C. Haubelt and J. Teich. Actor-Oriented Modeling and Simulation of Sliding Window Image Processing Algorithms. Proceedings of the 2007 IEEE/ACM/IFIP Workshop of Embedded Systems for Real-Time Multimedia (ESTIMEDIA 2007), pp. 113-118, Salzburg, Oct. 4-5, 2007. ©1

259 T. Streichert, M. Glaß, C. Haubelt and J. Teich. Design space exploration of reliable networked embedded systems. In Journal on Systems Architecture (JSA). Volume 53(10): 751-763, 2007. ©1

258 M. Lukasiewycz, M. Glaß, C. Haubelt and J. Teich. SAT-Decoding in Evolutionary Algorithms for Discrete Constrained Optimization Problems. In Proceedings of the 2007 IEEE Congress on Evolutionary Computation (CEC 2007), Singapore, Singapore, pp. 935-942, September 25-28, 2007. ©1

257 D. Ziener and J. Teich. Watermarking Apparatus, Software Enabling an Implementation of an Electronic Circuit Comprising a Watermark, Method for Detecting a Watermark and Apparatus for Detecting a Watermark. US-Patent US2007/0220263, Anmeldetag 19.10.2006 aus EP 1835425, veröffentlicht 20.09.2007, Patentklassen (IPC) H04L 9/00. ©1

256 D. Ziener and J. Teich. Watermarking apparatus, software enabling an implementation of an electronic circuit comprising a watermark, method for detecting a watermark and apparatus for detecting a watermark. Europäisches Patent EP1835425, Anmeldetag 17.03.2006, veröffentlicht 19.09.2007, Patentklassen (IPC) G06F 17/50; G06F 21/00. ©1

255 J. Gladigau, C. Haubelt, B. Niemann and J. Teich. Mapping Actor-Oriented Models to TLM Architectures. In Proceedings FDL'07, Forum on specification and Design Languages 2007, Barcelona, Spain, September 18-20, 2007. ©1

254 D. Koch, T. Streichert, C. Haubelt and J. Teich. Efficient Reconfigurable On-Chip Buses. Europäisches Patent EP07017975, Anmeldetag 13.09.2007. ©1

253 J. Teich. Reconfigurable Computing Systems. it - Information Technology, http://it-information-technology.de, Oldenbourg Wissenschaftsverlag, vol. 49(3):139-142, 2007. ©1

252 B. Niemann, C. Haubelt, M. Uribe and J. Teich. Formalizing TLM with Communicating State Machines. In Advances in Design and Specification Languages for Embedded Systems, pp. 225-242, Springer, 2007. ©1

251 J. Keinert, C. Haubelt and J. Teich. Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow. In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, Acoustics, Speech, and Signal Processing (IC-SAMOS VII), Samos (Greece) July 16-19, 2007. ©1

250 H. Dutta, F. Hannig, A. Kupriyanov, D. Kissler, J. Teich, R. Schaffer, S. Siegel, R. Merker and B. Pottier. Massively Parallel Processor Architectures: A Co-design Approach. Proceedings of the 3rd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC), pp. 61-68, Montpellier, France, June 18-20, 2007. ©1

249 J. Teich, F. Hannig, H. Ruckdeschel, H. Dutta, D. Kissler and A. Stravet. A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Invited paper, pp. 14-24, Las Vegas, NV, USA, June 25-28, 2007. ©1

248 W. Stechele, O. Bringmann, R. Ernst, A. Herkersdorf, K. Hojenski, P. Janacik, F. Rammig, J. Teich, N. Wehn, J. Zeppenfeld and D. Ziener. Concepts for Autonomic Integrated Systems. In Proceedings of edaWorkshop07, Hannover, Germany, June 19-20, 2007. ©1

247 H. Dutta, F. Hannig, H. Ruckdeschel and J. Teich. Efficient Control Generation for Mapping Nested Loop Programs onto Processor Arrays. In Journal of Systems Architecture, 53(5-6):300-309, 2007. ©1

246 M. Lukasiewycz, M. Glaß, C. Haubelt and J. Teich. Solving Multiobjective Pseudo-Boolean Problems. In Proceedings of Tenth International Conference on Theory and Applications of Satisfiability Testing (SAT 2007), Lisbon, Portugal, pp. 56-69, May 28-31, 2007. ©1

245 D. Koch, C. Haubelt, T. Streichert and J. Teich. Modeling and Synthesis of Hardware-Software Morphing. In Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), pp. 2746-2749, New Orleans, LA, U.S.A., May 2007. ©1

244 D. Kissler, F. Hannig and J. Teich. Schwach-programmiert macht stark. Design&Elektronik, April 2007, pp. 34-39, WEKA Fachzeitschriften-Verlag GmbH. ©1

243 A. Kupriyanov, D. Kissler, F. Hannig and J. Teich. Efficient Event-driven Simulation of Parallel Processor Architectures. In Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems (SCOPES), Nice, France, pp. 71-80, April 20, 2007. ©1

242 M. Glaß, M. Lukasiewycz, T. Streichert, C. Haubelt and J. Teich. Reliability-Aware System Synthesis. In Proceedings of Design, Automation and Test in Europe (DATE 2007), IEEE Computer Society, Nice, France, pp. 409-414, April 16-20, 2007. ©1

241 T. Streichert, C. Strengert, D. Koch, C. Haubelt and J. Teich. Communication Aware Optimization of the Task Binding in Hardware/Software Reconfigurable Networks. Journal on Integrated Circuits and Systems, Volume 2, Number 1, pp. 29-36, March 2007. ©1

240 M. Glaß, M. Lukasiewycz, T. Streichert, C. Haubelt and J. Teich. Synthese zuverlässiger und flexibler Systeme. In Proceedings of Zuverlässigkeit und Entwurf (ZuD 2007), Munich, Germany, pp. 141-148, March 26-28, 2007. ©1

239 W. Stechele, O. Bringmann, R. Ernst, A. Herkersdorf, K. Hojenski, P. Janacik, F. Rammig, J. Teich, N. Wehn, J. Zeppenfeld and D. Ziener. Autonomic MPSoCs for Reliable Systems. In Proceedings of Zuverlässigkeit und Entwurf (ZuD 2007), pp. 137-138, Munich, Germany, March 26-28, 2007. ©1

238 S. Fekete, J. van der Veen, J. Angermeier, D. Göhringer, M. Majer and J. Teich. Scheduling and communication-aware mapping of HW-SW modules for dynamically and partially reconfigurable SoC architectures. In Proceedings of the Dynamically Reconfigurable Systems Workshop (DRS 2007), Zürich, Switzerland, pages 151-160, March 15, 2007. ©1

237 J. Angermeier, D. Göhringer, M. Majer and J. Teich. The Erlangen Slot Machine: A flexible FPGA-platform for partially reconfigurable applications at run-time. Tutorial, 20th International Conference on Architecture of Computing Systems (ARCS 2007), Springer LNCS series, Swiss Federal Institute of Technology (ETH) Zurich, Switzerland, March 12-15, 2007. ©1

236 A. Kupriyanov, F. Hannig, D. Kissler, J. Teich, J. Lallet, O. Sentieys and S. Pillement. Modeling of Interconnection Networks in Massively Parallel Processor Architectures. In Proceedings of the 20th International Conference on Architecture of Computing Systems (ARCS 2007), Springer LNCS series, Swiss Federal Institute of Technology (ETH), Zurich, Switzerland, pp. 268-282, March 12-15, 2007. ©1

235 M. Lukasiewycz, M. Glaß, C. Haubelt and J. Teich. Symbolic Archive Representation for a Fast Nondominance Test. In Proceedings of the Fourth International Conference on Evolutionary Multi-Criterion Optimization (EMO 2007), Sendai, Japan, pp. 111-125, March 5-8, 2007. ©1

234 M. Streubühr, C. Riedel, C. Haubelt and J. Teich. System Level Modeling and Performance Simulation for Dynamic Reconfigurable Computing Systems in SystemC. 10. Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen", Erlangen, Germany, pp. 59-68, March 05-07, 2007. ©1

233 J. Teich and C. Haubelt. Digitale Hardware/Software-Systeme: Synthese und Optimierung. 2. Auflage, Springer-Verlag, Berlin Heidelberg, 2007. ©1

232 M. Majer, J. Teich, A. Ahmadinia and C. Bobda. The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-Based Computer. Journal of VLSI Signal Processing Systems, Springer, vol. 47(1), pages 15-31, March 2007. ©1

231 C. Haubelt, J. Falk, J. Keinert, T. Schlichter, M. Streubühr, A. Deyhle, A. Hadert and J. Teich. A SystemC-based Design Methodology for Digital Signal Processing Systems. In EURASIP Journal on Embedded Systems, Special Issue on Embedded Digital Signal Processing Systems, Volume 2007 (2007), Article ID 47580, 22 pages, March 2007. ©1

230 C. Haubelt and J. Teich. Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen. Shaker Verlag, Aachen, Germany, 2007. ©1

229 D. Koch, C. Haubelt and J. Teich. Efficient Hardware Checkpointing -- Concepts, Overhead Analysis, and Implementation. In Proceedings of the 15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2007), Monterey, CA, pp. 188-196, February 18-20, 2007. Download demo video. ©1

228 N. Bergmann, M. Platzner and J. Teich. Dynamically Reconfigurable Architectures. EURASIP Journal of Embedded Systems, Volume 2007 (2007), Article ID 28405, 2 pages, February 2007. ©1

227 J. Angermeier, D. Göhringer, M. Majer, J. Teich, S. Fekete and J. van der Veen. The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Reconfigurable Computing. it - Information Technology, http://it-information-technology.de, Oldenbourg Wissenschaftsverlag, vol. 49(3):143-148, 2007. ©1

226 J. Teich. Evaluation and Optimization of Reliability of Embedded Systems during Design Space Exploration. Dagstuhl Seminar No. 07101, Quantitative Aspects of Embedded Systems, IBFI, March 5-9, 2007. ©1

225 A. Ahmadinia, C. Bobda, S. Fekete, J. Teich and J. van der Veen. Optimal free-space management and routing-conscious dynamic placement for reconfigurable computing. IEEE Transactions on Computers, volume 56, number 3, pages 673-680, 2007. ©1

2006

224 D. Kissler, F. Hannig, A. Kupriyanov and J. Teich. A Highly Parameterizable Parallel Processor Array Architecture. In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT 2006), pp. 105-112, Bangkok, Thailand, December 13-15, 2006. ©1

223 D. Ziener and J. Teich. FPGA Core Watermarking Based on Power Signature Analysis. In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2006), pp. 205-212, Bangkok, Thailand, December 13-15, 2006. ©1

222 J. Falk, J. Gladigau, C. Haubelt and J. Teich. SysteMoC - Verification and Refinement of Actor-Based Models of Computation. Talk, ARTIST2 Workshop on MoCC - Models of Computation and Communication, November 16-17, Zurich, Switzerland, 2006. ©1

221 D. Kissler, F. Hannig, A. Kupriyanov and J. Teich. Hardware Cost Analysis for Weakly Programmable Processor Arrays. In Proceedings of the International Symposium on System-on-Chip (SoC), pp. 179-182, Tampere, Finland, November 14-16, 2006. ©1

220 S. Siegel, R. Merker, F. Hannig and J. Teich. Communication-conscious Mapping of Regular Nested Loop Programs onto Massively Parallel Processor Arrays. In Proceedings of the 18th International Conference on Parallel and Distributed Computing and Systems (PDCS), pp. 71-76, Dallas, TX, USA, November 13-15, 2006. ©1

219 J. Teich. Are Current ESL Tools Meeting the Requirements of Advanced Embedded Systems?. In Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), p. 166, Seoul, Korea, October 22-25, 2006. ©1

218 T. Streichert, D. Koch, C. Haubelt and J. Teich. Modeling and Design of Fault-Tolerant and Self-Adaptive Reconfigurable Networked Embedded Systems. EURASIP Journal on Embedded Systems, Volume 2006 (2006), Article ID 42168, 15 pages, Hindawi Publishing Corporation. ©1

217 J. Falk, C. Haubelt and J. Teich. Efficient Representation and Simulation of Model-Based Designs in SystemC. In Proceedings FDL'06, Forum on Design Languages 2006, Darmstadt, Germany, September 19-22, pp. 129 - 134, 2006. ©1

216 H. Dutta, F. Hannig and J. Teich. Hierarchical Partitioning for Piecewise Linear Algorithms. In Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering (PARELEC), pp. 153-159, Bialystok, Poland, September 13-17, 2006. ©1

215 H. Dutta, F. Hannig, J. Teich, B. Heigl and H. Hornegger. A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. In Proceedings of IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 331-337, Steamboat Springs, CO, USA, September 11-13, 2006. ©1

214 T. Streichert, C. Strengert, C. Haubelt and J. Teich. Dynamic Task Binding for Hardware/Software Reconfigurable Networks . In Proceedings of SBCCI 2006, pages 38-43, Ouro Preto, Brasil, August 28th - September 1st, 2006. ©1

213 J. Teich, S. Kaxiras, T. Plaks and K. Flautner. Topic 18: Embedded Parallel Systems. In Proceedings of12th International Euro-Par Conference, p. 1179, Dresden, Germany, August 28-September 1, 2006. ©1

212 D. Ziener, S. Aßmus and J. Teich. Identifying FPGA IP-Cores based on Lookup Table Content Analysis. In Proceedings of 16th International Conference on Field Programmable Logic and Applications, Madrid, Spain, pp. 481-486, August 28-30, 2006. ©1

211 S. Fekete, J. van der Veen, M. Majer and J. Teich. Minimizing communication cost for reconfigurable slot modules. In Proceedings 16th International Conference on Field-Programmable Logic and Applications (FPL 2006), pp. 535-540, Madrid, Spain, August 28-30, 2006. ©1

210 A. Kupriyanov, F. Hannig, D. Kissler, J. Teich, J. Lallet, O. Sentieys and S. Pillement. Modeling of Interconnection Networks in Massively Parallel Processor Architectures. Technical Report 05-2006, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, August 2006. ©1

209 S. Fekete, E. Köhler and J. Teich. Higher-dimensional packing with order constraints. SIAM Journal on Discrete Mathematics,Vol. 20, No. 4, pp. 1056-1078, 2006. ©1

208 T. Streichert, C. Haubelt and J. Teich. Multi-Objective Topology Optimization for Networked Embedded Systems. In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2006), pp. 93--98, Samos (Greece), July 17-20, 2006.. ©1

207 D. Kissler, F. Hannig, A. Kupriyanov and J. Teich. A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. In Proceedings of the 2nd International Workshop on Reconfigurable Communication-Centric System-on-Chips (ReCoSoC), pp. 31-37, France, July 3-5, 2006. ©1

206 D. Göhringer, M. Majer and J. Teich. Bridging the Gap between Relocation and Available Technology: The Erlangen Slot Machine. In Proceedings of the Dagstuhl Seminar Nº 06141 on Dynamically Reconfigurable Architectures, P. M. Athanas, J. Becker, G. Brebner, J. Teich (Eds.), ISSN 1862 - 4405, Dagstuhl, Germany, April 02-07, 2006. ©1

205 D. Koch, M. Körber and J. Teich. Searching RC5-Keys with Distributed Reconfigurable Computing. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA 2006), Las Vegas, USA, June 26-29, 2006. ©1

204 D. Kissler, A. Kupriyanov, F. Hannig, D. Koch and J. Teich. A Generic Framework for Rapid Prototyping of System-on-Chip Designs. In Proceedings of the International Conference on Computer Design (CDES), pp. 189-195, Las Vegas, NV, USA, June 2006. ©1

203 F. Hannig, H. Dutta and J. Teich. Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays: Architectural Parameters and Methodology. In International Journal of Embedded Systems, Vol. 2, Nos. 1/2, pp. 114-127, 2006. ©1

202 C. Haubelt, T. Schlichter and J. Teich. Improving Automatic Design Space Exploration by Integrating Symbolic Techniques into Multi-Objective Evolutionary Algorithms. In International Journal of Computational Intelligence Research (IJCIR), Special Issue on Multiobjective Optimization and Applications, Volume 2, Issue 3. pp. 239-254, 2006. ©1

201 A. Ahmadinia, C. Bobda and J. Teich. Online Placement for Dynamically Reconfigurable Devices. Int. J. Embedded Systems, Vol. 1, Nos. 3/4, pp.165-178, 2006. ©1

200 J. Keinert, C. Haubelt and J. Teich. Modeling and Analysis of Windowed Synchronous Algorithms. In Proceedings of the 31st International Conference on Acoustics, Speech, and Signal Processing (ICASSP2006), Toulouse (France) May 14-19, 2006. ©1

199 H. Dutta, F. Hannig and J. Teich. A Formal Methodology for Hierarchical Partitioning of Piecewise Linear Algorithms. Technical Report 04-2006, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, April 2006. ©1

198 J. Becker, J. Teich, P. Athanas and G. Brebner. Dynamically Reconfigurable Architectures. Proceedings of the Dagstuhl Seminar Nº 06141, ISSN 1862 - 4405, Dagstuhl, Germany, April 02-07, 2006. ©1

197 A. Kupriyanov, F. Hannig, D. Kissler, R. Schaffer and J. Teich. MAML - An Architecture Description Language for Modeling and Simulation of Processor Array Architectures, Part I. Technical Report 03-2006, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, March 2006. ©1

196 D. Koch, T. Streichert, S. Dittrich, C. Strengert, C. Haubelt and J. Teich. An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks. In Proceedings of the 19th International Conference on Architecture of Computing Systems (ARCS 2006), Frankfurt/Main, Germany, pp. 202-216, March 13-16, 2006. ©1

195 H. Dutta, F. Hannig and J. Teich. Controller Synthesis for Mapping Partitioned Programs on Array Architectures. In Proceedings of the 19th International Conference on Architecture of Computing Systems (ARCS), Frankfurt/Main, Germany, pp. 176-191, March 13-16, 2006. ©1

194 C. Bobda, M. Platzner and J. Teich. The Renaissance of FPGA-Based High-Performance Computing. DATE'06 Friday Workshop, Conference Design Automation and Test in Europe, March 10, 2006, Munich, Germany. ©1

193 J. Teich, C. Haubelt, D. Koch and T. Streichert. Concepts for Self-Adaptive Automotive Control Architectures. DATE'06 Friday Workshop Future Trends in Automotive Electronics and Tool Integration, Conference Design Automation and Test in Europe, March 10, 2006, Munich, Germany. ©1

192 M. Streubühr, J. Falk, C. Haubelt, J. Teich, R. Dorsch and T. Schlipf. Task-Accurate Performance Modeling in SystemC for Real-Time Multi-Processor Architectures. In Proceedings of Design, Automation and Test in Europe (DATE 2006), IEEE Computer Society, Munich, Germany, pp. 480-481, March 6-10, 2006. ©1

191 T. Schlichter, M. Lukasiewycz, C. Haubelt and J. Teich. Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms. In Proceedings of IEEE Computer Society Annual Symposium on VLSI. Karlsruhe, Germany, pp. 309-314, March 2-3, 2006. ©1

190 A. Kupriyanov, F. Hannig, D. Kissler, J. Teich, R. Schaffer and R. Merker. An Architecture Description Language for Massively Parallel Processor Architectures. In Proceedings of the 9th ITG/GMM/GI Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Dresden, Germany, pp. 11-20, February 20-22, 2006. ©1

189 H. Dutta, F. Hannig and J. Teich. Mapping of Nested Loop Programs onto Massively Parallel Processor Arrays with Memory and I/O Constraints. In Friedhelm Meyer auf der Heide and Burkhard Monien, editors, Proceedings of the 6th International Heinz Nixdorf Symposium, New Trends in Parallel & Distributed Computing, volume 181 of HNI-Verlagsschriftenreihe, pp. 97-119, Paderborn, Germany, January 17-18, 2006. ©1

188 J. Teich. Timing Analysis of Systems of Communicating Tasks with Internal State. Technical Report 01-2006, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, January 2006. ©1

187 J. Teich. Stochastic Timing Analysis of Communicating Tasks with Internal State. Technical Report 02-2006, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, January 2006. ©1

2005

186 J. Falk, C. Haubelt and J. Teich. Syntax and execution behavior of SysteMoC. Technical Report 04-2005, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, December 2005. ©1

185 A. Ahmadinia, C. Bobda, T. Haller, A. Linarth, M. Majer and J. Teich. Increasing the Flexibility in FPGA-Based Reconfigurable Platforms: The Erlangen Slot Machine. In Proc. IEEE 2005 Conference on Field-Programmable Technology (FPT), Singapore, Singapore, pages 37-42, December 11-14, 2005. ©1

184 H. Dutta, F. Hannig and J. Teich. Control Path Generation for Mapping Partitioned Dataflow-dominant Algorithms onto Array Architectures. Technical Report 03-2005, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, November 2005. ©1

183 J. Keinert, C. Haubelt and J. Teich. Windowed Synchronous Data Flow. Department of Computer Science 12, Hardware-Software-Co-Design, University of Erlangen-Nuremberg, Am Weichselgarten 3, D-91058 Erlangen, Germany Co-Design-Report 02-2005. ©1

182 A. Ahmadinia, C. Bobda, J. Ding, M. Majer and J. Teich. Modular Video Streaming on a Reconfigurable Platform. In Proc. IFIP VLSI SOC 2005, pages 103-108, Perth, Australia, pp. 103-108, October 17-19, 2005. ©1

181 C. Haubelt, M. Jersak, K. Richter, K. Strehl, D. Ziegenbein, R. Ernst, J. Teich and L. Thiele. SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme. In Proceedings of INFORMATIK 2005 - Informatik LIVE. by Armin B. Cremers, Rainer Manthey, Peter Martini, and Volker Steinhage (Eds.). In Lecture Notes in Informatics. VOL. P-68, No. 2, Bonn, Germany, pp. 693-697, September 19-22, 2005. © Gesellschaft für Informatik, Bonn, Germany, 2005. ©1

180 S. Helwig, C. Haubelt and J. Teich. Modeling and Analysis of Indirect Communication in Particle Swarm Optimization. In Proceedings of the 2005 IEEE Congress on Evolutionary Computation, volume 2, pages 1246-1253, Edinburgh, UK, September 2nd-5th, 2005. ©1

179 A. Ahmadinia, C. Bobda, S. Fekete, M. Majer, J. Teich and J. van der Veen. DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL),Tampere, Finland, pp. 153-158, August 24-26, 2005. ©1

178 T. Schlichter, C. Haubelt, F. Hannig and J. Teich. Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems. In Proceedings of Application-specific Systems, Architectures and Processors (ASAP). Samos, Greece, pp. 9-14, July 23-25, 2005. ©1

177 H. Ruckdeschel, H. Dutta, F. Hannig and J. Teich. Automatic FIR Filter Generation for FPGAs. In Proceedings of the International Workshop on Embedded Computer Systems, Architectures, Modeling, and Simulation (SAMOS), Samos, Greece, pp. 51-61, July 18-20, 2005. ©1

176 F. Hannig and J. Teich. Output Serialization for FPGA-based and Coarse-grained Processor Arrays. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, USA, pp. 78-84, June 27-30, 2005. ©1

175 F. Hannig, H. Dutta, A. Kupriyanov, J. Teich, R. Schaffer, S. Siegel, R. Merker, R. Keryell, B. Pottier and D. Chillet, D. Ménard, O. Sentieys. Co-Design of Massively Parallel Embedded Processor Architectures. In Proceedings of the first ReCoSoC Workshop. Montpellier, France, June 27-29, 2005. ©1

174 A. Ahmadinia, C. Bobda, S. Fekete, F. Hannig, M. Majer, J. Teich and J. van der Veen. Defragmenting the Module Layout of a Partially Reconfigurable Device. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, USA, pp. 92-101, June 27-30, 2005. ©1

173 T. Schlichter, C. Haubelt and J. Teich. Improving EA-based Design Space Exploration by Utilizing Symbolic Feasibility Tests. In Proceedings of Genetic and Evolutionary Computation Conference (GECCO). Washington, DC, pp. 1945-1952, June 25-29, 2005. ©1

172 A. Ahmadinia, C. Bobda, J. Ding, S. Fekete, M. Majer, J. Teich and J. van der Veen. A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices. In Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping, Montreal, Canada, pp. 84-90, June 8-10, 2005. ©1

171 S. Mostaghim and J. Teich. Quad-trees: A Data structure for storing Pareto-sets in Multi-objective Evolutionary Algorithms with Elitism. In Ajith Abraham and Lakhmi Jain and Robert Goldberg (eds.), Evolutionary Multiobjective Optimization, Theoretical Advances and Applications. Springer Advanced Information and Knowledge Processing Series, London, pp. 81-104, 2005. ©1

170 A. Ahmadinia, C. Bobda, S. Fekete, T. Haller, A. Linarth, M. Majer, J. Teich and J. van der Veen. The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform. In Proceedings of the 2005 IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, USA, pp. 319-320, April 17-20, 2005. ©1

169 T. Dinkel, C. Haubelt, U. Heinkel, J. Knäblein, T. Schlichter, S. Schock and J. Teich. Comparison of Techniques for the Automatic Verification of ADeVA Specifications. In Dresdener Arbeitstagung Schaltungs- und Systementwurf (DASS 2005). Dresden, Germany, April 13-14, 2005. ©1

168 J. Falk, C. Haubelt and J. Teich. Representing Models of Computation in SystemC. GI/ITG/GMM-Workshop 2005, Munich, Germany, April 06-07, 2005. ©1

167 T. Dinkel, C. Haubelt, U. Heinkel, T. Schlichter and J. Teich. Automatische Verification von ADeVA-Spezifikationen. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen. GI/ITG/GMM-Workshop 2005, Munich, Germany, April 06-07, 2005. ©1

166 A. Ahmadinia, C. Bobda, M. Majer and J. Teich. Packet Routing in Dynamically Changing Networks on Chip. In Proceedings of the 12th Reconfigurable Architectures Workshop (RAW 2005), Denver, USA, p. 154b, IEEE Computer Society, April 4-5, 2005. ©1

165 J. Teich. Model-Based System-Level Design Using SystemC. Invited talk, Akademische Tage'05, IBM Forschungslaboratorium, March 18, 2005, Böblingen, Germany. ©1

164 J. Teich. The Future of Reconfigurable Computing. DATE'05 Friday Workshop, Conference Design Automation and Test in Europe, March 11, 2005, Munich, Germany. ©1

163 A. Ahmadinia, C. Bobda, T. Haller, A. Linarth, M. Majer and J. Teich. The Erlangen Slot Machine (ESM): A Flexible Platform for Dynamic Reconfigurable Computing. Board Demo at the University Booth at Design, Automation and Test in Europe (DATE 2005), Munich, Germany, March 7-11, 2005. ©1

162 C. Haubelt, J. Gamenik and J. Teich. Initial Population Construction for Convergence Improvement of MOEAs. In Evolutionary Multi-Criterion Optimization, Carlos A. Coello Coello, Arturo Hernández Aguirre, and Eckart Zitzler (eds.), Lecture Notes in Computer Science, Vol. 3410, pp. 191-205, Springer, Berlin, Heidelberg, New York, 2005. ©1

161 T. Streichert, C. Haubelt and J. Teich. Distributed HW/SW-Partitioning for Embedded Reconfigurable Systems. In Proceedings of DATE 2005, Munich, Germany, pp. 894-895, March 7-11, 2005. ©1

160 D. Ziener and J. Teich. Evaluation of Watermarking methods for FPGA-based IP-cores. Technical Report 01-2005, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, March 2005. ©1

159 T. Streichert, C. Haubelt and J. Teich. Verteilte HW/SW-Partitionierung für fehlertolerante rekonfigurierbare Netzwerke. In Proceedings of 17. ITG/GI/GMM Workshop für Testmethoden und Zuverlässigkeit und Fehlertoleranz von Schaltungen und Systemen. Innsbruck, Austria, pp. 50-54, February 27 - March 1, 2005. ©1

158 C. Haubelt, S. Otto, C. Grabbe and J. Teich. A System-Level Approach to Hardware Reconfigurable Systems. In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC'05). Shanghai, China, pp. 298-301, January 18-21, 2005. ©1

157 T. Streichert, C. Haubelt and J. Teich. Online Hardware/Software Partitioning in Networked Embedded Systems. In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC'05). Shanghai, China, pp. 982-985, January 18-21, 2005. ©1

2004

156 A. Ahmadinia, C. Bobda, H. Kalte, D. Koch and J. Teich. FPGA Architecture Extensions for Preemptive Multitasking and Hardware Defragmentation. In Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology (FPT), Brisbane, Australia, pp. 433-436, December 6-8, 2004. ©1

155 A. Ahmadinia, C. Bobda, J. Ding and J. Teich. Design and Implementation of Reconfigurable Multiple Bus on Chip (RMBoC). Technical Report 02-2004, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, November 2004. ©1

154 S. Mostaghim and J. Teich. Multi-Objective Particle Swarm Optimization. Dagstuhl Seminar No. 04461, Practical Approaches to Multi-Objective Optimization, IBFI, November 7 - 12, 2004. ©1

153 F. Hannig and J. Teich. Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. In Proceedings of the 15th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2004), pp. 17-27, Galveston, TX, USA, September 27-29, 2004. ©1

152 A. Kupriyanov, F. Hannig and J. Teich. Automatic and Optimized Generation of Compiled High-Speed RTL Simulators. In Proceedings of the Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES 2004). Washington, DC, U.S.A., September 22, 2004. ©1

151 F. Hannig and J. Teich. Dynamic Piecewise Linear/Regular Algorithms. In Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), pp. 79-84, Dresden, Germany, September 7-10, 2004. ©1

150 A. Ahmadinia, C. Bobda, D. Koch, M. Majer and J. Teich. Task Scheduling for Heterogeneous Reconfigurable Computers. In Proceedings of the 17th Symposium on Integrated Circuits and Systems Design (SBCCI), Pernambuco, Brazil, pp. 22-27, ACM Press, September 7-11, 2004. ©1

149 A. Ahmadinia, C. Bobda, D. Koch, M. Majer and J. Teich. A Dynamic NoC Approach for Communication in Reconfigurable Devices. In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL), Antwerp, Belgium, LNCS 3203, pp. 1032-1036, Springer, August 30 - September 1, 2004. ©1

148 A. Ahmadinia, C. Bobda, S. Fekete, J. Teich and J. van der Veen. Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices. In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL), Antwerp, Belgium, LNCS 3203, pp. 847-851, Springer, August 30 - September 01, 2004. ©1

147 C. Haubelt, D. Koch and J. Teich. Basic OS Support for Distributed Reconfigurable Hardware. In Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04), Samos, Greece, July 19-21, published as Springer Lecture Notes in Computer Science (LNCS), volume 3133, pages 30-38, 2004. ©1

146 N. Bambha, S. Bhattacharyya, J. Teich and E. Zitzler. Systematic Integration of Parameterized Local Search Into Evolutionary Algorithms. IEEE Transactions on Evolutionary Computation, vol. 8, no. 2, pages 137-155, April 2004. ©1

145 S. Bhattacharyya and J. Teich. Analysis of Dataflow Programs with Interval-Limited Data-Rates. In Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04), Samos, Greece, July 19-21, published as Springer Lecture Notes in Computer Science (LNCS), volume 3133, pages 507-518, 2004. ©1

144 A. Kupriyanov, F. Hannig and J. Teich. High-Speed Event-Driven RTL Compiled Simulation. In Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04), Samos, Greece, July 19-21, published as Springer Lecture Notes in Computer Science (LNCS), volume 3133, pages 519-529, 2004. ©1

143 N. Bambha, S. Bhattacharyya, J. Teich and E. Zitzler. Systematic Integration of Parameterized Local Search Techniques in Evolutionary Algorithms. In Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '04), Part II, pp. 383-384, Seattle, U.S.A., June 26-30, 2004. ©1

142 T. Frauenheim, M. Hoffman, P. Koenig, S. Mostaghim and J. Teich. Molecular Force Field Parameterization using Multi-Objective Evolutionary Algorithms. In Proceedings of the Congress on Evolutionary Computation (CEC '04), pp. 212-219, Portland, U.S.A., June 20-23, 2004. ©1

141 S. Mostaghim and J. Teich. Covering Pareto-optimal Fronts by Subswarms in Multi-objective Particle Swarm Optimization. In Proceedings of the Congress on Evolutionary Computation (CEC '04), pp. 1404-1411, Portland, U.S.A., June 20-23, 2004. ©1

140 F. Hannig and J. Teich. Resource Constrained and Speculative Scheduling of Dynamic Piecewise Regular Algorithms. Technical Report 01-2004, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, June 2004. ©1

139 F. Hannig, H. Dutta and J. Teich. Regular Mapping for Coarse-grained Reconfigurable Architectures. In Proceedings of the 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2004), Vol. V, pp. 57-60, Montréal, Quebec, Canada, May 17-21, 2004. ©1

138 A. Ahmadinia, M. Bednara, C. Bobda and J. Teich. A New Approach for On-line Placement on Reconfigurable Devices. In Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), Santa Fe, NM, U.S.A., April 26-30, 2004. ©1

137 F. Hannig, H. Dutta and J. Teich. Mapping of Regular Nested Loop Programs to Coarse-grained Reconfigurable Arrays -- Constraints and Methodology. In Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), Santa Fe, NM, USA, April 26-30, 2004. ©1

136 C. Haubelt and J. Teich. Modeling and Analysis of Distributed Reconfigurable Hardware. In Dresdener Arbeitstagung Schaltungs- und Systementwurf (DASS 2004), pp. 106-111, Dresden, Germany, April 19-20, 2004. ©1

135 D. Koch and J. Teich. Platform-Independent Methodology for Partial Reconfiguration. Proceedings of the 2004 ACM conference Computing Frontiers (CF 04), pp. 398-403, April 14-16, 2004, Ischia, Italy. ©1

134 A. Ahmadinia, C. Bobda, K. Danne and J. Teich. Generation of Distributed Arithmetic Designs for Reconfigurable Applications. In Proc. GI/ITG Dynamically Reconfigurable Systems Workshop at ARCS - Organic and Pervasive Computing, Augsburg, Germany, pp. 205-214, March 26, 2004. ©1

133 A. Ahmadinia, C. Bobda and J. Teich. A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware. In Proc. 17th International Conference on Architecture of Computing Systems (ARCS 2004), Augsburg, Germany, LNCS 2981, pp. 125-139, Springer, March 23-26, 2004. ©1

132 F. Hannig and J. Teich. Energy Estimation and Optimization for Piecewise Regular Processor Arrays. In Shuvra S. Bhattacharyya, Ed F. Deprettere and Jürgen Teich (eds.). Chapter 6 in Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation, pages 107-126. Number 20 in Signal Processing and Communication Series, Marcel Dekker, New York, U.S.A., 2004. ©1

2003

131 A. Ahmadinia, C. Bobda, K. Danne and J. Teich. A New Approach for Reconfigurable Massively Parallel Computers. In Proceedings of the IEEE International Conference on Field-Programmable Technology, Tokyo, Japan, pp. 391-394, December 15-17, 2003. ©1

130 A. Ahmadinia, C. Bobda and J. Teich. Temporal Task Clustering for Online Placement on Reconfigurable Hardware. In Proceedings of the IEEE International Conference on Field-Programmable Technology, Tokyo, Japan, pp. 359-362, December 15-17, 2003. ©1

129 A. Ahmadinia and J. Teich. Speeding up Online Placement for XILINX FPGAs by Reducing Configuration Overhead . In Proceedings of the IFIP International Conference on VLSI-SOC, Darmstadt, Germany, pp. 118-122, December 1-3, 2003. ©1

128 C. Haubelt and J. Teich. Accelerating Design Space Exploration. In Proceedings of 5th International Conference on ASIC (ASICON 2003), pp. 79-84, Beijing, China, October 21-24, 2003. ©1

127 P. Kralicek, C. Reinhold and J. Teich. Synthesizing Passive Networks by applying Genetic Programming and Evolution Strategies. In Proceedings of the Congress on Evolutionary Computation (CEC'03), pp. 1740-1747, Canberra, Australia, December 8-12, 2003. ©1

126 S. Mostaghim and J. Teich. The role of e-dominance in Multi-Objective Particle Swarm Optimization Methods. In Proceedings of the Congress on Evolutionary Computation (CEC'03), pp.1764-1771, Canberra, Australia, December 8-12, 2003 . ©1

125 C. Haubelt, D. Koch and J. Teich. ReCoNets: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware. In Proceedings of the 16th Symposium on Integrated Circuits and Systems Design (SBCCI2003), pp. 343-348, São Paulo, Brazil, September 8-11, 2003. ©1

124 R. Feldmann, C. Haubelt, B. Monien and J. Teich. Fault Tolerance Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques. In Proceedings of 13th International Conference on Field Programmable Logic and Applications, pp. 478-487, Lisbon, Portugal, September 1-3, 2003. ©1

123 C. Haubelt, D. Koch and J. Teich. Basic OS Support for Distributed Reconfigurable Hardware. In Proceedings of the Third International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'03), pp. 18-22, Samos, Greece, July 21-23, 2003, ISBN 90-807957-1-2. ©1

122 J. Teich. ReCoNets - Networks of Reconfigurable Nodes and Interconnect. Dagstuhl Seminar No. 03301, Dynamically Reconfigurable Architectures, IBFI, Germany, July 2003. ©1

121 M. Bednara, C. Grabbe, J. Shokrollahi, J. Teich and J. von zur Gathen. FPGA Designs of Parallel High Performance GF(2^233) Multipliers. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS-2003), pp. 268-271, Bangkok, Thailand, May 25-28, 2003. ©1

120 S. Mostaghim and J. Teich. Strategies for finding good local guides in multi-objective particle swarm optimization. In Proceedings of the Swarm Intelligence Symposium, pp. 26-33, Indianapolis, USA, April 24-26, 2003. ©1

119 M. Bednara, C. Grabbe, J. Shokrollahi, J. Teich and J. von zur Gathen. A High Performance VLIW Processor for Finite Field Arithmetic. In Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS-2003),p. 189, Nice, France, April 22-26, 2003. ©1

118 M. Bednara and J. Teich. Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms. Journal of Supercomputing, Vol. 26, No., 2, pp. 149-165, September 2003. ©1

117 D. Fischer, J. Teich, M. Thies and R. Weper. Buildabong: A Framework for Architecture/Compiler Co-Exploration . Journal of Circuits, Systems, and Computers, Vol. 12, No. 3, pp. 353-375, World Scientific Publishing Company, June 2003. ©1

116 M. Bednara, K. Danne, M. Deppe, F. Oberschelp, F. Slomka and J. Teich. Design and Implementation of Digital Linear Control Systems on Reconfigurable Hardware. EURASIP Journal of Applied Signal Processing, Vol. 2003, Number 6, pp. 1-9, Hindawi Publishing Corporation, 2003. ©1

115 M. Dellnitz, S. Mostaghim, O. Schütze and J. Teich. Covering Pareto Sets by Multilevel Evolutionary Subdivision Techniques. In Proceedings of the Second International Conference on Evolutionary Multi-Criterion Optimization (EMO), pp. 118-132, Faro, Portugal, April 8-11, 2003. ©1

114 J. Teich. Challenges and Potentials of Reconfigurable Computing. 6th German-American Frontiers of Engineering Symposium, Alexander von Humboldt-Foundation, U.S. National Academy of Engineering, Ludwigsburg, Germany, April 2003. ©1

113 C. Haubelt, S. Mostaghim, J. Teich and A. Tyagi. Solving Hierarchical Optimization Problems Using MOEAs. In Evolutionary Multi-Criterion Optimization, Carlos M. Fonseca, Peter J. Fleming, Eckart Zitzler, Kalyanmoy Deb, and Lothar Thiele (eds.), Lecture Notes in Computer Science, Vol. 2632, pp. 162-176, Springer, Berlin, Heidelberg, New York, 2003. ©1

112 C. Haubelt, S. Mostaghim, F. Slomka, J. Teich and A. Tyagi. Hierachical Synthesis of Embedded Systems Using Evolutionary Algorithms. In Evolutionary Algorithms in System Design by Drechsler, R. and Drechsler, N., in Genetic Algorithms and Evolutionary Computation (GENA), pp. 63-104, Kluwer Academic Publishers, Boston, Dordrecht, London, 2003. ©1

111 J. Gerling, G. Mrozynski, J. Schrage, O. Stuebbe and J. Teich. Improved time domain simulation of optical multimode intrasystem interconnects. In Proceedings of Design, Automation and Test in Europe (DATE 2003), Messe Munich, Germany, pp. 1110-1111, March 3-7, 2003. ©1

110 C. Haubelt, J. Teich, R. Feldmann and B. Monien. SAT-Based Techniques in System Synthesis. In Proceedings of Design, Automation and Test in Europe (DATE 2003), Norbert Wehn and Diederik Verkest, IEEE Computer Society, Munich, Germany, pp. 1168-1169, March 3-7, 2003. ©1

109 F. Slomka and J. Teich. A Model for Buffer Exploration in EDF Scheduled Embedded Systems. 11. EIS-Workshop, Entwurf Integrierter Schaltungen und Systeme, Erlangen, Germany. VDE/VDI-Gesellschaft Mikroelektronik, Mikro- und Feinwerktechnik (GMM), GMM-Fachbericht, pp. 91-96, VDE-Verlag, Berlin, März 2003. ©1

108 J. Teich. Entwurfsautomatisierung elektronischer Systeme auf Systemebene. 11. EIS-Workshop, Entwurf Integrierter Schaltungen und Systeme, VDE/VDI-Gesellschaft Mikroelektronik, Mikro- und Feinwerktechnik (GMM), GMM-Fachbericht, VDE-Verlag, Berlin, März 2003. ©1

107 S. Bhattacharyya, E. Deprettere and J. Teich. Domain-Specific Processors: Systems, Architectures, Modeling and Simulation. Marcel Dekker, Signal Processing and Communication Series, New York, USA, 2004. ©1

106 C. Haubelt and J. Teich. Accelerating Design Space Exploration Using Pareto-Front Arithmetics. In Proceedings ASP-DAC 2003, Asia and South Pacific Design Automation Conference, pp. 525-531, Kitakyushu, Japan, January 21-24, 2003. ©1

2002

105 D. Fischer, J. Teich, M. Thies and R. Weper. Efficient Architecture/Compiler Co-Exploration for ASIPs. In ACM SIG Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES2002), pp. 27-34, October 8-11, Grenoble, France. ©1

104 F. Hannig and J. Teich. Energy Estimation of Nested Loop Programs. Proceedings 14th Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA 2002), Winnipeg, Manitoba, Canada, August 10-13, 2002. ©1

103 F. Hannig and J. Teich. Energy Estimation for Piecewise Regular Processor Arrays. In Proceedings of the Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2002). Island of Samos, Greece, July 22-25, 2002. ©1

102 M. Bednara and J. Teich. Interface Synthesis for FPGA Based VLSI Processor Arrays. In Proc. of The International Conference on Engineering of Reconfigurable Sytsems and Algorithms (ERSA02), Las Vegas, Nevada, U.S.A., June 24-27, 2002 . ©1

101 M. Bednara, M. Daldrup, J. Shokrollahi, J. Teich and J. von zur Gathen. Tradeoff Analysis of FPGA Based Elliptic Curve Cryptography. In Proc. of IEEE International Symposium on Circuits and Systems (ISCAS-02). Scottsdale, Arizona, U.S.A., May 26-29 2002.. ©1

100 S. Mostaghim, J. Teich and A. Tyagi. Comparison of Data Structures for Storing Pareto-sets in MOEAs. In 2002 World Congress on Computational Intelligence (CEC02), pp. 843-849, May 2002. ©1

99 M. Bednara, M. Daldrup, J. Shokrollahi, J. Teich and J. von zur Gathen. Reconfigurable Implementation of Elliptic Curve Crypto Algorithms. In RAW2002- Proc. The 9th Reconfigurable Architectures Workshop, Fort Lauderdale, Florida, U.S.A., April 2002. ©1

98 C. Haubelt, J. Teich, K. Richter and R. Ernst. System Design for Flexibility. In Proc. DATE 2002, Design, Automation and Test in Europe, IEEE Computer Society Press, pp. 854-861, Paris, France, March 4-8, 2002. ©1

97 E. Deprettere, J. Teich and S. Vassiliadis. Embedded Processor Design Challenges, E. F. Deprettere, J. Teich, and S. Vassiliadis, editors. Lecture Notes in Computer Science (LNCS), Vol. 2268, Springer, Berlin, Germany, March 2002. ©1

96 J. Teich and L. Thiele. Exact Partitioning of Affine Dependence Algorithms. In Embedded Processor Design Challenges, E. Deprettere, J. Teich, and S. Vassiliadis, editors, Lecture Notes in Computer Science (LNCS), Vol. 2268, pp. 135-151, Springer, Berlin, Germany, March 2002. ©1

95 M. Köster and J. Teich. (Self-) reconfigurable Finite State Machines. In Proc. DATE 2002, Design, Automation and Test in Europe, IEEE Computer Society Press, Paris, France, March 4 -8, 2002. ©1

94 C. Haubelt, J. Teich, K. Richter and R. Ernst. Flexibility / Cost-Tradeoffs of Platform-Based Systems. In Embedded Processor Design Challenges, E. Deprettere, J. Teich, and S. Vassiliadis, editors, Lecture Notes in Computer Science (LNCS), Vol. 2268, pp. 38-56, Springer, Berlin, Germany, March 2002. ©1

93 M. Bednara, F. Hannig and J. Teich. Generation of Distributed Loop Control. In Embedded Processor Design Challenges, E. F. Deprettere, J. Teich, and S. Vassiliadis, editors, Lecture Notes in Computer Science (LNCS), Vol. 2268, pp. 154-170, Springer, Berlin, Germany, March 2002. ©1

92 C. Haubelt, J. Teich, K. Richter and R. Ernst. Modellierung Rekonfigurierbarer Systemarchitekturen. GI / ITG / GMM Workshop - Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Tuebingen, Germany, Shaker Verlag, pp. 163-171, February 25-27, 2002. ©1

91 R. Ernst, K. Richter, J. Teich, L. Thiele and D. Ziegenbein. SPI - A System Model for Heterogeneously Specified Embedded Systems. J. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 4, pp. 379-389, August 2002. ©1

2001

90 D. Fischer, U. Kastens, J. Teich, M. Thies and R. Weper. Design Space Characterization for Architecture/Compiler Co-Exploration. In ACM SIG Proceedings International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES 2001), pp. 108-115, Atlanta, Georgia, USA, November 2001. ©1

89 M. Bednara, F. Hannig and J. Teich. Boundary Control: A new Distributed Control Architecture for Space-Time Transformed (VLSI) Processor Arrays. Proc. 35th IEEE Asilomar Conf. on Signals, Systems and Computers, Pacific Grove,California, USA, November 2001. ©1

88 F. Hannig and J. Teich. Design Space Exploration for Massively Parallel Processor Arrays. In Proc. of the Sixth International Conference on Parallel Computing Technologies (PaCT-2001), Novosibirsk, Russia, September 3-7, 2001. ©1

87 S. Fekete, E. Köhler and J. Teich. Higher-Dimensional Packing with Order Constraints. Proc. 7th Workshop on Algorithms and Data Structures, Lecture Notes in Computer Science (LNCS), Vol. 2125, pp. 300-312, Springer, August 2001. ©1

86 R. Ernst, M. Gries, K. Strehl, J. Teich, L. Thiele and D. Ziegenbein. FunState - An Internal Design Representation for Codesign. J. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 4, pp. 524-544, August 2001. ©1

85 J. Teich. Symbiose von Hardware und Software. Hardware/Software Codesign, K. J. Buchenrieder, editor, IT Press, Bruchsal, pp. 79-107, July 2001. In Schriftenreihe Informationsverarbeitung und Technische Informatik. ©1

84 J. Teich. Exact Partitioning of Affine Dependence Algorithms. Proc. SAMOS - Systems, Architectures, Modeling and Simulation Workshop, Island of Samos, Greece, July 13-16, 2001. ©1

83 M. Bednara and J. Teich. Synthesis of FPGA Implementations from Loop Algorithms. In Proc. of the First International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA?01), pp. 1-7, Las Vegas, Nevada, U.S.A., June 25-28, 2001. ©1

82 S. Fekete, J. Schepers and J. Teich. Optimization of Dynamic Hardware Reconfigurations. The J. of Supercomputing, Kluwer Academic Publishers, Vol. 19, No. 1, pp. 57-75, May 2001. ©1

81 S. Bhattacharyya, J. Teich, E. Zitzler and N. Bambha. Hybrid Global/Local Search Strategies for Dynamic Voltage Scaling in Embedded Multiprocessors. Proc. 9th Int. Workshop on Hardware/Software Co-Design, Copenhagen, Denmark, pp. 243-248, April 25-27, 2001. ©1

80 J. Teich. Pareto-Front Exploration with Uncertain Objectives. Proc. First International Conference on Evolutionary Multi-Criterion Optimization, Zurich, Switzerland, March 7-9, 2001. In Lecture Notes in Computer Science (LNCS), Vol. 1993, pp. 314-328, Springer, 2001. ©1

79 D. Fischer, J. Teich and R. Weper. Hierarchical Modeling and Simulation of Embedded Processors Using ASMs. International Workshop on Software and Compilers for Embedded Systems, (SCOPES 2001), St.Goar, Germany, March 20-22, 2001. ©1

78 S. Fekete, E. Köhler and J. Teich. Optimal FPGA Module Placement with Temporal Precedence Constraints. In Proc. DATE 2001, Design, Automation and Test in Europe, Computer Society Press, Munich, Germany, pp. 658-665, March 13-16, 2001. ©1

77 M. Anlauff, D. Fischer, P. Kutter, J. Teich and R. Weper. Hierarchical Microprocessor Design Using XASM. In Proc. EUROCAST 2001, Las Palmas de Gran Canaria, Spain, pp. 271-274, February 19-23, 2001. ©1

76 M. Bednara, O. Beyer, J. Teich and R. Wanka. Hardware Supported Sorting: Design and Tradeoff Analysis. In System Design Automation, R. Merker and W. Schwarz, editors, Kluwer Academic Publishers, pp. 97-107, 2001. ©1

75 J. Teich. Synthesis and Optimization of Digital Hardware/Software Systems. In System Design Automation, R. Merker and W. Schwarz, editors, Kluwer Academic Publishers, pp. 3-26, 2001. ©1

74 S. Fekete, E. Köhler and J. Teich. Extending Partial Suborders. Electronic Notes in Discrete Mathematics, Hajo Broersma, Ulrich Faigle, Johann Hurink and Stefan Pickl, editors, Elsevier Science Publishers, Vol. 8, 2001. ©1

2000

73 K. Strehl, J. Teich and L. Thiele. Regular State Machines. J. Parallel Algorithms and Applications, Vol. 15, pp. 265-300, December 2000. ©1

72 D. Fischer, J. Teich, S. Trinkert and R. Weper. A Joined Architecture/Compiler Environment for ASIPs. ACM SIG Proc. International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES 2000). San Jose, CA, U.S.A., pp. 26 - 33, November 2000 . ©1

71 F. Cieslok, H. Esau and J. Teich. EXPLORA - Generic Design Space Exploration During Embedded System Synthesis. Proc. DIPES 2000, Int. IFIP Workshop on Distributed and Parallel Embedded Systems. Schloss Eringerfeld, Germany, October 2000. In Architecture and Design of Distributed Embedded Systems, B. Kleinjohann, editor, Kluwer Academic Publishers, pp. 215-225, June 2001. ©1

70 D. Fischer, J. Teich, S. Trinkert and R. Weper. BUILDABONG: A Rapid Prototyping Environment for ASIPs. Proc. DSP-Deutschland 2000, pp. 153-162, Munich, Germany. WEKA Fachzeitschriften Verlag, October 2000. ©1

69 P. Kutter, J. Teich and R. Weper. Description and Simulation of Microprocessor Instruction Sets Using ASMs. International Workshop on Abstract State Machines. Lecture Notes in Computer Science (LNCS) 1912, pp. 266-286, Springer-Verlag, October 2000. ©1

68 F. Cieslok, R. Ernst, M. Jersak, K. Richter, K. Strehl, J. Teich, L. Thiele, F. Wolf and D. Ziegenbein. Embedded System Design using the SPI Workbench. Proc. FDL'00, Forum on Design Languages 2000, Tübingen, Germany, September 2000. ©1

67 S. Bhattacharyya, J. Teich and E. Zitzler. Evolutionary Algorithms for the Synthesis of Embedded Software. J. IEEE Trans. on VLSI Systems, Vol. 8, No. 4, pp. 452-456, August 2000 . ©1

66 M. Bednara, O. Beyer, J. Teich and R. Wanka. Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter. Proc. ASAP'00, the Int. Conf. on Application Specific Systems, Architectures, and Processors, pp. 299-308, Boston, MA, U.S.A. IEEE Computer Society Press, July 2000. ©1

65 S. Bhattacharyya, J. Teich and E. Zitzler. Optimizing the Efficiency of Parameterized Local Search within Global Search:. Proc. of CEC'2000, the Int. Conf. on Evolutionary Computation, La Jolla, CA, U.S.A., pp. 365-372, July 2000. ©1

64 J. Teich. Embedded System Synthesis and Optimization. Invited paper, Proc. Workshop on System Design Automation - SDA 2000, pp. 9-22, Rathen, Germany. VDE-Verlag, March 2000. ©1

63 M. Bednara, W. Hardt, A. Rettberg and J. Teich. Automated Design Space Exploration on System Level for Embedded Systems. Proc. Ninth Annual International HDL Conference and Exhibition (HDL Conf. 2000), San Jose, CA, U.S.A., March 2000. ©1

62 M. Bednara, O. Beyer, J. Teich and R. Wanka. Hardware-Supported Sorting: Design and Tradeoff Analysis. Workshop on System Design Automation - SDA 2000, pp.37-44, Rathen, Germany. VDE-Verlag, March 2000. ©1

61 R. Ernst, K. Richter, J. Teich and D. Ziegenbein. SPI Workbench - Entwurf gemischt reaktiv/transformativer Systeme. AES 2000, Workshop Architekturentwurf für eingebettete Systeme, pp. 184-191, Karlsruhe, Germany, January 2000. ©1

60 P. Kutter, J. Teich and R. Weper. Description and Simulation of Microprocessor Instruction Sets Using ASMs. Proc. ASM 2000 Workshop, pp. 376-397, Monte Verita, Ascona, Switzerland, 2000. ©1

59 J. Teich. Symbiose von Hardware und Software. ForschungsForum 2000, No.2, pp. 82-87, Universität Paderborn, Germany, 2000. ©1

58 S. Bhattacharyya, J. Teich and E. Zitzler. Multidimensional Exploration of Software Implementations for DSP Algorithms. J. of VLSI Signal Processing Systems, Vol. 24, pp. 83-98, Kluwer Academic Publishers, 2000. ©1

1999

57 R. Ernst, K. Strehl, J. Teich, L. Thiele and D. Ziegenbein. FunState - An Internal Design Representation for Codesign. Proc. ICCAD'99, the IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 558-565, San Jose, CA, U.S.A., November 1999. ©1

56 S. Bhattacharyya, J. Teich and E. Zitzler. Optimized Software Synthesis for DSP Using Randomization Techniques. Technical Report No. 75, Computer Engineering and Communication Networks Lab (TIK), Swiss Federal Institute of Technology (ETH) Zurich, Gloriastrasse 35, CH-8092 Zurich, July 1999. ©1

55 S. Bhattacharyya, J. Teich and E. Zitzler. Evolutionary Algorithm Based Exploration of Software Schedules for Digital Signal Processors. Proc. GECCO'99, the Genetic and Evolutionary Computation Conference, pp. 1762-1769, Orlando, Florida, U.S.A., July 1999. ©1

54 S. Fekete, J. Schepers and J. Teich. Compile-Time Optimization of Dynamic Hardware Reconfigurations. Proc. Int. Conf. on Parallel and Distributed Processing Techniques and Applications (PDPTA'99), pp. 1097-1103, Las Vegas, Nevada, U.S.A., June 1999. ©1

53 R. Ernst, K. Richter, J. Teich, L. Thiele and D. Ziegenbein. Representation of Function Variants for Embedded System Optimization and Synthesis. Proc. 36th Design Automation Conference (DAC), pp. 517-522, New Orleans, U.S.A., June 1999. ©1

52 R. Ernst, K. Strehl, J. Teich, L. Thiele and D. Ziegenbein. Scheduling Hardware/Software Systems Using Symbolic Techniques. Proc. CODES'99, the 7th Int. Workshop on Hardware/Software Co-Design, pp. 173-177, Rome, Italy, May 1999. ©1

51 S. Bhattacharyya, J. Teich and E. Zitzler. 3D Exploration of Software Schedules for DSP Algorithms. Proc. CODES'99, the 7th Int. Workshop on Hardware/Software Co-Design, pp. 168-172, Rome, Italy, May 1999. ©1

50 S. Bhattacharyya, J. Teich and E. Zitzler. 3D Exploration of Uniprocessor Schedules for DSP ALgorithms. Technical Report No. 56, Computer Engineering and Communication Networks Lab (TIK), Swiss Federal Institute of Technology (ETH) Zurich, Gloriastrasse 35, CH-8092 Zurich, April 1999. ©1

49 R. Ernst, K. Richter, J. Teich, L. Thiele and D. Ziegenbein. SPI - An Internal Representation for Heterogeneously Specified Embedded Systems. Proc. GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, pp. 160-169, Braunschweig, Germany, February 1999. ©1

48 R. Ernst, K. Richter, J. Teich, L. Thiele and D. Ziegenbein. Hardware/Software Codesign of Embedded Systems - The SPI Workbench. Proc. Int. Workshop on VLSI, pp. 9-17, Orlando, Florida, U.S.A., 1999. ©1

1998

47 R. Ernst, K. Richter, J. Teich, L. Thiele and D. Ziegenbein. Representation of Process Mode Correlation for Scheduling. Proc. of ICCAD - the ACM/IEEE Int. Conf. on CAD, pp. 54-61, San Jose, CA, U.S.A., November 1998. ©1

46 S. Fekete, J. Schepers and J. Teich. Optimizing Dynamic Hardware Reconfigurations. Technical Report, Zentrum für Paralleles Rechnen, Universität zu Köln, Oktober 1998. ©1

45 S. Bhattacharyya, J. Teich and E. Zitzler. Optimized Software Synthesis for Digital Signal Processing Algorithms: An Evolutionary Approach. Proc. of the 1998 Workshop on Signal Processing Systems (SiPS), Boston, U.S.A., pp. 589-598, October 1998. ©1

44 S. Bhattacharyya, J. Teich and E. Zitzler. Optimized Software Synthesis for Digital Signal Processing Algorithms: An Evolutionary Approach. Proc. of the 1998 Workshop on Signal Processing Systems (SiPS), Boston, U.S.A., pp. 589-598, October 1998. ©1

43 S. Bhattacharyya, J. Teich and E. Zitzler. Buffer Memory Optimization in DSP Applications - An Evolutionary Approach. Parallel Problem Solving from Nature (PPSN'98), Amsterdam, The Netherlands, Springer Lecture Notes in Computer Science (LNCS) 1498, pp. 292-301, Springer-Verlag, September 1998. ©1

42 M. Eisenring and J. Teich. Interfacing Hardware and Software. Proc. of FPL'98, the Conf. on Field-Programmable Logic and Applications, Tallin, Estonia, Springer Lecture Notes in Computer Science (LNCS) 1482, pp. 520-524, Springer-Verlag, September 1998. ©1

41 J. Teich and L. Thiele. Regular State Machines. Presented at Workshop Seminar No. 98341, Tiling for Optimal Resource Utilization, Schloss Dagstuhl, Germany, August 1998. ©1

40 J. Teich and E. Zitzler. 3D Exploration of Uniprocessor Schedules for DSP Algorithms. Technical Report, Computer Engineering and Communication Networks Lab (TIK), Swiss Federal Institute of Technology (ETH) Zurich, Gloriastrasse 35, CH-8092 Zurich, August 1998. ©1

39 R. Esser, J. Teich and L. Thiele. CodeSign: An Embedded System Design Environment. IEE Proc. - Computers and Digital Techniques, 145(3):171-180, May 1998. ©1

38 M. Eisenring and J. Teich. Domain-Specific Interface Generation From Dataflow Specifications. Proc. of Codes/CASHE'98, the 6th Int. Workshop on Hardware/Software Co-design, Seattle, Washington, U.S.A., pp. 43-47, March 1998. ©1

37 R. Ernst, K. Richter, J. Teich, L. Thiele and D. Ziegenbein. Combining Multiple Models of Computation for Scheduling and Allocation. Proc. of Codes/CASHE\'98, the 6th Int. Workshop on Hardware/Software Codesign, Seattle, Washington, U.S.A., pp. 9-13, March 1998. ©1

36 M. Naedele, K. Strehl, J. Teich, L. Thiele and D. Ziegenbein. SCF - State Machine Controlled Flow Diagrams. Technical Report No. 33, Computer Engineering and Communication Networks Lab (TIK), Swiss Federal Institute of Technology (ETH) Zurich, Gloriastrasse 35, CH-8092 Zurich, January 1998. ©1

35 S. Bhattacharyya, J. Teich and E. Zitzler. Optimized Software Synthesis for Digital Processing Algorithms - An Evolutionary Approach. Technical Report No. 32, Computer Engineering and Communication Networks Lab (TIK), Swiss Federal Institute of Technology (ETH) Zurich, Gloriastrasse 35, CH-8092 Zurich, January 1998. ©1

34 M. Eisenring, J. Teich and L. Thiele. Rapid Prototyping of Dataflow Programs on Hardware/Software Architectures. In Proc. of HICSS'98, the Hawai'i Int. Conf. on Syst. Sci., Kona, Hawaii, U.S.A., pp. 187-196, January 1998. ©1

33 T. Blickle, J. Teich and L. Thiele. System-Level Synthesis Using Evolutionary Algorithms. J. Design Automation for Embedded Systems, Vol. 3, No. 1, pp. 23-58 , Kluwer Academic Publishers, January 1998. ©1

1997

32 J. Teich, L. Thiele and L. Zhang. Partitioning Processor Arrays under Resource Constraints. Int. Journal on VLSI and Signal Processing, Vol. 17, No. 1, pp. 5-20, September 1997. ©1

31 J. Fortes, T. Noll, V. Taylor, J. Teich, L. Thiele and K. Vissers. Proc. IEEE Int. Conference on Application Specific Systems, Architectures, and Processors (ASAP´97). IEEE Computer Society Press, Los Alamitos, July 1997. ©1

30 M. Martin, S. Sriram, J. Teich and L. Thiele. Performance Analysis of Mixed Asynchronous-Synchronous Systems. J. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 16, No. 5, pp. 473-484, May 1997. ©1

29 J. Teich. Hardware/Software-Codesign: Massgeschneiderte elektronische Systeme. Teil II: HW/SW-Synthese. J. SEV/VSE Bulletin, Vol. 3/97, pp. 17-22, March 1997. ©1

28 T. Blickle, J. Teich and L. Thiele. An Evolutionary Approach to System-Level Synthesis. Proc. of Codes/CASHE'97, the 5th Int. Workshop on Hardware/Software Co-design, Braunschweig, Germany, pp. 167-171, March 1997. ©1

27 J. Teich. Digitale Hardware/Software-Systeme: Synthese und Optimierung. Springer-Lehrbuch, Springer-Verlag, Berlin, 1997. ©1

1996

26 J. Teich. Hardware/Software-Codesign: Massgeschneiderte elektronische Systeme.Teil I: HW/SW-Architekturen und Spezifikation. J. SEV/VSE Bulletin, Vol. 25/96, pp. 17-23, December 1996. ©1

25 T. Blickle, J. Teich and L. Thiele. An evolutionary approach to system-level synthesis. Proc. of WSC1, the 1st Online Workshop on Soft Computing, pp. 251-256, Nagoya, Japan, August 1996. ©1

24 J. Teich, L. Thiele and L. Zhang. Scheduling of partitioned regular algorithms on processor arrays with constrained resources. In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP´96), pp. 131-144, Chicago, U.S.A., August 1996. ©1

23 J. Teich. Synthesis and Optimization of Digital Hardware/Software Systems. Habilitationsschrift, Computer Engineering and Communication Networks Lab (TIK), ETH Zurich, Switzerland, April 1996. ©1

22 J. Teich and L. Thiele. A new approach to solving resource-constrained scheduling problems based on a flow-model. Technical Report No. 17, Computer Engineering and Communication Networks Lab (TIK), Swiss Federal Institute of Technology (ETH) Zurich, Gloriastrasse 35, CH-8092 Zurich, March 1996. Presented at Workshop Dagstuhl Seminar No. 9617, Design Automation for Embedded Systems, Schloss Dagstuhl, Germany, April 1996 . ©1

21 T. Blickle, J. Teich and L. Thiele. System-level synthesis using evolutionary algorithms. Technical Report No. 16, Computer Engineering and Communication Networks Lab (TIK), Swiss Federal Institute of Technology (ETH) Zurich, Gloriastrasse 35, CH-8092 Zurich, March 1996. Presented at Workshop Dagstuhl Seminar No. 9613, Evolutionary Algorithms and their Application, Schloss Dagstuhl, Germany, March 1996. ©1

1995

20 E. Lee, J. Teich and L. Thiele. Simulation and modeling of heterogeneous systems modeled by deterministic discrete event systems. In 8th Int. Symposium on System Level Synthesis (ISSS´95), Cannes, France, pp. 156-161, October 1995. ©1

19 B. Evans, C. Schwarz, J. Teich and E. Welzl. On finding a minimal enclosing parallelogram. In Proc. 11th ACM Symposium on Computational Geometry, Vancouver, British Columbia, Canada, June 1995. ©1

1994

18 B. Evans, T. Kalker and J. Teich. Families of Smith Form Decompositions to simplify Multidimensional Filter Design. In Proc. IEEE Asilomar Conf. on Signals, Systems and Computers, pp. 498-501, Pacific Grove, CA, U.S.A., November 1994. ©1

17 M. Martin, S. Sriram, J. Teich and L. Thiele. Performance analysis and optimization of mixed asynchronous synchronous systems. Technical report, ERL Technical Report UCB/ERL No. 94/95, University of California, Berkeley, CA 94720, U.S.A., November 1994. ©1

16 B. Evans, C. Schwarz and J. Teich. Automateddesign of two-dimensional rational decimation systems. In Proc. IEEE Asilomar Conf. on Signals, Systems and Computers, pp. 363-367, Pacific Grove, CA, U.S.A., November 1994. ©1

15 M. Martin, S. Sriram, J. Teich and L. Thiele. Performance Analysis of Mixed Asynchronous-Synchronous Systems. In Proc. of the IEEE Int. Workshop on VLSI Signal Processing 94,pp. 103-112, Proceedings published as IEEE VLSI Signal Processing VII, October 1994. ©1

14 B. Evans, C. Schwarz, J. Teich and E. Welzl. On finding a minimal enclosing parallelogram. 4th MSI Workshop on Computational Geometry, Cornell University, Ithaca, NY, U.S.A., October 1994. ©1

13 B. Evans, C. Schwarz, J. Teich and E. Welzl. On finding a minimal enclosing parallelogram. Technical Report TR-94-036, ICSI - International Computer Science Institute, Berkeley, CA, U.S.A., 1994. ©1

1993

12 J. Teich. A Compiler for Application-Specific Processor Arrays. Doctoral thesis, Institut für Mikroelektronik, Universität des Saarlandes, Saarbrücken, Germany, September 1993. ©1

11 J. Teich, L. Thiele and L. Zhang. Minimal communication in massively parallel architectures. In Proc. of PARS Workshop 93, pp. 154-161, Dresden, Germany, April 1993. ©1

10 J. Teich. A Compiler for Application-Specific Processor Arrays. Shaker (Reihe Elektrotechnik), ISBN 3-86111-701-0, Aachen, Germany, 1993. ©1

9 J. Teich and L. Thiele. Partitioning of processor arrays: A piecewise regular approach. INTEGRATION: The VLSI Journal, 14(3):297-332, 1993. ©1

1992

8 J. Teich and L. Thiele. A transformative approach to the partitioning of processor arrays. In Proc. Int. Conf. on Application Specific Array Processors (ASAP´92), Berkeley, CA, U.S.A., pp. 4-20, IEEE Computer Society, August 1992. ©1

7 U. Arzt, J. Teich and L. Thiele. The concepts of COMPAR: A compiler for massive parallel architectures. In Proc. International Symposium on Circuits and Systems (ISCAS´92), pp. 681-684, San Diego, CA, U.S.A., May 1992. ©1

6 U. Arzt, J. Teich and L. Thiele. Hierarchical concepts in the design of processor arrays. In Proc. CompEuro 1992, pp. 232-238, The Hague, The Netherlands, May 1992. ©1

5 J. Teich and L. Thiele. Control generation in the design of processor array. In J.A Nossek, editor, Parallel Processing on VLSI Arrays, Kluwer Academic Publishers, 1992. ©1

1991

4 J. Teich and L. Thiele. Control generation in the design of processor arrays. Int. Journal on VLSI and Signal Processing, 3(2):77-92, 1991. ©1

3 J. Teich and L. Thiele. Uniform design of parallel programs for DSP. In Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), pages 344a-347a, Singapore, June 1991.. ©1

1990

2 J. Teich and L. Thiele. Systematic design concepts for signal processing arrays (invited paper). Frequenz /Journal of telecommunications, Vol. 44, pp. 122-132, May 1990. ©1

1 M. Huber, J. Teich and L. Thiele. Design of configurable processor arrays (invited paper). In Proc. IEEE Int. Symp. Circuits and Systems (ISCAS). ©1