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| 2012 | 7 M. Schmid, F. Hannig and J. Teich.
Power Management Strategies for Serial RapidIO Endpoints in FPGAs.
To appear in Proceedings of the 20th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM),Toronto, Canada, April 29 - May 2, 2012. ©1
 | | 2011 | 6 J. Wasza, S. Bauer, S. Haase, M. Schmid, S. Reichert and J. Hornegger.
RITK: The Range Imaging Toolkit – A Framework for 3-D Range Image Stream Processing.
In Proceeding of International Workshop on Vision, Modeling and Visualization (VMV), pp. 57-64, Berlin, Oct. 2011. ©1
| | 2010 | 5 F. Hannig, M. Schmid, J. Teich and H. Hornegger.
A Deeply Pipelined and Parallel Architecture for Denoising Medical Images.
In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT), pp. 485-490, Beijing, China, December 8-10, 2010. ©3
| 4 D. Ziener, M. Schmid and J. Teich.
Robustness Analysis of Watermark Verification Techniques for FPGA Netlist Cores.
In Design Methodologies for Secure Embedded Systems, A. Biedermann and H. Gregor Molter (Eds.), Lecture Notes in Electrical Engineering, volume 78, pp. 105-127, Springer-Verlag, Berlin Heidelberg, 2010. ©1
 | 3 H. Dutta, F. Hannig, M. Schmid and J. Keinert.
Modeling and Synthesis of Communication Subsystems for Loop Accelerator Pipelines.
In Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), pp. 125-132, Rennes, France, July 7-9, pages 125-132, 2010. ©2
| 2 M. Schmid, F. Hannig, J. Teich, R. Diefenbach, H. Pettendorf and H. Hornegger.
Discourse on Extending Embedded Medical Image Processing Systems Using the High Speed Serial RapidIO Interconnect.
Proceedings of the Embedded World Conference, Nuremberg, Germany, March 03-05, 2010. ©1
| | 2008 | 1 M. Schmid, D. Ziener and J. Teich.
Netlist-Level IP Protection by Watermarking for LUT-Based FPGAs.
In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2008), pp. 209-216, Taipei, Taiwan, December 08-10, 2008. ©1
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Massively Parallel VLSI Architectures, Project 
