Dipl.-Inf. Felix Reimann

Address:	Department of Computer Science 12 (Hardware-Software-Co-Design) University of Erlangen-Nuremberg Cauerstraße 11 D-91058 Erlangen Germany
Phone:	+49 9131 85-25157
Fax:	+49 9131 85-25149
Email:	felix.reimann@informatik.uni-erlangen.de
PGP/GPG-Key:	8E16CAB4

Curriculum vitae

February 5, 1982	born in Fürth, Germany
01/2008	Diploma degree in Computer Science, University of Erlangen-Nuremberg, Germany
02/2008	Researcher at the Department of Computer Science 12 (Hardware-Software-Co-Design), University of Erlangen-Nuremberg, Germany

Research Interests

Real-time networks esp. real-time Ethernet
System Level Design Space Exploration for Embedded Systems
Multi-Objective Optimization / Development of the Opt4J-Framework
Modeling and Analysis of Distributed Hardware Reconfigurable Systems
JReliability – The Java-based Reliability Library

Education

Nature-Inspired Optimization
Entwurf und Analyse eingebetteter Netzwerke des Automobilbaus
Hardware-Software-Co-Design
Ereignisgesteuerte Systeme

Open Theses:
— Parallelisierung eines Partikelschwarmoptimierers
— Partikelschwarmoptimierung für Diskrete Optimierungsprobleme
Supervised Theses:
— Christoph Strobl: Analyse echtzeitfähiger Ethernetvarianten, Studienarbeit 2009.
— Michael Eberl: Früzeitige Gültigkeitsüberprüfung in der SAT-Dekodierung, Diplomarbeit 2010.
— Christoph Strobl: Migrationsstrategien für Ethernet-basierte E/E-Architekturen, Diplomarbeit 2011.
— Sebastian Gruber: Entwicklung eines echtzeitfähigen Gateways zur Vermittlung zwischen CAN und Ethernet, Studienarbeit 2011.
— Fabian Streit: Echtzeitanalyse von Ethernet AVB, Bachelorarbeit 2012.

Publications

2012

13 M. Glaß, H. Yu, F. Reimann and J. Teich.
Cross-Level Compositional Reliability Analysis for Embedded Systems.
To appear in Proceedings of the 31th International Conference on Computer Safety, Reliability and Security (SAFECOMP 2012), Magdeburg, Germany, September 25-28, 2012. ©¹

2011

12 S. Wildermann, F. Reimann, J. Teich and Z. Salcic.
Operational Mode Exploration for Reconfigurable Systems with Multiple Applications.
Proceedings of the International Conference on Field-Programmable Technology (FPT'11), New Delhi, India. Dec. 12-14, 2011. ©¹

11 S. Wildermann, F. Reimann, D. Ziener and J. Teich.
Symbolic Design Space Exploration for Multi-Mode Reconfigurable Systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 129-138, Taipei, Taiwan. Oct. 9-14, 2011. (Best Paper Candidate). ©¹

10 M. Lukasiewycz, M. Glaß, F. Reimann and J. Teich.
Opt4J - A Modular Framework for Meta-heuristic Optimization.
Proceedings of the Genetic and Evolutionary Computing Conference (GECCO 2011), pp. 1723-1730, Dublin, Ireland, Jul. 12-16, 2011. ©¹

9 F. Reimann, M. Lukasiewycz, M. Glaß, C. Haubelt and J. Teich.
Symbolic System Synthesis in the Presence of Stringent Real-Time Constraints.
Proceedings of the 48th Design Automation Conference (DAC 2011), pp. 393-398, San Diego, USA, Jun. 5-10, 2011. ©¹

2010

8 M. Glaß, M. Lukasiewycz, F. Reimann, C. Haubelt and J. Teich.
Symbolic System Level Reliability Analysis.
In Proceedings of the International Conference on Computer-Aided Design (ICCAD), pp. 185-189, San Jose, USA, November 07-11, 2010. Tutorial Paper. ©¹

7 F. Reimann, M. Glaß, C. Haubelt, M. Eberl and J. Teich.
Improving Platform-Based System Synthesis by Satisfiability Modulo Theories Solving.
In Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 135-144, Scottsdale, USA. October 24-29 2010. ©³

6 F. Reimann, A. Kern, C. Haubelt, T. Streichert and J. Teich.
Echtzeitanalyse Ethernet-basierter E/E-Architekturen im Automobil.
In: GMM-Fachbericht -- Automotive meets Electronics (AmE 2010), (64), 2010, p. 9–14. ©¹

5 D. Koch, T. Streichert, C. Haubelt, F. Reimann and J. Teich.
ReCoNets – Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections.
In Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications, p. 223-244, Springer, Heidelberg, February 2010. 10.1007/978-90-481-3485-4_11. ©¹

2008

4 F. Reimann, M. Glaß, M. Lukasiewycz, J. Keinert, C. Haubelt and J. Teich.
Symbolic Voter Placement for Dependability-Aware System Synthesis.
In Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 237-242, Atlanta, GA USA, October 19-24 2008. ©¹

3 M. Glaß, M. Lukasiewycz, F. Reimann, C. Haubelt and J. Teich.
Symbolic Reliability Analysis of Self-healing Networked Embedded Systems.
In Proceedings of the 27th International Conference on Computer Safety, Reliability and Security (SAFECOMP 2008), pp. 139-152, Newcastle upon Tyne, UK, September 22-25, 2008. ©¹

2 M. Glaß, M. Lukasiewycz, F. Reimann, C. Haubelt and J. Teich.
Symbolic Reliability Analysis and Optimization of ECU Networks.
Proceedings of Design, Automation and Test in Europe (DATE 2008), IEEE Computer Society, pp. 158-163, Munich, Germany, March 10-14, 2008. ©¹

2006

1 F. Reimann.
Reconfigurable Computing Architectures.
In Proceedings of the 1st Chinese-German Summer School. Shanghai, China, pp. 477-483, September 18-28, 2006. ©¹

Misc.

2012

3 F. Reimann, S. Graf, M. Glaß and J. Teich.
Design Space Exploration for Modern Automotive Ethernet-based E/E Architectures.
University Booth at Design, Automation and Test in Europe (DATE 2012), Dresden, Germany, March 13-15, 2012. ©¹

2010

2 F. Reimann and M. Glaß.
Timing Analysis for Real-Time Ethernet Variants in ECU Network Design.
Talk at the 4th Symtavision News Conference, Braunschweig, Germany, September 29-30,2010. ©¹

2009

1 M. Glaß, M. Lukasiewycz, F. Reimann, M. Streubühr, J. Keinert, C. Haubelt and J. Teich.
Dependability-Aware System Synthesis: SystemCoDesigner, OPT4J and JRELIABILITY.
University Booth at Design, Automation and Test in Europe (DATE 2009), Nice, France, April 20-24, 2009. ©¹

Thesis

2008

2 F. Reimann.
Einsatz symbolischer Techniken zur Synthese fehlertolerierender eingebetteter Systeme.
Diplomarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Januar 2008. ©¹

2006

1 F. Reimann.
Entwurf und Implementierung eines Reconfigurable Multiple Bus für die Erlangen Slot Machine.
Studienarbeit, Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Oktober 2006. ©¹

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