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Curriculum Vitae
| 1999-2003 |
B.E in Electrical and Electronics Engineering, Osmania University,India |
| 2003-2005 |
M.Tech in Microelectronics and VLSI design, IIT Madras, India |
| 11/2004 to 06/2005 |
Intern Engineer, Redpine Signals Inc, Hyderabad, India |
| 06/2005 to 06/2011 |
ASIC Design Lead, Open-Silicon Inc, Bangalore, India |
Research Interests
| Invasive Computing, Computer Architecture, Low-Power and Fault-Tolerant VLSI System Design, 3D ICs |
| Currently i am working on B2 and Z2 sub-projects of InvasIC, which deals with the design of area and power optimized tightly-coupled processor arrays and building a demonstrator platform using Synoposys-CHIPit System for the InvasIC |
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