All Publications
72
inproceedings
Arifin Farhadur, Richard Membarth, Amouri Abdulazim, Frank Hannig, and Jürgen Teich.
FSM-Controlled Architectures for Linear Invasion.
To appear in Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC),
Florianópolis, Brazil, October 12-14, 2009.
[Further information][BibTeX]
71
inproceedings
Vahid Lari, Frank Hannig, and Jürgen Teich.
System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance.
To appear in Proceedings of the 4th International Symposium on Embedded Multicore Systems-on-Chip (MCSoC),
Vienna, Austria, September 22-25, 2009.
[Further information][BibTeX]
70
inproceedings
Richard Membarth, Frank Hannig, Hritam Dutta, and Jürgen Teich.
Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors.
To appear in Proceedings of the 9th International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS),
Island of Samos, Greece, July 20-23, 2009.
[Further information][BibTeX]
69
inproceedings
Richard Membarth, Frank Hannig, Hritam Dutta, and Jürgen Teich.
Optimization Flow for Algorithm Mapping on Graphics Cards.
To appear in Proceedings of ACACES 2009 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems,
Terrassa, Spain, July 12-18, 2009.
[Further information][BibTeX]
68
inproceedings
Hritam Dutta, Jiali Zhai, Frank Hannig, and Jürgen Teich.
Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines.
To appear in Proceedings of 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP),
Boston, MA, USA, July 7-9, 2009.
[Further information][BibTeX]
67
inproceedings
Richard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig, and Jürgen Teich.
Acceleration of Multiresolution Imaging Algorithms: A Comparative Study.
To appear in Proceedings of 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP),
Boston, MA, USA, July 7-9, 2009.
[Further information][BibTeX]
66
inproceedings
Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, and Jürgen Teich.
Model-Based Synthesis and Optimization of Static Multi-Rate Image Processing Algorithms.
In Proceedings of the Conference on Design, Automation and Test in Europe (DATE),
pp. 135-140, Nice, France, April 20-24, 2009.
[Further information][BibTeX]
65
article
Dmitrij Kissler, Andreas Strawetz, Frank Hannig, and Jürgen Teich.
Power-efficient Reconfiguration Control in Coarse-grained Dynamically Reconfigurable Architectures.
Journal of Low Power Electronics,
5(1):96-105, 2009.
[Further information][Digital object identifier][BibTeX]
64
inproceedings
Frank Hannig, Hritam Dutta, and Jürgen Teich.
Parallelization Approaches for Hardware Accelerators - Loop Unrolling versus Loop Partitioning.
In Proceedings of the 22nd International Conference on Architecture of Computing Systems (ARCS),
Delft, The Netherlands, March 10-13, 2009,
volume 5455 of Lecture Notes in Computer Science (LNCS), pp. 16-27, Springer, 2009.
[Further information][BibTeX]
63
inproceedings
Hritam Dutta, Frank Hannig, and Jürgen Teich.
Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis.
In Proceedings of the 22nd International Conference on Architecture of Computing Systems (ARCS),
Delft, The Netherlands, March 10-13, 2009,
volume 5455 of Lecture Notes in Computer Science (LNCS), pp. 233-245, Springer, 2009.
[Further information][BibTeX]
62
article
Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, and Bernard Pottier.
A Holistic Approach for Tightly Coupled Reconfigurable Parallel Processors.
Microprocessors and Microsystems,
33(1):53-62, 2009.
[Further information][Digital object identifier][BibTeX]
61
unpublished
Frank Hannig.
Power-Efficient Design of Tightly Coupled Parallel Processors with Dynamic Reconfiguration Capabilities.
Talk, HiPEAC Cluster Meeting, Paris, France, November 27-28, 2008.
[Further information][BibTeX]
60
inproceedings
Dmitrij Kissler, Andreas Strawetz, Frank Hannig, and Jürgen Teich.
Power-efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures.
In Proceedings of the 18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS),
Lisbon, Portugal, September 10-12, 2008,
volume 5349 of Lecture Notes in Computer Science (LNCS), pp. 307-317, Springer, 2008.
[Further information][Digital object identifier][BibTeX]
59
inproceedings
Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, and Frank Hannig.
Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures.
In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL),
pp. 391-396, Heidelberg, Germany, September 8-10, 2008.
[Further information][Digital object identifier][BibTeX]
58
inproceedings
Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, and Manfred Glesner.
SPP1148 Booth: Coarse-Grained Reconfiguration.
In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL),
pp. 349, Heidelberg, Germany, September 8-10, 2008.
[Further information][Digital object identifier][BibTeX]
57
inproceedings
Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, and Frank Hannig.
Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures.
In Proceedings of the 11th Euromicro Conference on Digital System Design (DSD),
pp. 345-352, Parma, Italy, September 3-5, 2008.
[Further information][Digital object identifier][BibTeX]
56
inproceedings
Rainer Schaffer, Renate Merker, Frank Hannig, and Jürgen Teich.
Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism.
In Proceedings of the 11th Euromicro Conference on Digital System Design (DSD),
pp. 391-398, Parma, Italy, September 3-5, 2008.
[Further information][Digital object identifier][BibTeX]
55
inproceedings
Hritam Dutta, Frank Hannig, and Jürgen Teich.
PARO: A Design Tool for Automatic Generation of Hardware Accelerators.
In Proceedings of ACACES 2008 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems,
pp. 317-320, L'Aquila, Italy, July 13-19, 2008.
[Further information][BibTeX]
54
inbook
Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, and Jürgen Teich.
Processor Description Languages,
chapter 12, MAML: An ADL for Designing Single and Multiprocessor Architectures,
pp. 295-327. In Systems on Silicon, Morgan Kaufmann, 2008.
[Further information][BibTeX]
53
inproceedings
Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, and Frank Hannig.
Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures.
In Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM),
pp. 306-309, Palo Alto, CA, USA, April 14-15, 2008.
[Further information][BibTeX]
52
inproceedings
Frank Hannig, Holger Ruckdeschel, Hritam Dutta, and Jürgen Teich.
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications.
In Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing (ARC),
London, United Kingdom, March 26-28, 2008,
volume 4943 of Lecture Notes in Computer Science (LNCS), pp. 287-293, Springer, 2008.
[Further information][PDF][BibTeX]
51
unpublished
Hritam Dutta, Frank Hannig, and Jürgen Teich.
The PARO Design Tool for Automatic Generation of Hardware Accelerators.
Interactive Presentation at Friday Workshop, The New Wave of the High-Level Synthesis, Design, Automation and Test in Europe (DATE), Munich, Germany, March 10-14, 2008.
[Further information][BibTeX]
50
unpublished
Jürgen Teich, Frank Hannig, Hritam Dutta, Dmitrij Kissler, and Matthias Hartl.
Domain-specific Reconfigurable MPSoC-Systems - Challenges and Trends.
Talk at Friday Workshop, Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures, Design, Automation and Test in Europe (DATE), Munich, Germany, March 10-14, 2008.
[Further information][BibTeX]
49
unpublished
Dmitrij Kissler, Hritam Dutta, Alexey Kupriyanov, Frank Hannig, and Jürgen Teich.
A High-Speed Dynamic Reconfigurable Multilevel Parallel Architecture.
Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), Munich, Germany, March 10-14, 2008.
[Further information][BibTeX]
48
inproceedings
Frank Hannig, Holger Ruckdeschel, and Jürgen Teich.
The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications.
In Proceedings of the GI/ITG/GMM-Workshop - Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen,
pp. 129-138, Freiburg, Germany, March 3-5, 2008.
[Further information][PDF][BibTeX]
47
inproceedings
Frank Hannig, Hritam Dutta, Holger Ruckdeschel, and Jürgen Teich.
Quantitative Evaluation of Behavioral Synthesis Approaches for Reconfigurable Devices.
In Proceedings of the 2nd HiPEAC Workshop on Reconfigurable Computing (WRC),
pp. 73-82, Gothenburg, Sweden, January 27, 2008.
[Further information][PDF][BibTeX]
46
unpublished
Frank Hannig.
Reconfigurable Computing Activities at University of Erlangen-Nuremberg, Hardware/Software Co-Design.
Talk, HiPEAC Cluster Meeting, Cambridge, United Kingdom, November 26-28 , 2007.
[Further information][BibTeX]
45
unpublished
Frank Hannig.
A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays - Case Study and Quantitative Evaluation.
Talk, Dagstuhl Seminar No. 07361, Programming Models for Ubiquitous Parallelism, Wadern, Germany, September 2-7, 2007.
[Further information][BibTeX]
44
inproceedings
Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, and Andrej Stravet.
A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation.
In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Invited paper,
pp. 14-24, Las Vegas, NV, USA, June 25-28, 2007.
[Further information][BibTeX]
43
inproceedings
Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, and Bernard Pottier.
Massively Parallel Processor Architectures: A Co-design Approach.
In Proceedings of the 3rd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC),
pp. 61-68, Montpellier, France, June 18-20, 2007.
[Further information][BibTeX]
41
inproceedings
Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, and Jürgen Teich.
Efficient Event-driven Simulation of Parallel Processor Architectures.
In Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems (SCOPES),
pp. 71-80, Nice, France, April 20, 2007.
[Further information][Digital object identifier][BibTeX]
40
article
Dmitrij Kissler, Frank Hannig, and Jürgen Teich.
Schwach programmiert macht stark - Massiv parallele Prozessorfelder.
Design&Elektronik,
(4):34-39, 2007.
[Further information][PDF][BibTeX]
39
inproceedings
Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, and Sébastien Pillement.
Modeling of Interconnection Networks in Massively Parallel Processor Architectures.
In Paul Lukowicz, Lothar Thiele, and Gerhard Tröster, editors, Proceedings of the 20th International Conference on Architecture of Computing Systems (ARCS),
Zurich, Switzerland, March 12-15, 2007,
In Lecture Notes in Computer Science (LNCS), pp. 268-282, Springer, 2007.
[Further information][Digital object identifier][BibTeX]
38
inproceedings
Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, and Jürgen Teich.
A Highly Parameterizable Parallel Processor Array Architecture.
In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT),
pp. 105-112, Bangkok, Thailand, December 13-15, 2006.
[Further information][Digital object identifier][BibTeX]
37
inproceedings
Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, and Jürgen Teich.
Hardware Cost Analysis for Weakly Programmable Processor Arrays.
In Proceedings of the International Symposium on System-on-Chip (SoC),
pp. 179-182, Tampere, Finland, November 14-16, 2006.
[Further information][Digital object identifier][BibTeX]
36
inproceedings
Sebastian Siegel, Renate Merker, Frank Hannig, and Jürgen Teich.
Communication-conscious Mapping of Regular Nested Loop Programs onto Massively Parallel Processor Arrays.
In Proceedings of the 18th International Conference on Parallel and Distributed Computing and Systems (PDCS),
pp. 71-76, Dallas, TX, USA, November 13-15, 2006.
[Further information][BibTeX]
35
inproceedings
Hritam Dutta, Frank Hannig, and Jürgen Teich.
Hierarchical Partitioning for Piecewise Linear Algorithms.
In Proceedings of the 5th International Conference on Parallel Computing in Electrical Engineering (PARELEC),
pp. 153-160, Bialystok, Poland, September 13-17, 2006.
[Further information][Digital object identifier][BibTeX]
34
inproceedings
Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, and Heinz Hornegger.
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing.
In Proceedings of IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors (ASAP),
pp. 331-337, Steamboat Springs, CO, USA, September 11-13, 2006.
[Further information][Digital object identifier][BibTeX]
33
techreport
Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, and Sébastien Pillement.
Modeling of Interconnection Networks in Massively Parallel Processor Architectures.
Technical Report 05-2006, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, August, 2006.
[Further information][BibTeX]
32
inproceedings
Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, and Jürgen Teich.
A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template.
In Proceedings of the 2nd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC),
pp. 31-37, Montpellier, France, July 3-5, 2006.
[Further information][BibTeX]
31
inproceedings
Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, and Jürgen Teich.
A Generic Framework for Rapid Prototyping of System-on-Chip Designs.
In Proceedings of International Conference on Computer Design (CDES),
pp. 189-195, Las Vegas, NV, USA, June 26-29, 2006.
[Further information][BibTeX]
30
article
Frank Hannig, Hritam Dutta, and Jürgen Teich.
Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays: Architectural Parameters and Methodology.
International Journal of Embedded Systems,
2(1/2):114-127, 2006.
[Further information][Digital object identifier][BibTeX]
29
techreport
Hritam Dutta, Frank Hannig, and Jürgen Teich.
A Formal Methodology for Hierarchical Partitioning of Piecewise Linear Algorithms.
Technical Report 04-2006, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, April, 2006.
[Further information][BibTeX]
28
techreport
Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Rainer Schaffer, and Jürgen Teich.
MAML - An Architecture Description Language for Modeling and Simulation of Processor Array Architectures, Part I.
Technical Report 03-2006, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, March, 2006.
[Further information][BibTeX]
27
inproceedings
Hritam Dutta, Frank Hannig, and Jürgen Teich.
Controller Synthesis for Mapping Partitioned Programs on Array Architectures.
In Werner Grass, Bernhard Sick, and Klaus Waldschmidt, editors, Proceedings of the 19th International Conference on Architecture of Computing Systems (ARCS),
Frankfurt am Main, Germany, March 13-16, 2006,
volume 3894 of Lecture Notes in Computer Science (LNCS), pp. 176-191, Springer, 2006.
[Further information][Digital object identifier][BibTeX]
26
inproceedings
Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, and Renate Merker.
An Architecture Description Language for Massively Parallel Processor Architectures.
In Proceedings of the GI/ITG/GMM-Workshop - Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen,
pp. 11-20, Dresden, Germany, February, 2006.
[Further information][BibTeX]
25
inproceedings
Hritam Dutta, Frank Hannig, and Jürgen Teich.
Mapping of Nested Loop Programs onto Massively Parallel Processor Arrays with Memory and I/O Constraints.
In Friedhelm Meyer auf der Heide and Burkhard Monien, editors, Proceedings of the 6th International Heinz Nixdorf Symposium, New Trends in Parallel & Distributed Computing,
Paderborn, Germany, January 17-18, 2006,
volume 181 of HNI-Verlagsschriftenreihe, pp. 97-119, Heinz Nixdorf Institut, Universit{\"a}t Paderborn, 2006.
[Further information][BibTeX]
24
techreport
Hritam Dutta, Frank Hannig, and Jürgen Teich.
Controller Synthesis for Mapping Partitioned Programs on Array Architectures.
Technical Report 03-2005, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, November, 2005.
[Further information][BibTeX]
23
inproceedings
Thomas Schlichter, Christian Haubelt, Frank Hannig, and Jürgen Teich.
Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems.
In Proceedings of the 16th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP),
pp. 9-14, Island of Samos, Greece, July 23-25, 2005.
[Further information][Digital object identifier][BibTeX]
22
inproceedings
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, and Jürgen Teich.
Automatic FIR Filter Generation for FPGAs.
In Timo D. Hämäläinen, Andy D. Pimentel, Jarmo Takala, and Stamatis Vassiliadis, editors, Embedded Computer Systems: Architectures, Modeling, and Simulation, 5th International Workshop, SAMOS, Proceedings,
Island of Samos, Greece, July 18-20, 2005,
volume 3553 of Lecture Notes in Computer Science (LNCS), pp. 51-61, Springer, 2005.
[Further information][Digital object identifier][PDF][BibTeX]
21
inproceedings
Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, and Olivier Sentieys.
Co-Design of Massively Parallel Embedded Processor Architectures.
In Proceedings of the first International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC),
pp. 27-34, Montpellier, France, June 27-29, 2005.
[Further information][PDF][BibTeX]
20
inproceedings
Frank Hannig and Jürgen Teich.
Output Serialization for FPGA-based and Coarse-grained Processor Arrays.
In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA),
pp. 78-84, Las Vegas, NV, USA, June 27-30, 2005.
[Further information][PDF][BibTeX]
19
inproceedings
Jan van der Veen, Sándor Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, and Jürgen Teich.
Defragmenting the Module Layout of a Partially Reconfigurable Device.
In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA),
pp. 92-101, Las Vegas, NV, USA, June 27-30, 2005.
[Further information][BibTeX]
18
unpublished
Frank Hannig.
Architektur und Compiler Co-Design.
Talk, DFG SPP 1148 Workshop, Blaubeuren, Germany, October 4, 2004.
[Further information][BibTeX]
17
inproceedings
Frank Hannig and Jürgen Teich.
Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals.
In Proceedings of the 15th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP),
pp. 17-27, Galveston, TX, USA, September 27-29, 2004.
[Further information][Digital object identifier][PDF][BibTeX]
16
inproceedings
Alexey Kupriyanov, Frank Hannig, and Jürgen Teich.
Automatic and Optimized Generation of Compiled High-Speed RTL Simulators.
In Proceedings of Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES),
Washington, DC, USA, September 22, 2004.
[Further information][PDF][BibTeX]
15
inproceedings
Frank Hannig and Jürgen Teich.
Dynamic Piecewise Linear/Regular Algorithms.
In Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC),
pp. 79-84, Dresden, Germany, September 7-10, 2004.
[Further information][Digital object identifier][PDF][BibTeX]
14
inproceedings
Alexey Kupriyanov, Frank Hannig, and Jürgen Teich.
High-Speed Event-Driven RTL Compiled Simulation.
In Andy D. Pimentel and Stamatis Vassiliadis, editors, Computer Systems: Architectures, Modeling, and Simulation, 4th International Samos Workshop (SAMOS), Proceedings,
Island of Samos, Greece, July 19-21, 2004,
volume 3133 of Lecture Notes in Computer Science (LNCS), pp. 519-529, Springer, 2004.
[Further information][Digital object identifier][PDF][BibTeX]
13
techreport
Frank Hannig and Jürgen Teich.
Resource Constrained and Speculative Scheduling of Dynamic Piecewise Regular Algorithms.
Technical Report 01-2004, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, 91058 Erlangen, Germany, June, 2004.
[Further information][PDF][BibTeX]
12
inproceedings
Frank Hannig, Hritam Dutta, and Jürgen Teich.
Regular Mapping for Coarse-grained Reconfigurable Architectures.
In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP),
volume V, pp. 57-60, Montréal, Quebec, Canada, May 17-21, 2004.
[Further information][Digital object identifier][PDF][BibTeX]
11
inproceedings
Frank Hannig, Hritam Dutta, and Jürgen Teich.
Mapping of Regular Nested Loop Programs to Coarse-grained Reconfigurable Arrays - Constraints and Methodology.
In Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS),
Santa Fe, NM, USA, April 26-30, 2004.
[Further information][Digital object identifier][PDF][BibTeX]
10
unpublished
Alexey Kupriyanov, Frank Hannig, Jürgen Teich, Dirk Fischer, Michael Thies, and Ralph Weper.
ArchitectureComposer.
CAD Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), Paris, France, February 16-20, 2004.
[Further information][BibTeX]
9
unpublished
Frank Hannig.
Mapping of Regular Algorithms to Massively Parallel Architectures.
Invited talk, Department of System Simulation, University Erlangen-Nuremberg, Germany, February 12, 2004.
[Further information][BibTeX]
8
inbook
Frank Hannig and Jürgen Teich.
Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation,
chapter 6, Energy Estimation and Optimization for Piecewise Regular Processor Arrays,
pp. 107-126. Number 20 in Signal Processing and Communications, Marcel Dekker, New York, USA, 2004.
[Further information][BibTeX]
6
inproceedings
Frank Hannig and Jürgen Teich.
Energy Estimation for Piecewise Regular Processor Arrays.
In Proceedings of the Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS),
Island of Samos, Greece, July 22-25, 2002.
[Further information][PDF][BibTeX]
5
inbook
Marcus Bednara, Frank Hannig, and Jürgen Teich.
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS,
chapter Generation of Distributed Loop Control,
pp. 154-170. Volume 2268 of Lecture Notes in Computer Science (LNCS), Springer, 2002.
[Further information][Digital object identifier][PDF][BibTeX]
4
inproceedings
Marcus Bednara, Frank Hannig, and Jürgen Teich.
Boundary Control: A new Distributed Control Architecture for Space-Time Transformed (VLSI) Processor Arrays.
In Proceedings 35th IEEE Asilomar Conference on Signals, Systems, and Computers,
volume 2, pp. 468-474, Pacific Grove, CA, USA, November 4-7, 2001.
[Further information][Digital object identifier][BibTeX]
3
inproceedings
Frank Hannig and Jürgen Teich.
Design Space Exploration for Massively Parallel Processor Arrays.
In Victor Malyshkin, editor, Parallel Computing Technologies, 6th International Conference, PaCT 2001, Proceedings,
Novosibirsk, Russia, September 3-7, 2001,
volume 2127 of Lecture Notes in Computer Science (LNCS), pp. 51-65, Springer, 2001.
[Further information][Digital object identifier][PDF][BibTeX]
2
masterthesis
Frank Hannig.
Exploration von Raum- und Zeittransformationen für Algorithmen mit uniformen Datenabhängigkeiten.
Diplomarbeit, Universität-GH Paderborn, Fachbereich Elektrotechnik und Informationstechnik, Fachgebiet Datentechnik, October, 2000.
[Further information][BibTeX]
1
masterthesis
Frank Hannig.
Eine Softwareumgebung für neuronale Assoziativspeicher.
Studienarbeit, Universität-GH Paderborn, Fachbereich Elektrotechnik und Informationstechnik, Fachgebiet Schaltungstechnik, April, 1999.
[Further information][BibTeX]
Massively Parallel VLSI Architectures, Project 
