Professor M. Bader (TUM) und Professor J. Teich (FAU) organisieren den Kurs "Multi-Core = Multi-Performance?" auf der Ferienakademie im Sarntal/Südtirol.

Hier finden Sie nähere Informationen zur Ferienakademie

Dr. Martin Daněk hält im Rahmen des Sonderforschungsbereich/Transregio 89 einen Gastvortrag "Implementation of ISE for the micro-threaded model in LEON3 SPARC"

Uhrzeit: 10:00 Uhr
Raum: RZ 2.037

Abstract:
The talk will describe instruction set extensions for a variant of multi-threading called micro-threading for the LEON3 SPAR Cv8 processor. An architecture of the developed processor will be presented and its key blocks described – cache controller, register file, thread scheduler. The processor has been implemented in a Xilinx Virtex2Pro and Virtex5 FPGAs. The extensions will be evaluated in terms of extra resources needed, and the overall performance of the developed processor will be shown for a simple DSP computation typical for embedded systems.

Für den Beitrag "Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays" wird Prof. Teich (2. von rechts) mit dem Best Paper Award geehrt auf der 24th IEEE Int. Conference on Application-specific Systems, Architectures and Processors (ASAP13), Washington DC, USA.

Austin, Texas, USA: Vahid Lari und Frank Hannig präsentierten im Designer Track bei der 50. Design Automation Conference (DAC) ihre Forschungsergebnisse im Bereich Hybrid Prototyping of Tightly-Coupled Processor Arrays for MPSoC Designs, eine Gemeinschaftsarbeit im SFB TRR 89 der Projekte B2: Invasive Tightly-Coupled Processor Arrays, Z2: Validation and Demonstrator, und der Firma Synopsys, Inc.

Professor Klaus Schneider von der Universität Kaiserslautern hält im Rahmen des Sonderforschungsbereich/Transregio 89 den Gastvortrag "Using Synchronous Models for the Design of Parallel Embedded Systems".

Uhrzeit: 10:00 Uhr
Raum: RZ 2.037

Abstract:
To meet required real-time constraints, modern embedded systems have to perform many tasks in parallel and therefore require the modeling of concurrent systems with an adequate notion of time. To this end, several models of computation (MoCs) have been defined that determine why (causality), when (time), which atomic action of the system is executed. The most important classes of MoCs are event-triggered, time/clock-triggered, and data-driven MoCs that have their on advantages and disadvantages. This talk gives an overview on the design flow used in the Averest system developed at the University of Kaiserslautern. The heart of this design flow is a synchronous (clock-driven) MoC which is used for modeling, simulation, and formal verification. The use of a synchronous MoC offers many advantages for these early design phases. For the synthesis, however, it is for some target architectures difficult to maintain the synchronous MoC, and therefore transformations are applied to translate the original models into other MoCs. In particular, we consider transformations that allow developers to desynchronize the system into asynchronous components which is a new technique to synthesize distributed/multithreaded systems from verified synchronous models.

Professor Theo Ungerer von der Universität Augsburg hält im Rahmen des Sonderforschungsbereich/Transregio 89 den Gastvortrag "Hardware and System Software Requirements for Multi-core Deployment in Hard Real-time Systems".

Zeit: 14:00 Uhr
Raum: RZ 2.037

Abstract:
Providing higher performance than state-of-the-art embedded processors can deliver today will increase safety, comfort, number and quality of services, while also lowering emissions as well as fuel demands for automotive, avionic and automation applications. Such a demand for increased computational performance is widespread among European key industries. Engineers who design hard real-time embedded systems in such embedded domains express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelising hard real-time applications and running them on an embedded multi-core processor, which enables combining the requirements for high-performance with time-predictable execution. The talk will discuss results of the EC FP-7 project MERASA (Multi-Core Execution of Hard Real-Time Applications Supporting Analysability, 2007-2011) and objectives and preliminary results of the successor project parMERASA (Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability, starting Oct. 1, 2011). Both projects target timing analysable systems of parallel hard real-time applications running on a scalable multi-core processor. MERASA delivered a fully timing analysable four-core SMT processor FPGA prototype together with adapted system software and WCET tools, running a parallelised version of a Honeywell International autonomous flying vehicle code as demonstrator. parMERASA shifts its objectives even more towards parallelisation of hard real-time software. To this end application companies of avionics, automotive, and construction machinery domains cooperate with tool developers and multi-core architects.

Herr Richard Membarth hat am 02.05.2013 sein Promotionsverfahren mit dem Promotionsvortrag
"Code Generation for GPU Accelerators from a Domain-Specific Language for Medical Imaging"
abgeschlossen.

Am Tag der Informatik 2013 der Friedrich-Alexander-Universität Erlangen-Nürnberg hat Professor Dr.-Ing. Michael Glaß seine Antrittsvorlesung gehalten. Als zentraler Forschungsaspekt seiner Professur für Dependable Embedded Systems sieht er die Fragestellung, wie eingebettete Systeme, während sie stetig kleiner, günstiger und leistungsfähiger werden auch zuverlässig entworfen werden können.

Professor Glaß legt dazu dar, dass die klassische Betrachtung der Zuverlässigkeit eines Gesamtsystem an Hand der Badewannenkurve auf Grund der gestiegenen Komplexität nicht mehr ausreicht, sondern bereits früh in der Entwurfsphase geeignete Maßnahmen ergriffen werden müssen, um eine angestrebte Zuverlässigkeit oder Verfügbarkeit zu erreichen. Hierzu sind automatische Werkzeuge nötig, die Mittel zur Zuverlässigkeitssteigerung bereits beim Entwurf eines Systems berücksichtigen können und deren Auswirkung auf die Lebensdauer der zukünftigen Systeme abschätzen können.

Da hierzu die Berücksichtigung konkreter Fehlermodi wie NBTI nötig ist, das System im frühen Entwurf jedoch erst abstrakt modelliert vorliegt, müssen hierzu geeignete Verfahren zur Abschätzung der Auswirkungen dieser Fehler entwickelt werden. Wir wünschen Professor Glaß dabei viel Erfolg und exzellente Ideen.

Der Tag der Informatik wurde abgerundet durch spannende Fachvorträge von Prof. Reinhard Wilhelm, der die Herausforderungen der WCET-Analyse auf Multi Core-Architekturen vorstellte, sowie von Prof. Samarjit Chakraborty mit einem Fachvortrag zu den spezifischen Problemen bei der Entwicklung von Cyber-Physical Systems.

Professor Teich hält auf dem Workshop GNARP 2013 (The 20^th annual ASCI Computing Workshop) in Soesterberg, Niederlande die Keynote "Invasive Computing - The Quest for Many-Core Efficiency and Predictability".

Abstract:
Technology roadmaps foresee 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of multiple concurrent applications can obviously not be organized in a fully centralized way any more as it is done today.

In this talk, we present a novel paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs called "Invasive Computing".

The main goal of "Invasive Computing" is to provide scalable efficiency and at the same time more predictability of parallel computing on multi-core systems including execution time, power and safety aspects. Conceptually, efficiency may be raised if temporal computational needs of an application may be translated into a dynamic reservation of exclusive resources. The result of an invasion phase is a so-called claim of resources. After termination of computational demanding phase, the application may then release the resources again back to the pool in a phase called retreat. Now, through the exclusiveness of provided resources including not only processors, but also memory access and communication bandwidth on a network on chip, a much higher predictability of non-functional properties becomes possible as well.

In the talk, we provide a first language definition and for invasive computing
based on X10 as developed by IBM. Moreover, we will show how invasive programs may be efficiently simulated so to have a testbed for a) invasive application developers, b) resource-aware programming, and c) design space exploration of architectural tradeoffs such as numbers and types of processors, and memory organization.

Finally, a real-time video application is used to show that predictable throughput processing may be achieved on invasive massively parallel target architectures called tightly-coupled processor arrays (TCPAs) even for varying number of available processors at run-time by exploiting and proposing a claim-dependent selection of the video processing algorithm to be executed as a QoS tradeoff with image quality.

Professor Teich wurde eingeladen, am 24.04.2013 an der Universität Amsterdam den Vortrag "More Cores = Less Predictability?" zu halten.

Abstract:
Multi-core technology has become affordable and is offering enourmous opportunities not only with respect to high speed processing data processing, but also for power savings and other objectives.

However, in emerging application domains such as embedded data and reactive processing, maximizing average performance for which these systems have been typically designed for, is not at all the goal. For hard deadline or guaranteed throughput processing, it turns out that available architectures and tools for their programming may introduce a worse predictability than single core systems due to the interference of multiple applications or threads on the same
and neighbor cores sharing common resources such as memory, cache, and due to affects resulting from OS service levels such as thread schedulers.

We propose a new paradigm called "invasive computing" and show how to achieve the required predictability for multi-core processing im embedded systems by providing resource isolation on demand. Fundamental changes involve language, compiler, and architecture design.

Professor Teich hält auf dem Innovation Forum Smart Systems | Embedded 2013 in München den Vortrag "More Cores = Less Predictability?".
Veranstalter des Forums ist das Bavarian Information and Communication Technology Cluster (BICCNet).

Weitere Informationen finden Sie hier: Innovation Forum Smart Systems | Embedded 2013

Abstract:
Multi-core technology has become affordable and is offering enourmous opportunities not only with respect to high speed processing data processing, but also for power savings and other objectives.
However, in emerging application domains such as embedded data and reactive processing, maximizing average performance for which these systems have been typically designed for, is not at all the goal. For hard deadline or guaranteed throughput processing, it turns out that available architectures and tools for their programming may introduce a worse predictability than single core systems due to the interference of multiple applications or threads on the same and neighbor cores sharing common resources such as memory, cache, and due to affects resulting from OS service levels such as thread schedulers.
We propose a new paradigm called "invasive computing" and show how to achieve the required predictability for multi-core processing im embedded systems by providing resource isolation on demand. Fundamental changes involve language, compiler, and architecture design.

Grenoble, France: Invasive Computing was represented with multiple contributions at DATE 2013. Amongst technical presentations, Vahid Lari (FAU) had a demonstration at DATE 2013 University Booth on "Resource-aware Video Processing on Tightly-Coupled Processor Arrays". Here, a prototype of a 5x5 tightly-coupled processor array (TCPA) was demonstrated using a Synopsys CHIPit prototyping platform. The demonstration shows how an invasive image processing application can adapt its quality of image filtering while keeping a fixed level of output throughput (as an application requirement). More specific, an input video stream is fed to the CHIPit system, through a DVI extension board, and processed by the TCPA and then, the output is shown on a display. The targeted applications on the invasive TCPA prototype are several real-time 1-D and 2-D image filters on a streaming input video. Here, based on the number of available PEs in the TCPA, a suitable 2-D edge detection or Gaussian filtering kernel is loaded.

Am 8. März feierte unser Lehrstuhl seinen 10ten Geburtstag mit einem Festsymposium.

Nach der Begrüßung durch Professor Jürgen Teich, dem Grußwort des Vizepräsidenten der Universität, Professor Joachim Hornegger, und dem Festvortrag von Professor Franz-Josef Rammig aus Paderborn folgten fünf spannende Fachvorträge von Professor Christian Haubelt, Dr. Thilo Streichert, Professor Christophe Bobda, Dr. Dirk Koch und Dr. Sanaz Mostaghim.
Mit Wissenswertem über Erlangen und so mancher Anekdote aus den Anfängen der Informatik 12 rundete Dr. Frank Hannig das Symposium ab.
Details finden Sie im Programm.
Viele Gäste aus Universität, Industrie, den Reihen der Alumni und unsere Studenten nutzten die Pause und den Empfang zum Gedankenaustausch.

Herzlichen Dank noch einmal allen Gastrednern und Beteiligten für diesen gelungenen Tag.

Das Sympsium in Bildern:

Dr. Frank Hannig hielt beim 10th Workshop on Optimizations for DSP and Embedded Systems (ODES) in Shenzhen, China den Keynote-Vortrag "Resource-Aware Computing on Domain-Specific Accelerators"

Abstract
The continuous progress in semiconductor technology allows for more and more complex processors architectures. The downside of these technological advances is that computing has hit already a power and complexity wall. These days, energy efficiency has become more important than pure computing power. That means, in order to scale computing performance in the future, systems´ energy efficiency has to be significantly improved. The design of heterogeneous hardware with different specialized resources, such as accelerators dedicated for one application domain is a promising solution to address this challenge.

In this talk, I introduce a class of domain-specific programmable accelerators. In addition, techniques for increasing their energy efficiency as well as
resource-aware programming approaches and symbolic mapping techniques for such massively parallel systems are presented.

Invasive Computing has received considerable attention in the HPC community. A contribution by Michael Bader, Hans-Joachim Bungartz, and Martin Schreiber has found mentioning in a news article of HPC Wire under
http://www.hpcwire.com/hpcwire/2013-02-21/the_week_in_hpc_research.html?page=4

Professor Teich hielt auf der Konferenz ARCS 2013 in Prag die Keynote "Invasive Computing - The Quest for Many-Core Efficiency and Predictability"

Abstract
Technology roadmaps foresee 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of multiple concurrent applications can obviously not be organized in a fully centralized way any more as it is done today.
In this talk, we present a novel paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs called "Invasive Computing".

The main goal of "Invasive Computing" is to provide scalable efficiency and at the same time more predictability of parallel computing on multi-core systems including execution time, power and safety aspects. Conceptually, efficiency may be raised if temporal computational needs of an application may be translated into a dynamic reservation of exclusive resources.
The result of an invasion phase is a so-called claim of resources. After termination of computational demanding phase, the application may then release the resources again back to the pool in a phase called retreat. Now, through the exclusiveness of provided resources including not only processors, but also memory access and communication bandwidth on a network on chip, a much higher predictability of non-functional properties becomes possible as well.

In the talk, we provide a first language definition and for invasive computing based on X10 as developed by IBM. Moreover, we will show how invasive programs may be efficiently simulated so to have a testbed for a) invasive application developers, b) resource-aware programming, and c) design space exploration of architectural tradeoffs such as numbers and types of processors, and memory organization.

Finally, a real-time video application is used to show that predictable throughput processing may be achieved on invasive massively parallel target architectures called tightly-coupled processor arrays (TCPAs) even for varying number of available processors at run-time by exploiting and proposing a claim-dependent selection of the video processing algorithm to be executed as a QoS tradeoff with image quality.

Im Rahmen des Dagstuhl-Seminars "Multicore Enablement for Embedded and Cyber Physical Systems" hielt Herr Professor Teich den Vortrag "Safe(r) Loop Computations on Multi-Cores".

Prof. Wanka vom Lehrstuhl für Informatik 12 ist seit dem 1. Januar 2013 für drei Jahre Mitglied im Leitungsgremium der Fachgruppe Parallel -Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS) im Fachbereich Technische Informatik der Gesellschaft für Informatik.