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Lehrstuhl für Informatik 12
FPGA-Online Advanced Course (VHDL)
Department Informatik  >  Informatik 12  >  Lehre  >  FPGA-Online Advanced Course (VHDL)

FPGA-Online Advanced Course (VHDL)

Lecturer Prof. J. Teich, Dr. D. Ziener, T. Ziermann
Scope/Credit Virtual Lab 2.5 ECTS,
Computer Science, IuK, SIM, Medical and Health Engineering, Mechatronics, Computational Engineering, and interested Listeners
Lecture, location and time
Anytime using the online lab


Registration open until 15.04.2012. Use the vhb-website to register.

Course content:

In the course "FPGA-Online Advanced Course with VHDL" you will learn advanced techniques to program an FPGA. These techniques include: Script-based synthesis, place and route, and loading of the FPGA, the use of the high speed interface PCI Express, and the use of special hardware blocks on the FPGA. The techniques are applied on the example application of hardware accelerated video compression and decompression.
The experimental setup consists out of a standard PC with a build-in XUPV5-platform. The board and the PC are connected over the PCI Express bus. With this connection, a high speed hardware-software communication is possible that enables us to send a video stream in real-time to the FPGA and back. On the FPGA, the video stream is encoded using different techniques in real-time. Since we are using a specialized video codec, the stream needs to be decoded on the board. It is then send back to the PC, where we can display the result.
Lab setup

Learning Objectives

  • Learn how to build an advanced design for a high-performance FPGA. As an example throughout the lab, a modular real-time video compression system based on a Xilinx Virtex 5 FPGA is build.
  • Get familiar with the Hardware/Software communication PCI Express, which allows a high-speed communication between a standard PC and an FPGA.
  • Use the hard-wired resources such as XtremeDSP or BlockRAM to speed up your FPGA design.

Outline:

  1. Introduction to the lab environment
  2. Getting started with the Xilinx design flow
  3. Generating and customizing a PCIe-interface with the Xilinx Core Generator
  4. Transmitting pictures to the FPGA and back
  5. Creating a simple JPEG en/decoder
  6. Creating a JPEG en/decoder using extremeDSP
  7. Creating the final video coder

Exam:

There will be an oral exam at the end of the semester by Dr.-Ing. Daniel Ziener.

Documents:

Useful links:

  Impressum Stand: 20 March 2012.   T.Z.